Commit Graph

34 Commits

Author SHA1 Message Date
Linus Torvalds 6f630784cc This time around we have 4 lines of diff in the core framework, removing a
function that isn't used anymore. Otherwise the main new thing for the common
 clk framework is that it is selectable in the Kconfig language now. Hopefully
 this will let clk drivers and clk consumers be testable on more than the
 architectures that support the clk framework. The goal is to introduce some
 Kunit tests for the framework.
 
 Outside of the core framework we have the usual set of various driver updates
 and non-critical fixes. The dirstat shows that the new Baikal-T1 driver is the
 largest addition this time around in terms of lines of code. After that the x86
 (Intel), Qualcomm, and Mediatek drivers introduce many lines to support new or
 upcoming SoCs. After that the dirstat shows the usual suspects working on their
 SoC support by fixing minor bugs, correcting data and converting some of their
 DT bindings to YAML.
 
 Core:
  - Allow the COMMON_CLK config to be selectable
 
 New Drivers:
  - Clk driver for Baikal-T1 SoCs
  - Mediatek MT6765 clock support
  - Support for Intel Agilex clks
  - Add support for X1830 and X1000 Ingenic SoC clk controllers
  - Add support for the new Renesas RZ/G1H (R8A7742) SoC
  - Add support for Qualcomm's MSM8939 Generic Clock Controller
 
 Updates:
  - Support IDT VersaClock 5P49V5925
  - Bunch of updates for HSDK clock generation unit (CGU) driver
  - Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs
  - Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver
  - Enable supply regulators for GPU gdscs on Qualcomm SoCs
  - Add support for Si5342, Si5344 and Si5345 chips
  - Support custom flags in Xilinx zynq firmware
  - Various small fixes to the Xilinx clk driver
  - A single minor rounding fix for the legacy Allwinner clock support
  - A few patches from Abel Vesa as preparation of adding audiomix clock support
    on i.MX
  - A couple of cleanups from Anson Huang for i.MX clk-sscg-pll and clk-pllv3
    drivers
  - Drop dependency on ARM64 for i.MX8M clock driver, to support aarch32 mode on
    aarch64 hardware
  - A series from Peng Fan to improve i.MX8M clock drivers, using composite
    clock for core and bus clk slice
  - Set a better parent clock for flexcan on i.MX6UL to support CiA102 defined
    bit rates
  - A couple changes for EMC frequency scaling on Tegra210
  - Support for CPU frequency scaling on Tegra20/Tegra30
  - New clk gate for CSI test pattern generator on Tegra210
  - Regression fixes for Samsung exynos542x and exynos5433 SoCs
  - Use of fallthrough; attribute for Samsung s3c24xx
  - Updates and fixup HDMI and video clocks on Meson8b
  - Fixup reset polarity on Meson8b
  - Fix GPU glitch free mux switch on Meson gx and g12
  - A minor fix for the currently unused suspend/resume handling on Renesas RZ/A1 and RZ/A2
  - Two more conversions of Renesas DT bindings to json-schema
  - Add support for the USB 2.0 clock selector on Renesas R-Car M3-W+
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "This time around we have four lines of diff in the core framework,
  removing a function that isn't used anymore. Otherwise the main new
  thing for the common clk framework is that it is selectable in the
  Kconfig language now. Hopefully this will let clk drivers and clk
  consumers be testable on more than the architectures that support the
  clk framework. The goal is to introduce some Kunit tests for the
  framework.

  Outside of the core framework we have the usual set of various driver
  updates and non-critical fixes. The dirstat shows that the new
  Baikal-T1 driver is the largest addition this time around in terms of
  lines of code. After that the x86 (Intel), Qualcomm, and Mediatek
  drivers introduce many lines to support new or upcoming SoCs. After
  that the dirstat shows the usual suspects working on their SoC support
  by fixing minor bugs, correcting data and converting some of their DT
  bindings to YAML.

  Core:
   - Allow the COMMON_CLK config to be selectable

  New Drivers:
   - Clk driver for Baikal-T1 SoCs
   - Mediatek MT6765 clock support
   - Support for Intel Agilex clks
   - Add support for X1830 and X1000 Ingenic SoC clk controllers
   - Add support for the new Renesas RZ/G1H (R8A7742) SoC
   - Add support for Qualcomm's MSM8939 Generic Clock Controller

  Updates:
   - Support IDT VersaClock 5P49V5925
   - Bunch of updates for HSDK clock generation unit (CGU) driver
   - Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs
   - Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver
   - Enable supply regulators for GPU gdscs on Qualcomm SoCs
   - Add support for Si5342, Si5344 and Si5345 chips
   - Support custom flags in Xilinx zynq firmware
   - Various small fixes to the Xilinx clk driver
   - A single minor rounding fix for the legacy Allwinner clock support
   - A few patches from Abel Vesa as preparation of adding audiomix
     clock support on i.MX
   - A couple of cleanups from Anson Huang for i.MX clk-sscg-pll and
     clk-pllv3 drivers
   - Drop dependency on ARM64 for i.MX8M clock driver, to support
     aarch32 mode on aarch64 hardware
   - A series from Peng Fan to improve i.MX8M clock drivers, using
     composite clock for core and bus clk slice
   - Set a better parent clock for flexcan on i.MX6UL to support CiA102
     defined bit rates
   - A couple changes for EMC frequency scaling on Tegra210
   - Support for CPU frequency scaling on Tegra20/Tegra30
   - New clk gate for CSI test pattern generator on Tegra210
   - Regression fixes for Samsung exynos542x and exynos5433 SoCs
   - Use of fallthrough; attribute for Samsung s3c24xx
   - Updates and fixup HDMI and video clocks on Meson8b
   - Fixup reset polarity on Meson8b
   - Fix GPU glitch free mux switch on Meson gx and g12
   - A minor fix for the currently unused suspend/resume handling on
     Renesas RZ/A1 and RZ/A2
   - Two more conversions of Renesas DT bindings to json-schema
   - Add support for the USB 2.0 clock selector on Renesas R-Car M3-W+"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (155 commits)
  clk: mediatek: Remove ifr{0,1}_cfg_regs structures
  clk: baikal-t1: remove redundant assignment to variable 'divider'
  clk: baikal-t1: fix spelling mistake "Uncompatible" -> "Incompatible"
  dt-bindings: clock: Add a missing include to MMP Audio Clock binding
  dt: Add bindings for IDT VersaClock 5P49V5925
  clk: vc5: Add support for IDT VersaClock 5P49V6965
  clk: Add Baikal-T1 CCU Dividers driver
  clk: Add Baikal-T1 CCU PLLs driver
  dt-bindings: clk: Add Baikal-T1 CCU Dividers binding
  dt-bindings: clk: Add Baikal-T1 CCU PLLs binding
  clk: mediatek: assign the initial value to clk_init_data of mtk_mux
  clk: mediatek: Add MT6765 clock support
  clk: mediatek: add mt6765 clock IDs
  dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC
  dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC
  dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC
  CLK: HSDK: CGU: add support for 148.5MHz clock
  CLK: HSDK: CGU: support PLL bypassing
  CLK: HSDK: CGU: check if PLL is bypassed first
  clk: clk-si5341: Add support for the Si5345 series
  ...
2020-06-10 11:42:19 -07:00
Chunyan Zhang 2c1c969645 clk: sprd: add mipi_csi_xx gate clocks
mipi_csi_xx clocks are used by camera sensors.

Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Link: https://lkml.kernel.org/r/20200527053638.31439-5-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26 23:41:14 -07:00
Chunyan Zhang 8b4f6b8d59 clk: sprd: check its parent status before reading gate clock
Some clocks only can be accessed if their parent is enabled. mipi_csi_xx
clocks on SC9863A are an examples. We have to ensure the parent clock is
enabled when reading those clocks.

Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Link: https://lkml.kernel.org/r/20200527053638.31439-2-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26 23:41:14 -07:00
Chunyan Zhang c2f30986d4 clk: sprd: return correct type of value for _sprd_pll_recalc_rate
The function _sprd_pll_recalc_rate() defines return value to unsigned
long, but it would return a negative value when malloc fail, changing
to return its parent_rate makes more sense, since if the callback
.recalc_rate() is not set, the framework returns the parent_rate as
well.

Fixes: 3e37b00558 ("clk: sprd: add adjustable pll support")
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Link: https://lkml.kernel.org/r/20200519030036.1785-2-zhang.lyra@gmail.com
Reviewed-by: Baolin Wang <baolin.wang7@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26 20:14:56 -07:00
Chunyan Zhang 3aff9b5492 clk: sprd: mark the local clock symbols static
There's a few pll gate clocks which were not marked with static, and
those clock are used only in the current file, so add static key word
for them.

Fixes: 0e4b8a2349 ("clk: sprd: add clocks support for SC9863A")
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Link: https://lkml.kernel.org/r/20200519030036.1785-1-zhang.lyra@gmail.com
Reviewed-by: Baolin Wang <baolin.wang7@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26 20:14:46 -07:00
Chunyan Zhang ca6df49d62 clk: sprd: don't gate uart console clock
Don't gate uart1_eb which provides console clock, gating that clock would
make serial stop working if serial driver didn't enable that explicitly.

Fixes: 0e4b8a2349 ("clk: sprd: add clocks support for SC9863A")
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Link: https://lkml.kernel.org/r/20200408020234.31764-1-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-04-13 12:20:07 -07:00
Chunyan Zhang 39d1c90665 clk: sprd: fix to get a correct ibias of pll
The current driver is getting a wrong ibias index of pll clocks from
number 1. This patch fix that issue, then getting ibias index from 0.

Fixes: 3e37b00558 ("clk: sprd: add adjustable pll support")
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Link: https://lkml.kernel.org/r/20200330021640.14133-1-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-04-02 18:07:58 -07:00
Chunyan Zhang 0e4b8a2349 clk: sprd: add clocks support for SC9863A
Add the list of clocks for the Unisoc SC9863A, along with clock
initialization.

Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Link: https://lkml.kernel.org/r/20200304072730.9193-8-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-24 19:03:57 -07:00
Chunyan Zhang f95e8c7923 clk: sprd: support to get regmap from parent node
Some SC9863a clock nodes would be the child of a syscon node, clocks can
use the regmap of syscon device directly for this kind of cases.

Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Link: https://lkml.kernel.org/r/20200304072730.9193-7-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-24 19:03:57 -07:00
Chunyan Zhang ea8ca3109d clk: sprd: Add macros for referencing parents without strings
With the new clk parenting code, clk_init_data was expanded to include
.parent_hws and .parent_data, for clk drivers to specify parents without
name strings of clocks.

Also some macros were added for using these two items to reference
clock parents. Based on that to expand macros for sprd clocks:

- SPRD_*_DATA, take an array of struct clk_parent_data * as its parents
  which should be a combination of .fw_name (devicetree clock-names),
  .hw (pointers to a local struct clk_hw).

- SPRD_*_HW, take a local struct clk_hw pointer, instead of a string, as
  its parent.

- SPRD_*_FW_NAME, take a string of clock-names decleared in the device
  tree as the clock parent.

Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Link: https://lkml.kernel.org/r/20200304072730.9193-6-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-24 19:03:57 -07:00
Xiaolong Zhang 187e5cd2d1 clk: sprd: add gate for pll clocks
Some sprd's gate clocks are used to the switch of pll, which
need to wait a certain time for stable after being enabled.

Signed-off-by: Xiaolong Zhang <xiaolong.zhang@unisoc.com>
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Link: https://lkml.kernel.org/r/20200304072730.9193-2-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-24 19:03:56 -07:00
Stephen Boyd dabedfede3 Merge branches 'clk-gpio-flags', 'clk-tegra', 'clk-rockchip', 'clk-sprd' and 'clk-pxa' into clk-next
- Make gpio gate clks propagate rate setting up to parent

* clk-gpio-flags:
  clk: clk-gpio: propagate rate change to parent

* clk-tegra: (23 commits)
  clk: tegra: Use match_string() helper to simplify the code
  clk: tegra: Fix build error without CONFIG_PM_SLEEP
  clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP
  clk: tegra: Optimize PLLX restore on Tegra20/30
  clk: tegra: Add suspend and resume support on Tegra210
  clk: tegra: Share clk and rst register defines with Tegra clock driver
  clk: tegra: Use fence_udelay() during PLLU init
  clk: tegra: clk-dfll: Add suspend and resume support
  clk: tegra: clk-super: Add restore-context support
  clk: tegra: clk-super: Fix to enable PLLP branches to CPU
  clk: tegra: periph: Add restore_context support
  clk: tegra: Support for OSC context save and restore
  clk: tegra: pll: Save and restore pll context
  clk: tegra: pllout: Save and restore pllout context
  clk: tegra: divider: Save and restore divider rate
  clk: tegra: Reimplement SOR clocks on Tegra210
  clk: tegra: Reimplement SOR clock on Tegra124
  clk: tegra: Rename sor0_lvds to sor0_out
  clk: tegra: Move SOR0 implementation to Tegra124
  clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRC
  ...

* clk-rockchip:
  clk: rockchip: protect the pclk_usb_grf as critical on px30
  clk: rockchip: add video-related niu clocks as critical on px30
  clk: rockchip: move px30 critical clocks to correct clock controller
  clk: rockchip: Add div50 clocks for px30 sdmmc, emmc, sdio and nandc
  clk: rockchip: Add div50 clock-ids for sdmmc on px30 and nandc
  clk: rockchip: make clk_half_divider_ops static

* clk-sprd:
  clk: sprd: Use IS_ERR() to validate the return value of syscon_regmap_lookup_by_phandle()

* clk-pxa:
  clk: pxa: fix one of the pxa RTC clocks
2019-11-27 08:15:00 -08:00
Baolin Wang 9629dbdabd clk: sprd: Use IS_ERR() to validate the return value of syscon_regmap_lookup_by_phandle()
The syscon_regmap_lookup_by_phandle() will never return NULL, thus use
IS_ERR() to validate the return value instead of IS_ERR_OR_NULL().

Fixes: d41f59fd92 ("clk: sprd: Add common infrastructure")
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Link: https://lkml.kernel.org/r/1995139bee5248ff3e9d46dc715968f212cfc4cc.1570520268.git.baolin.wang@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-13 14:59:46 -08:00
Baolin Wang 793ee798cc clk: sprd: Change to use devm_platform_ioremap_resource()
Use the new helper that wraps the calls to platform_get_resource()
and devm_ioremap_resource() together, which can simpify the code.

Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Link: https://lkml.kernel.org/r/841d26a2adb4bf3b4423f82a41dd3f1346413db6.1570520268.git.baolin.wang@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16 16:18:30 -07:00
Linus Torvalds a703d279c5 We have a small collection of core framework updates this time, mostly around
clk registration by clk providers and debugfs "nice to haves" for rate
 constraints. I'll highlight that we're now setting the clk_init_data pointer
 inside struct clk_hw to NULL during clk_register(), which may break some
 drivers that thought they could use that pointer during normal operations. That
 change has been sitting in next for a while now but maybe something is still
 broken. We'l see. Other than that the core framework changes aren't invasive
 and they're fixing bugs, simplifying, and making things better.
 
 On the clk driver side we got the usual addition of new SoC support, new
 features for existing drivers, and bug fixes scattered throughout. The biggest
 diffstat is the Amlogic driver that gained CPU clk support in addition to
 migrating to the new way of specifying clk parents. After that the Qualcomm,
 i.MX, Mediatek, and Rockchip clk drivers got support for various new SoCs and
 clock controllers from those vendors.
 
 Core:
  - Drop NULL checks in clk debugfs
  - Add min/max rates to clk debugfs
  - Set clk_init_data pointer inside clk_hw to NULL after registration
  - Make clk_bulk_get_all() return an 'id' corresponding to clock-names
  - Evict parents from parent cache when they're unregistered
 
 New Drivers:
  - Add clock driver for i.MX8MN SoCs
  - Support aspeed AST2600 SoCs
  - Support for Mediatek MT6779 SoCs
  - Support qcom SM8150 GCC and RPMh clks
  - Support qcom QCS404 WCSS clks
  - Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807)
  - Addition of clock driver for Rockchip rk3308 SoCs
 
 Updates:
  - Add regulator support to the cdce925 clk driver
  - Add support for Raspberry Pi 4 bcm2711 SoCs
  - Add SDIO gate support to aspeed driver
  - Add missing of_node_put() calls in various clk drivers
  - Migrate Amlogic driver to new clock parent description method
  - Add DVFS support to Amlogic Meson g12
  - Add Amlogic Meson g12a reset support to the axg audio clock controller
  - Add sm1 support to the Amlogic Meson g12a clock controller
  - Switch i.MX8MM clock driver to platform driver
  - Add Hifi4 DSP related clocks for i.MX8QXP SoC
  - Fix Audio PLL setting and parent clock for USB
  - Misc i.MX8 clock driver improvements and corrections
  - Set floor ops for Qualcomm SD clks so that rounding works
  - Fix "always-on" Clock Domains on Renesas R-Car M1A, RZ/A1, RZ/A2, and RZ/N1
  - Enable the Allwinner V3 SoC and fix the i2s clock for H6
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "We have a small collection of core framework updates this time, mostly
  around clk registration by clk providers and debugfs "nice to haves"
  for rate constraints. I'll highlight that we're now setting the
  clk_init_data pointer inside struct clk_hw to NULL during
  clk_register(), which may break some drivers that thought they could
  use that pointer during normal operations. That change has been
  sitting in next for a while now but maybe something is still broken.
  We'l see. Other than that the core framework changes aren't invasive
  and they're fixing bugs, simplifying, and making things better.

  On the clk driver side we got the usual addition of new SoC support,
  new features for existing drivers, and bug fixes scattered throughout.
  The biggest diffstat is the Amlogic driver that gained CPU clk support
  in addition to migrating to the new way of specifying clk parents.
  After that the Qualcomm, i.MX, Mediatek, and Rockchip clk drivers got
  support for various new SoCs and clock controllers from those vendors.

  Core:
   - Drop NULL checks in clk debugfs
   - Add min/max rates to clk debugfs
   - Set clk_init_data pointer inside clk_hw to NULL after registration
   - Make clk_bulk_get_all() return an 'id' corresponding to clock-names
   - Evict parents from parent cache when they're unregistered

  New Drivers:
   - Add clock driver for i.MX8MN SoCs
   - Support aspeed AST2600 SoCs
   - Support for Mediatek MT6779 SoCs
   - Support qcom SM8150 GCC and RPMh clks
   - Support qcom QCS404 WCSS clks
   - Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807)
   - Addition of clock driver for Rockchip rk3308 SoCs

  Updates:
   - Add regulator support to the cdce925 clk driver
   - Add support for Raspberry Pi 4 bcm2711 SoCs
   - Add SDIO gate support to aspeed driver
   - Add missing of_node_put() calls in various clk drivers
   - Migrate Amlogic driver to new clock parent description method
   - Add DVFS support to Amlogic Meson g12
   - Add Amlogic Meson g12a reset support to the axg audio clock controller
   - Add sm1 support to the Amlogic Meson g12a clock controller
   - Switch i.MX8MM clock driver to platform driver
   - Add Hifi4 DSP related clocks for i.MX8QXP SoC
   - Fix Audio PLL setting and parent clock for USB
   - Misc i.MX8 clock driver improvements and corrections
   - Set floor ops for Qualcomm SD clks so that rounding works
   - Fix "always-on" Clock Domains on Renesas R-Car M1A, RZ/A1, RZ/A2, and RZ/N1
   - Enable the Allwinner V3 SoC and fix the i2s clock for H6"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits)
  clk: Drop !clk checks in debugfs dumping
  clk: imx: imx8mn: fix pll mux bit
  clk: imx: imx8mm: fix pll mux bit
  clk: imx: clk-pll14xx: unbypass PLL by default
  clk: imx: pll14xx: avoid glitch when set rate
  clk: mvebu: ap80x: add AP807 clock support
  clk: mvebu: ap806: Prepare the introduction of AP807 clock support
  clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver
  clk: mvebu: ap806: be more explicit on what SaR is
  clk: mvebu: ap80x-cpu: add AP807 CPU clock support
  clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock
  dt-bindings: ap806: Document AP807 clock compatible
  dt-bindings: ap80x: Document AP807 CPU clock compatible
  clk: sprd: add missing kfree
  clk: at91: allow 24 Mhz clock as input for PLL
  clk: Make clk_bulk_get_all() return a valid "id"
  clk: actions: Fix factor clk struct member access
  clk: qcom: rcg: Return failure for RCG update
  clk: remove extra ---help--- tags in Kconfig
  clk: add include guard to clk-conf.h
  ...
2019-09-20 15:45:07 -07:00
Stephen Boyd ebd47c8434 Merge branches 'clk-bulk-fix', 'clk-at91' and 'clk-sprd' into clk-next
- Make clk_bulk_get_all() return an 'id' corresponding to clock-names

* clk-bulk-fix:
  clk: Make clk_bulk_get_all() return a valid "id"

* clk-at91:
  clk: at91: allow 24 Mhz clock as input for PLL
  clk: at91: select parent if main oscillator or bypass is enabled
  clk: at91: fix update bit maps on CFG_MOR write

* clk-sprd:
  clk: sprd: add missing kfree
2019-09-19 15:31:59 -07:00
Chunyan Zhang 5e75ea9c67 clk: sprd: add missing kfree
The number of config registers for different pll clocks probably are not
same, so we have to use malloc, and should free the memory before return.

Fixes: 3e37b00558 ("clk: sprd: add adjustable pll support")
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: Chunyan Zhang <zhang.lyra@gmail.com>
Link: https://lkml.kernel.org/r/20190905103009.27166-1-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17 22:01:02 -07:00
Stephen Boyd f6c90df8e7 clk: sprd: Don't reference clk_init_data after registration
A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.

Cc: Chunyan Zhang <zhang.chunyan@linaro.org>
Cc: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190731193517.237136-8-sboyd@kernel.org
Acked-by: Baolin Wang <baolin.wang@linaro.org>
Acked-by: Chunyan Zhang <zhang.chunyan@linaro.org>
2019-08-16 10:20:07 -07:00
Chunyan Zhang c9a67cbb51 clk: sprd: Select REGMAP_MMIO to avoid compile errors
Make REGMAP_MMIO selected to avoid undefined reference to regmap symbols.

Fixes: d41f59fd92 ("clk: sprd: Add common infrastructure")
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-07-22 14:54:26 -07:00
Linus Torvalds 916f562fb2 This round of clk driver and framework updates is heavy on the driver update
side. The two main highlights in the core framework are the addition of an bulk
 clk_get API that handles optional clks and an extra debugfs file that tells the
 developer about the current parent of a clk.
 
 The driver updates are dominated by i.MX in the diffstat, but that is mostly
 because that SoC has started converting to the clk_hw style of clk
 registration. The next big update is in the Amlogic meson clk driver that
 gained some support for audio, cpu, and temperature clks while fixing some PLL
 issues. Finally, the biggest thing that stands out is the conversion of a large
 part of the Allwinner sunxi-ng driver to the new clk parent scheme that uses
 less strings and more pointer comparisons to match clk parents and children up.
 
 In general, it looks like we have a lot of little fixes and tweaks here and
 there to clk data along with the normal addition of a handful of new drivers
 and a couple new core framework features.
 
 Core:
  - Add a 'clk_parent' file in clk debugfs
  - Add a clk_bulk_get_optional() API (with devm too)
 
 New Drivers:
  - Support gated clk controller on MIPS based BCM63XX SoCs
  - Support SiLabs Si5341 and Si5340 chips
  - Support for CPU clks on Raspberry Pi devices
  - Audsys clock driver for MediaTek MT8516 SoCs
 
 Updates:
  - Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme
  - Small frequency support for SiLabs Si544 chips
  - Slow clk support for AT91 SAM9X60 SoCs
  - Remove dead code in various clk drivers (-Wunused)
  - Support for Marvell 98DX1135 SoCs
  - Get duty cycle of generic pwm clks
  - Improvement in mmc phase calculation and cleanup of some rate defintions
  - Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs
  - Add GPIO, SNVS and GIC clocks for i.MX8 drivers
  - Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock
  - Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting
  - Add clks for new Exynos5422 Dynamic Memory Controller driver
  - Clock definition for Exynos4412 Mali
  - Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3
  - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M
  - Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs
  - TI clock probing done from DT by default instead of firmware
  - Fix Amlogic Meson mpll fractional part and spread sprectrum issues
  - Add Amlogic meson8 audio clocks
  - Add Amlogic g12a temperature sensors clocks
  - Add Amlogic g12a and g12b cpu clocks
  - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N
  - Add CMM (Color Management Module) clocks on Renesas R-Car M3-W
  - Add Clock Domain support on Renesas RZ/N1
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "This round of clk driver and framework updates is heavy on the driver
  update side. The two main highlights in the core framework are the
  addition of an bulk clk_get API that handles optional clks and an
  extra debugfs file that tells the developer about the current parent
  of a clk.

  The driver updates are dominated by i.MX in the diffstat, but that is
  mostly because that SoC has started converting to the clk_hw style of
  clk registration. The next big update is in the Amlogic meson clk
  driver that gained some support for audio, cpu, and temperature clks
  while fixing some PLL issues. Finally, the biggest thing that stands
  out is the conversion of a large part of the Allwinner sunxi-ng driver
  to the new clk parent scheme that uses less strings and more pointer
  comparisons to match clk parents and children up.

  In general, it looks like we have a lot of little fixes and tweaks
  here and there to clk data along with the normal addition of a handful
  of new drivers and a couple new core framework features.

  Core:
   - Add a 'clk_parent' file in clk debugfs
   - Add a clk_bulk_get_optional() API (with devm too)

  New Drivers:
   - Support gated clk controller on MIPS based BCM63XX SoCs
   - Support SiLabs Si5341 and Si5340 chips
   - Support for CPU clks on Raspberry Pi devices
   - Audsys clock driver for MediaTek MT8516 SoCs

  Updates:
   - Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme
   - Small frequency support for SiLabs Si544 chips
   - Slow clk support for AT91 SAM9X60 SoCs
   - Remove dead code in various clk drivers (-Wunused)
   - Support for Marvell 98DX1135 SoCs
   - Get duty cycle of generic pwm clks
   - Improvement in mmc phase calculation and cleanup of some rate defintions
   - Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs
   - Add GPIO, SNVS and GIC clocks for i.MX8 drivers
   - Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock
   - Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting
   - Add clks for new Exynos5422 Dynamic Memory Controller driver
   - Clock definition for Exynos4412 Mali
   - Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3
   - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M
   - Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs
   - TI clock probing done from DT by default instead of firmware
   - Fix Amlogic Meson mpll fractional part and spread sprectrum issues
   - Add Amlogic meson8 audio clocks
   - Add Amlogic g12a temperature sensors clocks
   - Add Amlogic g12a and g12b cpu clocks
   - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N
   - Add CMM (Color Management Module) clocks on Renesas R-Car M3-W
   - Add Clock Domain support on Renesas RZ/N1"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (190 commits)
  clk: consoldiate the __clk_get_hw() declarations
  clk: sprd: Add check for return value of sprd_clk_regmap_init()
  clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK
  clk: Add Si5341/Si5340 driver
  dt-bindings: clock: Add silabs,si5341
  clk: clk-si544: Implement small frequency change support
  clk: add BCM63XX gated clock controller driver
  devicetree: document the BCM63XX gated clock bindings
  clk: at91: sckc: use dedicated functions to unregister clock
  clk: at91: sckc: improve error path for sama5d4 sck registration
  clk: at91: sckc: remove unnecessary line
  clk: at91: sckc: improve error path for sam9x5 sck register
  clk: at91: sckc: add support to free slow clock osclillator
  clk: at91: sckc: add support to free slow rc oscillator
  clk: at91: sckc: add support to free slow oscillator
  clk: rockchip: export HDMIPHY clock on rk3228
  clk: rockchip: add watchdog pclk on rk3328
  clk: rockchip: add clock id for hdmi_phy special clock on rk3228
  clk: rockchip: add clock id for watchdog pclk on rk3328
  clk: at91: sckc: add support for SAM9X60
  ...
2019-07-17 10:07:48 -07:00
Chunyan Zhang c974c48dee clk: sprd: Add check for return value of sprd_clk_regmap_init()
sprd_clk_regmap_init() doesn't always return success, adding check
for its return value should make the code more strong.

Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Reviewed-by: Baolin Wang <baolin.wang@linaro.org>
[sboyd@kernel.org: Add a missing int ret]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27 15:08:29 -07:00
Chunyan Zhang 78f5296951 clk: sprd: Check error only for devm_regmap_init_mmio()
The function devm_regmap_init_mmio() wouldn't return NULL pointer for
now, so only need to ensure the return value is not an error code.

Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Reviewed-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-26 11:15:08 -07:00
Chunyan Zhang 69b39d2503 clk: sprd: Switch from of_iomap() to devm_ioremap_resource()
devm_ioremap_resources() automatically requests resources and devm_ wrappers
do better error handling and unmapping of the I/O region when needed,
that would make drivers more clean and simple.

Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Reviewed-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-26 11:12:50 -07:00
Thomas Gleixner ec8f24b7fa treewide: Add SPDX license identifier - Makefile/Kconfig
Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-21 10:50:46 +02:00
Nishad Kamdar 7a12f838e4 clk: sprd: Use the correct style for SPDX License Identifier
This patch corrects the SPDX License Identifier style
in header files related to Clock Drivers for Spreadtrum SoCs.
For C header files Documentation/process/license-rules.rst
mandates C-like comments (opposed to C source files where
C++ style should be used)

Changes made by using a script provided by Joe Perches here:
https://lkml.org/lkml/2019/2/7/46

Suggested-by: Joe Perches <joe@perches.com>
Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-01 13:01:23 -07:00
Chunyan Zhang b3316a672b clk: sprd: add RTC gate for SC9860
Add a few gate clocks which are used for gating RTC for some
devices on AON area of SC9860.

This patch has been tested on SC9860, with this patch and proper DT
configurations, the watchdog can be initialized and work well.

Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-16 15:53:30 -07:00
Stephen Boyd 716d9b1d4a Merge branch 'clk-divider-container' into clk-next
* clk-divider-container:
  clk: divider: fix incorrect usage of container_of

Plus fixup sprd/div.c to pass the width too.
2018-01-26 16:43:14 -08:00
Chunyan Zhang a6ae1a2948 clk: sprd: add clocks support for SC9860
This patch added the list of clocks for Spreadtrum's SC9860 SoC,
together with clock initialization code.

Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21 15:00:54 -08:00
Chunyan Zhang 3e37b00558 clk: sprd: add adjustable pll support
Introduced a common adjustable pll clock driver for Spreadtrum SoCs.

Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21 15:00:53 -08:00
Chunyan Zhang 4fcba55cc6 clk: sprd: add composite clock support
This patch introduced composite driver for Spreadtrum's SoCs. The
functions of this composite clock simply consist of divider and
mux clocks.

Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21 15:00:52 -08:00
Chunyan Zhang e3f05d3b18 clk: sprd: add divider clock support
This is a feature that can also be found in sprd composite clocks,
provide a bunch of helpers that can be reused later on.

Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21 15:00:52 -08:00
Chunyan Zhang ab73cf2a54 clk: sprd: add mux clock support
This patch adds clock multiplexor support for Spreadtrum platforms,
the mux clocks also can be found in sprd composite clocks, so
provides two helpers that can be reused later on.

Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21 15:00:52 -08:00
Chunyan Zhang cdb09f67a2 clk: sprd: add gate clock support
Some clocks on the Spreadtrum's SoCs are just simple gates. Add
support for those clocks.

Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21 15:00:51 -08:00
Chunyan Zhang d41f59fd92 clk: sprd: Add common infrastructure
Added Spreadtrum's clock driver framework together with common
structures and interface functions.

Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21 15:00:51 -08:00