Remove call to the old GPIO init function.
Fix old MPP control offset value.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Acked-by: Saeed Bishara <saeed.bishara@gmail.com>
Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
If a counter overflows during a perf stat profiling run it may overtake
the last known value of the counter:
0 prev new 0xffffffff
|----------|-------|----------------------|
In this case, the number of events that have occurred is
(0xffffffff - prev) + new. Unfortunately, the event update code will
not realise an overflow has occurred and will instead report the event
delta as (new - prev) which may be considerably smaller than the real
count.
This patch adds an extra argument to armpmu_event_update which indicates
whether or not an overflow has occurred. If an overflow has occurred
then we use the maximum period of the counter to calculate the elapsed
events.
Acked-by: Jamie Iles <jamie@jamieiles.com>
Reported-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARMv7 dictates that the interrupt-enable and count-enable registers for
each PMU counter are UNKNOWN following core reset.
This patch adds a new (optional) function pointer to struct arm_pmu for
resetting the PMU state during init. The reset function is called on
each CPU via an arch_initcall in the generic ARM perf_event code and
allows the PMU backend to write sane values to any UNKNOWN registers.
Acked-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The ARMv7 architecture does not guarantee that effects from co-processor
writes are immediately visible to following instructions.
This patch adds two isbs to the ARMv7 perf code:
(1) Immediately after selecting an event register, so that the PMU state
following this instruction is consistent with the new event.
(2) Immediately before writing to the PMCR, so that any previous writes
to the PMU have taken effect before (typically) enabling the
counters.
Acked-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Reviewed-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The second GIC, present when EB board is used with a MPCore tile,
was initialised starting with irq number 64, which made interrupts
64-95 in the primary GIC unusable.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* 'syscore' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/suspend-2.6:
Introduce ARCH_NO_SYSDEV_OPS config option (v2)
cpufreq: Use syscore_ops for boot CPU suspend/resume (v2)
KVM: Use syscore_ops instead of sysdev class and sysdev
PCI / Intel IOMMU: Use syscore_ops instead of sysdev class and sysdev
timekeeping: Use syscore_ops instead of sysdev class and sysdev
x86: Use syscore_ops instead of sysdev classes and sysdevs
* 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jwessel/linux-2.6-kgdb:
kdb: add usage string of 'per_cpu' command
kgdb,x86_64: fix compile warning found with sparse
kdb: code cleanup to use macro instead of value
kgdboc,kgdbts: strlen() doesn't count the terminator
* 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
perf, x86: Complain louder about BIOSen corrupting CPU/PMU state and continue
perf, x86: P4 PMU - Read proper MSR register to catch unflagged overflows
perf symbols: Look at .dynsym again if .symtab not found
perf build-id: Add quirk to deal with perf.data file format breakage
perf session: Pass evsel in event_ops->sample()
perf: Better fit max unprivileged mlock pages for tools needs
perf_events: Fix stale ->cgrp pointer in update_cgrp_time_from_cpuctx()
perf top: Fix uninitialized 'counter' variable
tracing: Fix set_ftrace_filter probe function display
perf, x86: Fix Intel fixed counters base initialization
* 'core-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
futex: Fix WARN_ON() test for UP
WARN_ON_SMP(): Allow use in if() statements on UP
x86, dumpstack: Use %pB format specifier for stack trace
vsprintf: Introduce %pB format specifier
lockdep: Remove unused 'factor' variable from lockdep_stats_show()
* 'for-linus' of git://git390.marist.edu/pub/scm/linux-2.6:
[S390] cmpxchg: implement cmpxchg64()
[S390] xchg/cmpxchg: move to own header file
[S390] ccwgroup_driver: remove duplicate members
[S390] ccw_bus_type: make it static
[S390] ccw_driver: remove duplicate members
[S390] qdio: prevent handling of buffers if count is zero
[S390] setup: register bss section as resource
[S390] setup: simplify setup_resources()
[S390] wire up sys_syncfs
[S390] wire up sys_clock_adjtime
[S390] wire up sys_open_by_handle_at
[S390] wire up sys_name_to_handle_at
[S390] oprofile: disable hw sampling for CONFIG_32BIT
[S390] early: limit savesys cmd string handling
[S390] early: Fix possible overlapping data buffer
Fix sparse warning:
arch/x86/kernel/kgdb.c:123:9: warning: switch with no cases
Reported-by: Namhyung Kim <namhyung@gmail.com>
Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
These system calls we recently added.
32-bit ABIs need compat handling for sys_clock_adjtime().
o32 also needs compat handling for sys_open_by_handle_at();
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2165/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The conversion did not make use of the new chip flag which signals the
core code to mask the chip before calling the set_type callback. Sigh.
Use the new lockdep helper as well.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2183/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Currently there is one irq_chip per gpio_chip with the only difference
being the name. Since the information whether the irq belong to GPIO
bank A, B, C or D is not that important rewrite the code to simply use
a single irq_chip for all gpio_chips.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2182/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Convert the JZ4740 intc and gpio irq chips to use newstyle irq functions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2181/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Russell King