The node name preferred by mmc-controller.yaml binding spec is "mmc":
berlin2-sony-nsz-gs7.dt.yaml: sdhci@ab0000: $nodename:0:
'sdhci@ab0000' does not match '^mmc(@.*)?$'
berlin2-sony-nsz-gs7.dt.yaml: sdhci@ab0800: $nodename:0:
'sdhci@ab0800' does not match '^mmc(@.*)?$'
berlin2-sony-nsz-gs7.dt.yaml: sdhci@ab1000: $nodename:0:
'sdhci@ab1000' does not match '^mmc(@.*)?$'
berlin2cd-google-chromecast.dt.yaml: sdhci@ab0000: $nodename:0:
'sdhci@ab0000' does not match '^mmc(@.*)?$'
berlin2cd-valve-steamlink.dt.yaml: sdhci@ab0000: $nodename:0:
'sdhci@ab0000' does not match '^mmc(@.*)?$'
berlin2q-marvell-dmp.dt.yaml: sdhci@ab0000: $nodename:0:
'sdhci@ab0000' does not match '^mmc(@.*)?$'
berlin2q-marvell-dmp.dt.yaml: sdhci@ab0800: $nodename:0:
'sdhci@ab0800' does not match '^mmc(@.*)?$'
berlin2q-marvell-dmp.dt.yaml: sdhci@ab1000: $nodename:0:
'sdhci@ab1000' does not match '^mmc(@.*)?$'
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
There are better generic ones and the validation is going to complain:
mmp3-dell-ariel.dt.yaml: hsic@f0001000: $nodename:0: 'hsic@f0001000'
does not match '^usb(@.*)?'
mmp3-dell-ariel.dt.yaml: hsic@f0002000: $nodename:0: 'hsic@f0002000'
does not match '^usb(@.*)?'
...
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The current one makes validation unhappy:
mmp3-dell-ariel.dt.yaml: l2-cache-controller@d0020000: $nodename:0:
'l2-cache-controller@d0020000' does not match
'^(cache-controller|cpu)(@[0-9a-f,]+)*$'
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This way the device tree validator learns that each cell of the property
constitutes a separate item. Otherwise it gets unnecessairly upset:
mmp3-dell-ariel.dt.yaml: rtc@d4010000: interrupts: [[1, 0]] is too short
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This way the device tree validator learns that each cell of the property
constitutes a separate item. Otherwise it gets unnecessairly upset:
pxa168-aspenite.dt.yaml: rtc@d4010000: interrupts: [[5, 6]] is too short
pxa910-dkb.dt.yaml: rtc@d4010000: interrupts: [[5, 6]] is too short
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
gpio-pxa uses two cell to encode the interrupt source: the pin number
and the trigger type. Adjust the device node accordingly.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This way the device tree validator learns that each cell of the property
constitutes a separate item. Otherwise it gets unnecessairly upset:
pxa300-raumfeld-speaker-s.dt.yaml: gpio@40e00000: interrupts:
[[8, 9, 10]] is too short
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Robert Jarzmik <robert.jarzmik@free.fr.>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
gpio-pxa uses two cell to encode the interrupt source: the pin number
and the trigger type. Adjust the device node accordingly.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This makes the nodes compatible with the generic i2c binding without the
board DTS files having to supply the necessary properties themselves.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The current ones makes validation unhappy:
dove-d3plug.dt.yaml: main-interrupt-ctrl@20200: $nodename:0:
'main-interrupt-ctrl@20200' does not match
'^interrupt-controller(@[0-9a-f,]+)*$'
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The current ones makes validation unhappy:
kirkwood-lsxhl.dt.yaml: main-interrupt-ctrl@20200: $nodename:0:
'main-interrupt-ctrl@20200' does not match
'^interrupt-controller(@[0-9a-f,]+)*$'
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Various miscellaneous device tree source fixes to make them fully
binding compliant. It includes fixing various device node names,
order of interrupt properties, compatible names, address and size
cell fields and their aligment with children nodes as well as
moving some fixed devices out of bus node.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAl7DqaoACgkQAEG6vDF+
4phj+xAAw0pYfFBqH89qx7dl+BgKl4SMpue0WlhUgiZhbBS2RgrlGTW5TfBb6IVa
boU30Vw4rOdPozy7xizC0JnHsoD8PTxWKbA2t6s3VtTra3iGU0gT7wua/rzQ9pC2
yrk7mTMpa6j5FUdTNSkQwr3x5g95K5haTZV2kRZFBNHzgjZmh02BhGmfQ1TX+sbw
4vEde0xi1dOi9/A78gIWSUbvpdniFrYBkOAbMN8bo37KoCvnuvm2OU6t0UF6nj3h
51eKZjWbxxxh5Jj2DyFZzOaEW9T2vIeW6aqoNEinvz9blSUBmX8Dx8n2YZbUVr/O
ZsnfMXwU3SeRlIt4avNguGk0+xQuHAzy+Jls+A/ypTUL1vX8kTwO7Gs6gOZHsQ9n
DwFhoWesk86EQyzBy3t1mmvWU7Ic2YMjfW6WjmWxgccuTfTEbSZ6VAA/TQWQtvop
6xUtUbLJr1yuBshVsoJyO/yR1MoAnVKsOjB+AbiTW+nqs4oAoQ4q6TLti/z20G/k
l3cTdKVC97cqhXa9hEuIP5wTTBJ7uQJ0boR7fvdrfk0doRvEAI5Xh/OyCWKi2SUH
6nqUEtDoXFfUBfqLEj/uETQzHCo2CQPIyubJB0XhWkT+52/0Gi6KHzq6GvNrb7gt
tx27VizSRz1f1nbZ6jYi0MMnyGBjnRw+HIDBuiUU7kgFIGkJheI=
=Z5QL
-----END PGP SIGNATURE-----
Merge tag 'juno-updates-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt
ARMv8 Juno/Vexpress/Fast Models updates for v5.8
Various miscellaneous device tree source fixes to make them fully
binding compliant. It includes fixing various device node names,
order of interrupt properties, compatible names, address and size
cell fields and their aligment with children nodes as well as
moving some fixed devices out of bus node.
* tag 'juno-updates-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: Fix SCPI shared mem node name
arm64: dts: vexpress: Fix VExpress LED names
arm64: dts: juno: Fix GPU interrupt order
arm64: dts: fvp/juno: Fix bus node names
arm64: dts: fvp: Fix SMMU DT node
arm64: dts: fvp/juno: Fix serial node names
arm64: dts: juno: Use proper DT node name for USB
arm64: dts: fvp: Fix ITS node names and #msi-cells
arm64: dts: fvp: Fix GIC child nodes
arm64: dts: juno: Fix GIC child nodes
arm64: dts: fvp: Fix GIC compatible names
arm64: dts: juno: Fix mem-timer
arm64: dts: juno: Move fixed devices out of bus node
arm64: dts: fvp: Move fixed clocks out of bus node
arm64: dts: vexpress: Move fixed devices out of bus node
arm64: dts: fvp: Move fixed devices out of bus node
arm64: dts: fvp/juno: Fix node address fields
Link: https://lore.kernel.org/r/20200519094702.GA32975@bogus
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- New board: Microchip SAMA5D2 Industrial Connectivity Platform
- All SoCs are now converted to the new PMC device tree binding
- sama5d2 flexcom nodes are now fully described in sama5d2.dtsi
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEycoQi/giopmpPgB12wIijOdRNOUFAl7CpJMACgkQ2wIijOdR
NOWrAg//cH5TaJ+B/m4oHxfHgLg9qXXdKkLcCYB17YZLMKGbioaye1zBYWyCDJzb
Wz0AS5XNw9xgxA8U/p/okUV/t+TTWkL1/r98MqlBc7aPxk3UIiGVVlKD0rKLu0mW
/OsQwdeR/OyuBfLsspzoqHfhN3N/RZk1nlN2NbykTkHnKuY4CWpsewnJstpA7vl6
TTQgbbbs2VD5H3Fxo2tbSl03Iqbk3rPSzdtsSae4B7Ta4hO0r1xY04C3qe/bboh9
jautvydBnbSrqzbdcyHPh8XzF+TEyrPZzMuz9AD9sY6Zeqap69Aha6OYRe9cspNQ
05rMhvQaWhlvsmR5jAV0lHjnz+nA3sJ81QmBbaH9YOMgr0GhM940pNtjND7yOm1Q
jO20/NWJs8/POv1vIxAE8bKmAnk1ukV8HwcIn5gDaMVJWRuoqYqkCaZ0WfItcx7q
gdkC+k9pUWWscYQy8aZMhN7aqpC+wdLSlrdQ519R1HcpZMJ1K8oIz9h8/Fotgytx
b+KmgEFze6hQ9leZ2GJffDPZbknMsdcHdePk9j1dRyN6f0m33WVvNV4a5HVEmN0A
7ceVzT/5Mvp+pK4aAGPtxtNfKSLSFxyMgteGP+PjMRvnQmFwdQkuLRNb3qBR5XAI
sO+FoBRkgTBe4s+ztmioHBQERmynrbvX/p//FBho9+7y0m9Tt2o=
=EQfX
-----END PGP SIGNATURE-----
Merge tag 'at91-5.8-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt
AT91 DT for 5.8
- New board: Microchip SAMA5D2 Industrial Connectivity Platform
- All SoCs are now converted to the new PMC device tree binding
- sama5d2 flexcom nodes are now fully described in sama5d2.dtsi
* tag 'at91-5.8-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: (35 commits)
ARM: dts: at91: sama5d2_xplained: Add aliases for the dedicated I2C IPs
ARM: dts: at91: Configure I2C SCL gpio as open drain
ARM: dts: at91: sama5d2_xplained: Describe the flx0 I2C function
ARM: dts: at91: sama5d2_ptc_ek: Add comments to describe the aliases
ARM: dts: at91: sama5d2_xplained: Add alias for DBGU
ARM: dts: at91: sama5d2: Add missing flexcom definitions
ARM: dts: at91: sama5d2: Remove i2s and tcb aliases from SoC dtsi
ARM: dts: at91: sama5d2: Add DMA bindings for the SPI and I2C flx0 functions
ARM: dts: at91: sama5d2: Add DMA bindings for the flx1 I2C function
ARM: dts: at91: sama5d2: Add DMA bindings for the flx3 SPI function
ARM: dts: at91: sama5d2: Add DMA bindings for the SPI and UART flx4 functions
ARM: dts: at91: sama5d2: Specify the FIFO size for the Flexcom UART
ARM: dts: at91: sama5d2: Move flx0 definitions in the SoC dtsi
ARM: dts: at91: sama5d2: Move flx1 definitions in the SoC dtsi
ARM: dts: at91: sama5d2: Move flx2 definitions in the SoC dtsi
ARM: dts: at91: sama5d2: Move flx3 definitions in the SoC dtsi
ARM: dts: at91: sama5d2: Move flx4 definitions in the SoC dtsi
ARM: dts: at91: sama5d2: Fix the label numbering for flexcom functions
ARM: dts: at91: sama5d27_wlsom1: Add alias for i2c0
ARM: dts: at91: sama5d2-icp: add SAMA5D2-ICP
...
Link: https://lore.kernel.org/r/20200518212844.GA26356@piout.net
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add proximity sensor and magnetometer to the Samsung Golden
devicetree.
- Add magnetometer and touchscreen to the Samsung Skomer
devicetree.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAl7BoYoACgkQQRCzN7AZ
XXM2gA/+N9ni+nocsba5LkXSukYyZnww6ymCjjmlmrhfDkvmKFv1XOqar6zy/oBP
kAvJMvGrHH/17i/3S5CPEDugahKHkc1wD0AvidpTPfF6nomW1JkXZKloK2Cu4DU0
pmAzvpuozIjDzoO+BZKvu33qS5DlT3fjrAQLRmlRjfcf90EkdwTSFy4yQw9WJUwe
C/0w0b3anaGlA9iHuaE8PRzoU7mCPkTe2EJZcCrxyJHGR9shXv2VF9dpDRaE5GUl
LxlpBUuh4sXdivRzs2IAsQ4WNYudXN4o2JpcKTRAGLnygAA6C7vqke4V/QADzjEi
uPU4PPW2mCR8ntKMWTfOq6/pV0Il+Mkqinljbf3ae2NHJtmfrO+HhNk8NLU89gHz
ir2oc5lbLfIYlddeL3OSt1iuBrvTi0+aI0EwPadQlOpomZ7glIOwqPsszwUrsv3q
M12DAJCpyW5DxzXsdTDTvGlA9ph+/gkLiAv7inL5PCQUuOacyfVDADk6juRgCbNB
BnFfl6HxEyiDBFQ2lSiVUq4pq2E65waoBSwdZ3b8ttFmmcuk0INCM9ts3xOANJzQ
Su4+XKZrxRA8VbC1RMm1Hbz8W8AujNZhn32U5jN1CcpXQq5gwtdswANj9gXJu53o
SY2xDrDVSP/O+SlhCCZOEAiVNP5jDCsb/p/SEfhfzU+jBXU7k1k=
=UOo9
-----END PGP SIGNATURE-----
Merge tag 'ux500-dts-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into arm/dt
Ux500 DTS updates for the v5.8 kernel series:
- Add proximity sensor and magnetometer to the Samsung Golden
devicetree.
- Add magnetometer and touchscreen to the Samsung Skomer
devicetree.
* tag 'ux500-dts-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: dts: ux500: Add touchscreen to the Skomer
ARM: dts: ux500: samsung-skomer: Add magnetometer
ARM: dts: ux500: samsung-golden: Add magnetometer
ARM: dts: ux500: samsung-golden: Add proximity sensor
Link: https://lore.kernel.org/r/CACRpkdbukO33SxAZ_yn-1N8=hq3hF5OBOtP_V0fbjRT-fAa87A@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Leave the FPGA bridges disabled in base dtsi
- Add fpga2hps and fpga2sdram bridges on base Cyclone5/Arria5 dtsi
-----BEGIN PGP SIGNATURE-----
iQJIBAABCgAyFiEEoHhMeiyk5VmwVMwNGZQEC4GjKPQFAl6+6cMUHGRpbmd1eWVu
QGtlcm5lbC5vcmcACgkQGZQEC4GjKPQy2w/+KAzDC9PsZ+cx8qcb0t8BmB3N424G
tIIHXD+dITnJomeu+W9Z/BHBTwHTfEnH2jaVjCpIb7bQtm8u2abf/cNz7PLdza5+
6CX+uRWlerq42vWZuJAlT0PmTe1bi03+if7YRW09AlmR8z0LZ5kkyaJWhauPVC/V
8eIvGEoOc75d9r8f+M2w+Q+mq3skIVFJuQyY5pFQCzS2QAgKO6K6gYzj5vTTnDrH
9hZ13tPWTg7GioqoeApfzd2tOTdjADTS33C24/gwroWJuN9VxJnArTwhyfU5mWbQ
SRQKNcPHxJIcITV9vvCY+B6dUG6PqAJzxH3lh2aA3ktpkPMqjLxg1tssrJFUgTK8
NrrmNQ4cw75v0Y9Q0KSsNxiToTABnROTEpPkuNARq3uk3kEjyzxX/9Jp7e/eW/7k
VnOU5x7OgyI8L6AoEmRlnkF4EBmsLrCMlwPBLcoLLNJz+VZ4qiNpShEzlfesqW6Q
1/1FL9xBMH86djma0WT54fZnCWSiIDjORKQ3zbIrNJqkA9CK2Do0X7KCzhsbPHKn
3J9cPxrGBJ+4cprQZj1Uc1rce33JaYQytryNXbfAQat37Sp50sEe1YrtmiMmY/ab
TnzaIGqludJBZr+czrCPq35kjf8WoUfVGuyTT8/zKUsKxl2HYIAEvEs4ebCnLZ+X
a8UTu+xKVlHk/tw=
=UMA8
-----END PGP SIGNATURE-----
Merge tag 'socfpga_dts_update_for_v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt
SoCFPGA DTS updates for v5.8
- Leave the FPGA bridges disabled in base dtsi
- Add fpga2hps and fpga2sdram bridges on base Cyclone5/Arria5 dtsi
* tag 'socfpga_dts_update_for_v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: dts: socfpga: Add fpga2hps and fpga2sdram bridges
ARM: dts: socfgpa: set bridges status to disabled
Link: https://lore.kernel.org/r/20200515193029.11318-2-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
support, including:
- Support for the IOMMU on the H6
- Support for cpufreq / thermal throttling on the H6
- Support for the mailbox on the A64, A83t, H3, H5 and H6
- New boards: A20-OLinuXino-LIME-eMMC
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXr7NHgAKCRDj7w1vZxhR
xbhGAQCDavHkpjvq4Hwk/znoS0Y6NvW1JQUyKUWH8K6ah1ZkFwEA5gC0Ac9cbDAk
Q5fZeYl7mPbEL9DI0RphVqHmY2ezXw0=
=WR5/
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt-for-5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Our usual number of patches to improve the Allwinner Device Tree
support, including:
- Support for the IOMMU on the H6
- Support for cpufreq / thermal throttling on the H6
- Support for the mailbox on the A64, A83t, H3, H5 and H6
- New boards: A20-OLinuXino-LIME-eMMC
* tag 'sunxi-dt-for-5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (23 commits)
arm64: dts: allwinner: h6: Add IOMMU
arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6
arm64: dts: allwinner: h6: add voltage range to OPP table
arm64: dts: allwinner: sun50i-a64: Add missing address/size-cells
arm64: dts: allwinner: h6: Enable CPU opp tables for Pine H64
arm64: dts: allwinner: Sort Pine H64 device-tree nodes
arm64: dts: allwinner: h6: Enable CPU opp tables for Orange Pi 3
arm64: dts: allwinner: h6: Enable CPU opp tables for Beelink GS1
arm64: dts: allwinner: h6: Add CPU Operating Performance Points table
arm64: dts: allwinner: h6: Add thermal trip points/cooling map
arm64: dts: allwinner: h6: Add clock to CPU cores
arm64: allwinner: h6: orangepi-lite2: Support BT+WIFI combo module
arm64: dts: allwinner: h6: orangepi: Disable OTG mode
arm64: dts: allwinner: h6: orangepi: Add gpio power supply
ARM: dts: sun8i-h2-plus-bananapi-m2-zero: Fix led polarity
arm64: dts: allwinner: h6: Add msgbox node
arm64: dts: allwinner: a64: Add msgbox node
ARM: dts: sunxi: h3/h5: Add msgbox node
ARM: dts: sunxi: a83t: Add msgbox node
ARM: dts: sun8i-h3: add opp table for mali gpu
...
Link: https://lore.kernel.org/r/cfa66bd9-f74c-4614-9ea5-9ef8546cc571.lettre@localhost
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This contains a bit of cleanup and CPU frequency scaling support for the
Tegra30 Beaver board.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl6+pQYTHHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zoR+VD/9wS9fQMI3b56vWJa8EKMiIV6XlvDJ/
HGR0ZOcCH25pHcgMrvg/pAa3TISA2dCGnGxd3Ax+5bU9JvVfC7GujiYwa/IaUkZI
7alUKUe4sTG498hfix2XNDcYcnHm4UnPen2/3ehugRe8BW9v1fnQHwrz5NM/RbzX
+EsFA142e74NJ4BcCDsgUHOIU4yWlOVZZi1zP/NbwpNJO4eGV9cXGXVlQfhmtPqZ
Gz+fe4kUPgUDdTijng8eRpoJXytmki/C6grL0bITtkQ0G4AZIWd9pBts3KO4m+bf
tGuOMWfXBQm0HuiNB+5dMj4Twmj4h+U94SUVDw9hBhnYb0cYGhEdFhwfzCxqr+iC
XqY8NsXiKFWnsZUBWDGL5LOIV7qdQnBChizACLLf2qZ5adlRRanPdQRxkFko12pK
EG27dhN5YtRR1eRtNMmeEQIWZBVj6V1Vg2Mm5EReHO8r/GJ06Ic3lh4MMnk/LCL5
lYWbrlOTUrJl2LHMDM0N1fAJg97BLr9ni0VX1+E8bb3bQXyiDbzhEV2rLt4adEDF
0NEY12+/g0XKfxZ0QeC0DjyafHk7WmbO5pHr0FsB5ngc9RB8bfR+8yPvR2E0aiRW
DuKz6Bp4zXgMLQ7Rk72jU5HVNN7DRGPQ4wN3D9XK9wA1RnFVcspPlWTRMEkdzvrW
b+rrQnhnUQ22eg==
=55XZ
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-5.8-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
ARM: tegra: Device tree changes for v5.8-rc1
This contains a bit of cleanup and CPU frequency scaling support for the
Tegra30 Beaver board.
* tag 'tegra-for-5.8-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: dts: tegra30: beaver: Add CPU Operating Performance Points
ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS
ARM: tegra: Kill off "simple-panel" compatibles
Link: https://lore.kernel.org/r/20200515145311.1580134-11-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Initial support for the Renesas RZ/G1H SoC on the iWave RainboW
Qseven SOM (G21M) and board (G21D),
- Support for the AISTARVISION MIPI Adapter V2.1 camera board on the
Silicon Linux EK874 RZ/G2E evaluation kit.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCXr5g8QAKCRCKwlD9ZEnx
cDusAQD4SCmyY0MZZNWQhkhu2ics2wYpKItw4Y7E4fl9XUlXkQEAyyN11vVNoteX
7KvNX7/9eXpberlcx4H6szPQsOzWzwM=
=2KDk
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-dt-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.8 (take two)
- Initial support for the Renesas RZ/G1H SoC on the iWave RainboW
Qseven SOM (G21M) and board (G21D),
- Support for the AISTARVISION MIPI Adapter V2.1 camera board on the
Silicon Linux EK874 RZ/G2E evaluation kit.
* tag 'renesas-arm-dt-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: r8a774c0-cat874: Add support for AISTARVISION MIPI Adapter V2.1
ARM: dts: r8a7742: Add GPIO nodes
ARM: dts: r8a7742: Add [H]SCIF{A|B} support
ARM: dts: r8a7742: Add IRQC support
ARM: dts: r8a7742-iwg21d-q7: Add iWave G21D-Q7 board based on RZ/G1H
ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM
ARM: dts: r8a7742: Initial SoC device tree
clk: renesas: Add r8a7742 CPG Core Clock Definitions
dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros
Link: https://lore.kernel.org/r/20200515100547.14671-3-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Highlights:
----------
MCU part:
-fix a typo for DAC io-channel-cells on f429 and h743
MPU part:
-Generic:
-Bump tp PSCI 1.0
-Fix a typo for DAC io-channel-cells
-Add M4 pdds for deep sleep mode
-Add I2C fatmode plus support
-Add new Octavio lxa-mc1 board based on OSDMP15x SiP
-Add new Stinger96 board support. It is a 96Boards IoT Extended board
based on stm32mp157a SoC. Some figures: 256MB DDR, 125MB and flash,
Onboard BG96 modem...
-Add IoT Box board support based on stinger96 board + Wifi/BT, CCS811
VOC sensor, 2 digitals microphones ...
-DH:
-Adapt dhcom-som and dhcom-pdk2 dts(i) files to STM32MP15 SoC diversity
-Add GPIO led and GPIO keys support on PDK2 board
-AV96:
-Major rework to support official avenger96 board based on DHCOR SOM.
-Prototype board is no more supported
-----BEGIN PGP SIGNATURE-----
iQJMBAABCgA2FiEEctl9+nxzUSUqdELdf5rJavIecIUFAl69aa4YHGFsZXhhbmRy
ZS50b3JndWVAc3QuY29tAAoJEH+ayWryHnCFhH0QAK+7gK6fKXJU+meHe7kSuzm1
IvMYGA126KXubzNCSq2dxkHhGf+hlHE9jaQd27N9sTWY5Zi/B/xMDC+XotZhNEuL
+vLwPl5tfENOK/MC+eu5HFdx8D/1dMZ1eh0PyudjifxB1yiTqHpoce6hwJ+gHedT
GwvAz8udReP5jQTHK6Z66z56A81qMxLCKiAL4M2ExqzYECX/nl7bkqtpzG8OG56l
wsfjOowpw0g6KLMjnL+0l97/xhXUdEeIQ7IvrvNhC4zgNytZREk8wymh0odPHLZP
PmZ0f0cjgtP3HAt26GuyG2IZI2byoat3KWAqOxmXeqNR7EWPjkwAtU4kYprk1reu
rZ70SqCvk6ABH3E8s5v4Noa+ni7Et4NB/BqUwulfBXTgl3D9dzloKNc+rSi/BFXd
E1aaEL4qXu89b3GOsC1tq2SLbsr28GkNg54+Tb1SBpTJV8wTgScKTuopExQoBVPU
iMRDPJ8jv6fRD99g/ZOa+8u13cYh1u8pSOSS4jpgyHeEagebnxnkLv71uETp2Nva
WgLXEYuDgfwEJ6C4lyLbX1g5ak1LLix5gDMFTdSPiW0SCIs5NEk112ItQMWg8b3r
P3pThyzwpUOUyi742OCo02r5d+LrBbcBNktGYMcv/l/lc9u/ObDwmoaBjclTHVwq
yQuJS+y6TAoLORRr4rOg
=JFtr
-----END PGP SIGNATURE-----
Merge tag 'stm32-dt-for-v5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt
STM32 DT updates for v5.8, round 1
Highlights:
----------
MCU part:
-fix a typo for DAC io-channel-cells on f429 and h743
MPU part:
-Generic:
-Bump tp PSCI 1.0
-Fix a typo for DAC io-channel-cells
-Add M4 pdds for deep sleep mode
-Add I2C fatmode plus support
-Add new Octavio lxa-mc1 board based on OSDMP15x SiP
-Add new Stinger96 board support. It is a 96Boards IoT Extended board
based on stm32mp157a SoC. Some figures: 256MB DDR, 125MB and flash,
Onboard BG96 modem...
-Add IoT Box board support based on stinger96 board + Wifi/BT, CCS811
VOC sensor, 2 digitals microphones ...
-DH:
-Adapt dhcom-som and dhcom-pdk2 dts(i) files to STM32MP15 SoC diversity
-Add GPIO led and GPIO keys support on PDK2 board
-AV96:
-Major rework to support official avenger96 board based on DHCOR SOM.
-Prototype board is no more supported
* tag 'stm32-dt-for-v5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (58 commits)
ARM: dts: stm32: Split Avenger96 into DHCOR SoM and Avenger96 board
ARM: dts: stm32: Split SoC-independent parts of DHCOM SOM and PDK2
ARM: dts: stm32: Add GPIO LEDs for STM32MP1 DHCOM PDK2
ARM: dts: stm32: Add GPIO keys for STM32MP1 DHCOM PDK2
ARM: dts: stm32: Add IoT Box board support
dt-bindings: arm: stm32: Document IoT Box compatible
ARM: dts: stm32: Add Stinger96 board support
dt-bindings: arm: stm32: Document Stinger96 compatible
ARM: dts: stm32: Add missing pinctrl entries for STM32MP15
dt-bindings: Add vendor prefix for Shiratech Solutions
ARM: dts: stm32: Add bindings for SPI2 on AV96
ARM: dts: stm32: Add alternate pinmux for SPI2 pins
ARM: dts: stm32: Add bindings for ADC on AV96
ARM: dts: stm32: Add alternate pinmux for ADC pins
ARM: dts: stm32: Add bindings for FDCAN2 on AV96
ARM: dts: stm32: Add alternate pinmux for FDCAN2 pins
ARM: dts: stm32: Add bindings for FDCAN1 on AV96
ARM: dts: stm32: Add alternate pinmux for FDCAN1 pins
ARM: dts: stm32: Repair I2C2 operation on AV96
ARM: dts: stm32: Add alternate pinmux for I2C2 pins
...
Link: https://lore.kernel.org/r/19160355-364d-170c-7ae2-5ba7f714103f@st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
1. Add DTS for Exynos4210-based Samsung Galaxy S2 (GT-I9100)
mobile phone,
2. Enable WiFi and Bluetooth in multiple boards,
3. Add new features to S5Pv210-based Aries family of mobile phones
(e.g. Samsung Galaxy S): necessary configuration for suspend, audio
support, USB mux, touch keys, panel, i2c-gpio adapters, FM radio, ADC,
4. Many minor fixes (e.g. GPIO polarity, interrupts).
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAl66lFUQHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD1yYGEACBvawfckK8OOJig55ndsENHN+/qvhy2+e8
GK/vt5Rg0Hx296s+laDhvz7kH4djSca1hAvM6rceA0ov2EqxuncQwAN1elH96HLf
PHcfWX2+lREz5F5t4vb+/+5YCn0xIH0VQIwPQJUkTCDspo9XU7KrKUo2/h7qycCT
Pk+TmLJqO/8JKmYTDenm5yALHzdPJgvy/Q+dEU+cXSG//my9azI8vb7AUUgXJTWb
PYZX8LhyPAK8sOXkVVmfuvz/L+kVGNPP5UNurqUOM+i63OSLyHd1w+6U38OXUGsq
rJaFsQI7eZNCLH37MHEg0D8vlBG7VaB1jVHRMyQKemu9dojkbv65ISvO8N4gqP3F
pEgjwDYSddXjrGepHOUHxO+5PVBweDqrPHwk2G46+YdiudcaVflUkQ8XUKqABzPx
X31LLM7B0ITh3VUZtr1pwluThdlMKClchDzlYMntztSraMtuXxzMXE/MOSrUxmbL
wYXA2vLn361muuW1YV2kP/1k03vbdyunRybtlcCq4p9oBFC/5LZLVT6ZxIOUXZDm
620p67/a0o3vaw8xfwvheRv0q2BkbjmHIIedky2VMy5EH6a0czRm37Xxb3pRupxd
uvuIAHLp2Vu9N+CbKivDeUA37WZZhDi3xz/6jJpTiz9r4ktS5oYEQoyxhNKShOfp
rOdjhoP6Rg==
=kTHc
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Samsung DTS ARM changes for v5.8
1. Add DTS for Exynos4210-based Samsung Galaxy S2 (GT-I9100)
mobile phone,
2. Enable WiFi and Bluetooth in multiple boards,
3. Add new features to S5Pv210-based Aries family of mobile phones
(e.g. Samsung Galaxy S): necessary configuration for suspend, audio
support, USB mux, touch keys, panel, i2c-gpio adapters, FM radio, ADC,
4. Many minor fixes (e.g. GPIO polarity, interrupts).
* tag 'samsung-dt-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (29 commits)
ARM: dts: s5pv210: Set MAX8998 GPIO pulls on Aries boards
ARM: dts: s5pv210: Correct FIMC definitions
ARM: dts: s5pv210: Assign clocks to MMC devices on Aries boards
ARM: dts: s5pv210: Enable ADC on Aries boards
ARM: dts: s5pv210: Add an ADC node
ARM: dts: s5pv210: Disable pull for vibrator enable GPIO on Aries boards
ARM: dts: s5pv210: Add si470x FM radio to Galaxy S
ARM: dts: s5pv210: Add remaining i2c-gpio adapters to Aries boards
ARM: dts: s5pv210: Add panel support to Aries boards
ARM: dts: s5pv210: Add touchkey support to Aries boards
ARM: dts: s5pv210: Add FSA9480 support to Aries boards
ARM: dts: s5pv210: Add WM8994 support to Aries boards
ARM: dts: s5pv210: Disable pulls on GPIO I2C adapters for Aries
ARM: dts: s5pv210: Set keep-power-in-suspend for SDHCI1 on Aries
ARM: dts: s5pv210: Correct gpi pinctrl node name
ARM: dts: s5pv210: Add sleep GPIO configuration for Galaxy S
ARM: dts: s5pv210: Add sleep GPIO configuration for Fascinate4G
ARM: dts: s5pv210: Add helper define for sleep gpio config
ARM: dts: exynos: Enable WLAN support for the UniversalC210 board
ARM: dts: exynos: Enable WLAN support for the Rinato board
...
Link: https://lore.kernel.org/r/20200512122922.5700-2-krzk@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
for v5.8, please pull the following:
- Nicolas updates the Raspberry Pi 4 board DTS to include the GPIO
controlling power to the SD card, adds support for the vmmc regulator
for the emmc2 controller and finally updates the power management
provider for V3D to use the firmware to solve instabilities.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAl64WbsACgkQh9CWnEQH
BwSDyw//TdqnPMJO/U5RbH+prt4N4/FcymESDtZ4op4y2UyI6Cr5g+5IJyEGjaQ1
YSmdHcTcThYH0nneUIWiATNv7RtyTlg36HiWogxFpTEvvI77ttwiRcSphmxWnJMz
XLfwzr9b4p+y7IdanwGZ5YLnHfXNX/uZwxfkweRhvNlS9jLvGha1lchV/JS6MKGE
Nw+d9SN6TyoMxIKL6CJq6TuXDsSsIS94zYZybIN8yFWxbKkK4GXVvMp+s+Ix4dyc
9TVvT+YtJkKDElcPz0lulLI5P2a9Rdm4jNxTXUKzcfavSPFCq9nkDmxJIhRomAGr
OGJtIg8gjz44wiFN9WT6BQy1lHqfy44OhRLwZmX8krD6HxEjln8AB5H+8v/AZ5P3
02lLcfUPYb4y3Fog073zDLa9EZy4fJKxYNnRBVcPwpPkT8mNapC3OKdkC0l5V4s5
RwCRvvWVQCUDMYxkT1sXlQCFTbTL/VKoa+xS6fsP0TOY8OVCKhxm3M3D5PMDoYic
r0J/xNngzS8xvm9LwiEvA0tAKfPUTatlFfiFLuJhddUvMFHEsFTmYW+houO54e6N
jrAxcwMvJlHr/jkaRlpZYf+C18+Z841RDMTmAMpZ1/ad6CgJkyjuf9SLce4hbsp5
8Cvr6khD+843eWjZYoF5+ePa8UEnCzfpoVf2z4ivXuAf6X3ucLM=
=cX7l
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-5.8/devicetree' of https://github.com/Broadcom/stblinux into arm/dt
This pull request contains Broadcom ARM-based SoCs Device Tree changes
for v5.8, please pull the following:
- Nicolas updates the Raspberry Pi 4 board DTS to include the GPIO
controlling power to the SD card, adds support for the vmmc regulator
for the emmc2 controller and finally updates the power management
provider for V3D to use the firmware to solve instabilities.
* tag 'arm-soc/for-5.8/devicetree' of https://github.com/Broadcom/stblinux:
ARM: dts: bcm283x: Use firmware PM driver for V3D
ARM: dts: bcm2711: Add vmmc regulator in emmc2
ARM: dts: bcm2711: Update expgpio's GPIO labels
Link: https://lore.kernel.org/r/20200511210522.28243-2-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
We add support for beaglebone-ai board that's am5729 based devices.
Then we have a series changes to configure more hardware acceletators found
on omap variants. With the recent ti-sysc related changes, we can now better
configure the accelerators with help of the clock framework and reset driver.
So with a series of changes from Suman Anna and Tero Kristo, let's configure
IPUs and DSPs for dra7 devices like beagle-x15. And let's also configure the
missing crypto accelerators for omap5 as those have been missing.
Note that there are still some pending driver related patches to use IPU and
DSP related features with mainline kernel, but those are independent of the
devicetree changes.
Then there is a display related change for am57xx-idk for tc358778 bridge,
and a change to configure the missing clock source for some PWM timers.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAl60ST4RHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXPLbQ/9HtaOPHBGSiySIjiKMipiT4h7Ebc8b6ng
71rRGFgjlyGSDolBlvEfzRfuMRqIQpCRETMylpn4rHkx/BsTROt90/LayyJiJJ62
buQtSsx2Ydcxw+QMl8gkBW/Y1toZ31ZQKedeNJDvlAzOt8kgQjiCoBo9VVhiZANX
xV0tlfUjgU0BH3P5UhyAXQkBHzauqd+c9z4YOuNL1BbEu6b75b5a7f2+DtV/NLmZ
EaEMtoA/L0k5Ir8GWSc6R48kmpaSs3go6r7v2hUV8rHkQOwUhm6MgdD2xrbXRbH3
4TVF5KLhV9bSyoIRZryYQWS/8Y5CSfDOHcMFqSHoasvMt81Vnz/bit3akghyQ/Ir
+3J8sLT6LGVotbDrN++yIfc9KZr7xQBZSbz2lHw/Fg10iD33TvvEASmANNF6FTLy
mjJpwjqDCMcQ40LLP1aC7SzuM3hf8cWDsagIY3Reo/pW7aF4FEnX14FdObwtmQIJ
RePY5JLQU1UPXstUwLwjFcmkBYgBGC2DVYPeGTUAU6RQtIX3b9ddpjZxFpMgbBAM
OgLwDGvdYClh+cwPw4Ax2LPmqs534v75vhYsQO0jjaXcDDhGLGUkfD2v3f1B9Gcl
Lj2yj6vIBjE3A+LRxJeFv2FWOzi1qsh2NrHILmIh+pNkuTyjcsc4x02+BfQvS4x3
afVrdB0kOsU=
=WgDN
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v5.8/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt
DTS changes for omaps for v5.8 merge window
We add support for beaglebone-ai board that's am5729 based devices.
Then we have a series changes to configure more hardware acceletators found
on omap variants. With the recent ti-sysc related changes, we can now better
configure the accelerators with help of the clock framework and reset driver.
So with a series of changes from Suman Anna and Tero Kristo, let's configure
IPUs and DSPs for dra7 devices like beagle-x15. And let's also configure the
missing crypto accelerators for omap5 as those have been missing.
Note that there are still some pending driver related patches to use IPU and
DSP related features with mainline kernel, but those are independent of the
devicetree changes.
Then there is a display related change for am57xx-idk for tc358778 bridge,
and a change to configure the missing clock source for some PWM timers.
* tag 'omap-for-v5.8/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (26 commits)
ARM: OMAP5: Make L4SEC clock domain SWSUP only
ARM: OMAP4: Make L4SEC clock domain SWSUP only
ARM: dts: omap5: add DES crypto accelerator node
ARM: dts: omap5: add SHA crypto accelerator node
ARM: dts: omap5: add aes2 entry
ARM: dts: omap5: add aes1 entry
ARM: dts: dra7-ipu-dsp-common: Add watchdog timers to IPU and DSP nodes
ARM: dts: am571x-idk: Add CMA pools and enable IPUs & DSP1 rprocs
ARM: dts: am572x-idk-common: Add CMA pools and enable IPU & DSP rprocs
ARM: dts: beagle-x15-common: Add CMA pools and enable IPU & DSP rprocs
ARM: dts: dra76-evm: Add CMA pools and enable IPU & DSP rprocs
ARM: dts: dra71-evm: Add CMA pools and enable IPUs & DSP1 rprocs
ARM: dts: dra72-evm-revc: Add CMA pools and enable IPUs & DSP1 rprocs
ARM: dts: dra72-evm: Add CMA pools and enable IPUs & DSP1 rprocs
ARM: dts: dra7-evm: Add CMA pools and enable IPU & DSP rprocs
ARM: dts: dra7-ipu-dsp-common: Add timers to IPU and DSP nodes
ARM: dts: dra7-ipu-dsp-common: Add mailboxes to IPU and DSP nodes
ARM: dts: dra7-ipu-dsp-common: Move mailboxes into common files
ARM: dts: DRA72x: Add aliases for rproc nodes
ARM: dts: DRA74x: Add aliases for rproc nodes
...
Link: https://lore.kernel.org/r/pull-1588873628-477615@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Create a new device tree for the Integrator/AP with the
IM-PD1 expansion module fitted in the first slot.
If we want to augment the slot where it is sitting, we can
alter the device tree or make the bootloader do so.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAl6oi4YACgkQQRCzN7AZ
XXOpVBAAxco/qwxQndEPMWDVCtqOdhXglUvq220V5PQ4DNvpm52QeG65rwwR2TK9
Nun/vW70JZnXysGS4ZAU9NKToenyIdacwfFCea1eDK7cWpbZzZGo3dkMsr90KBah
iGDx1ua/lAPxP+IhGlv8GBFQ4rMYzBewaAvk30pi3FtoV/gUjszqLUX1UI7TTaEA
LWlI4t9aFrRryTsffVzCMXKWUbovMfPtf7dvi+H+Paid8x5PVRwpo91eLknydwb6
BQAxFhaNy34U27DIsH4L2ulcy7xFBwlmOVHA8h9cTq5qFF/ASxAhAmdQvg+DzjqK
8YZkWAgOMfwuY+zDFHsvGMJXWZeNOfo76tV0QhiHPlC9JcvOxc95SH7SDwTVjQ/v
JyLfqMxz6VaL4tL5j2APHgjQzpNtOs6aPNiUkmxrz3iLGuzi51f+Ua/I5MbYd2ME
oyW21YIebHtiHhZ30NenS0hnD2prFzsdDZLgI04LKwCTW56xM2XS7diz1if+yxJ8
49LWboInAq8B4ipuRmzNrUoWZlcYZcdUh/7gi1xCwkdpg0rNj/3hKzeRf3W78yw2
Tve2E2TK+I+l4bJclCjdYzbkWUkheZWApx5nK+4kAAwS+rr1AM4oXZYtd7530LUK
YL9CavQeDL8SfW8zzCVooureO9MDdzYb5o+joKhaBejgvCGThOg=
=XZ07
-----END PGP SIGNATURE-----
Merge tag 'versatile-dts-v5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into arm/dt
Versatile DTS updates for the v5.8 kernel:
Create a new device tree for the Integrator/AP with the
IM-PD1 expansion module fitted in the first slot.
If we want to augment the slot where it is sitting, we can
alter the device tree or make the bootloader do so.
* tag 'versatile-dts-v5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: dts: Add devicetree for Integrator/AP with IM-PD1
Link: https://lore.kernel.org/r/CACRpkdZ-28o+pPdP7i_fc+7g4ndPWf+SWTsjnhFEegTggiXVSg@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
These error messages are output when booting on a BCM HR2 system:
GIC: PPI11 is secure or misconfigured
GIC: PPI13 is secure or misconfigured
Per ARM documentation these interrupts are triggered on a rising edge.
See ARM Cortex A-9 MPCore Technical Reference Manual, Revision r4p1,
Section 3.3.8 Interrupt Configuration Registers.
The same issue was resolved for NSP systems in commit 5f1aa51c7a
("ARM: dts: NSP: Fix PPI interrupt types").
Fixes: b9099ec754 ("ARM: dts: Add Broadcom Hurricane 2 DTS include file")
Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The status "ACT" led on the Raspberry Pi Zero W is on when GPIO 47 is low.
This has been verified on a board and somewhat confirmed by both the GPIO
name ("STATUS_LED_N") and the reduced schematics [1].
[1]: https://www.raspberrypi.org/documentation/hardware/raspberrypi/schematics/rpi_SCH_ZeroW_1p1_reduced.pdf
Fixes: 2c7c040c73 ("ARM: dts: bcm2835: Add Raspberry Pi Zero W")
Signed-off-by: Vincent Stehlé <vincent.stehle@laposte.net>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Move the soc device register code to drivers/soc/imx to align with
i.MX8.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The soc device register code will be moved to drivers/soc/imx/,
the code needs the cpu type definitions. So let's move the cpu
type definitions to a header.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This is preparation to move imx_soc_device_init to drivers/soc/imx/
There is no reason to must put dt devices under /sys/devices/soc0,
they could also be under /sys/devices/platform, so we could
pass NULL as parent when calling of_platform_default_populate.
Following soc-imx8.c soc-imx-scu.c using device_initcall, need
to change return type to int type for imx_soc_device_init.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Group the port definitions of the dvi-converter in a 'ports' node to
make it compliant with the ti,tfp410 binding.
Signed-off-by: Ricardo Cañuelo <ricardo.canuelo@collabora.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Node name should be generic, use "reset-controller" instead of "src" for
i.MX5 SoCs src nodes.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Interrupt is a required property according to SRC binding, add
it for SRC node.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Node name should be generic, use "reset-controller" instead of "src" for
i.MX6/i.MX7 SoCs src nodes.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the missing input mux for ENET2 mdio. Without this setting, it is not
possible to read the MDIO answers back from the PHY.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Avoid LDB and IPU DI clocks both using the same parent. LDB requires
pasthrough clock to avoid breaking timing while IPU DI does not.
Force IPU DI clocks to use IMX6QDL_CLK_PLL2_PFD0_352M as parent
and LDB to use IMX6QDL_CLK_PLL5_VIDEO_DIV.
This fixes an issue where attempting atomic modeset while using
HDMI and display port at the same time causes LDB clock programming
to destroy the programming of HDMI that was done during the same
modeset.
Cc: stable@vger.kernel.org
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
[Use IMX6QDL_CLK_PLL2_PFD0_352M instead of IMX6QDL_CLK_PLL2_PFD2_396M
originally chosen by Robert Beckett to avoid affecting eMMC clock
by DRM atomic updates]
Signed-off-by: Ian Ray <ian.ray@ge.com>
[Squash Robert's and Ian's commits for bisectability, update patch
description and add stable tag]
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Although ocotp clock is always ON for i.MX6SL, OCOTP can be
accessed directly, but since i.MX6SL nvmem interface is supported,
and fsl,tempmon-data is deprecated, use it instead of getting fuse
data by reading ocotp directly, this makes all i.MX6 SoCs aligned.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Although ocotp clock is always ON for i.MX6QDL, OCOTP can be
accessed directly, but since i.MX6QDL nvmem interface is supported,
and fsl,tempmon-data is deprecated, use it instead of getting fuse
data by reading ocotp directly, this makes all i.MX6 SoCs aligned.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Connect the wl_reg regulator to usdhc2 such that it can be enabled
and disabled as needed. There is no need for this to be always-on.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The Sterling-LWB has a BCM4330 which has a UART based bluetooth
HCI. Add support for binding to the bcm_hci driver to take care
of handling the shutdown gpio and loading firmware.
Because the shutdown gpio is more of an enable than a regulator
go ahead and replace the regulator with a shutdown-gpio.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add one node for the accel/gyro i2c device and another for the separate
magnetometer device in the lsm9ds1.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add one node for the accel/gyro i2c device and another for the separate
magnetometer device in the lsm9ds1.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Interrupt is a required property according to SRC binding, add
it for SRC node.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Interrupt is a required property according to SRC binding, add
it for SRC node.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Fix sparse warning:
arch/arm/mach-imx/mach-pcm037.c:407:30: warning: symbol
'pcm970_sja1000_platform_data' was not declared. Should it be static?
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Ma Feng <mafeng.ma@huawei.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
There are new drivers for functionality of that family
(RTC and ADC), so enable them, since they are used by
various i.MX6 boards.
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The iomuxc-gpr node is not used and causes the following dtc
warning with W=1:
arch/arm/boot/dts/imx50.dtsi:286.28-289.6: Warning (unique_unit_address): /soc/bus@50000000/iomuxc@53fa8000: duplicate unit-address (also used in node /soc/bus@50000000/iomuxc-gpr@53fa8000)
Remove the node to fix the warning.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Let the PHY generate the RX and TX delay on the Odroid-C1 and MXIII
Plus.
Previously we did not know that these boards used an RX delay. We
assumed that setting the TX delay on the MAC side It turns out that
these boards also require an RX delay of 2ns (verified on Odroid-C1,
but the u-boot code uses the same setup on both boards). Ethernet only
worked because u-boot added this RX delay on the MAC side.
The 4ns TX delay was also wrong and the result of using an unsupported
RGMII TX clock divider setting. This has been fixed in the driver with
commit bd6f48546b ("net: stmmac: dwmac-meson8b: Fix the RGMII TX
delay on Meson8b/8m2 SoCs").
Switch to phy-mode "rgmii-id" to let the PHY side handle all the delays,
(as recommended by the Ethernet maintainers anyways) to correctly
describe the need for a 2ns RX as well as 2ns TX delay on these boards.
This fixes the Ethernet performance on Odroid-C1 where there was a huge
amount of packet loss when transmitting data due to the incorrect TX
delay.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200512215148.540322-3-martin.blumenstingl@googlemail.com
Add the "timing-adjusment" clock now that we now that this is connected
to the PRG_ETHERNET registers. It is used internally to generate the
RGMII RX delay no the MAC side (if needed).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200512215148.540322-2-martin.blumenstingl@googlemail.com
Use the Meson8m2 specific USB2 PHY compatible string. The 3.10 vendor
kernel has at least one known difference between Meson8 and Meson8m2:
Meson8m2 sets the ACA_ENABLE bit while Meson8 doesn't.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200515202520.1487514-1-martin.blumenstingl@googlemail.com
Testing with a USB RNDIS connection and iperf3 gives the following
results:
- From the host computer to the device at ~250Mbit/s
- From the device to the host computer at ~76Mbit/s
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200504195105.2909711-1-martin.blumenstingl@googlemail.com
With dmtimer and 32k counter being initialized based on devicetree data,
we can just drop the old timer code.
This still leaves the omap5 and dra7 realtime_counter_init() that
depend on the smc calls and control module platform code for the dra7
quirk init.
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Keerthy <j-keerthy@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We can now init system timers using the dmtimer and 32k counter
based on only devicetree data and drivers/clocksource timers.
Let's configure the clocksource and clockevent, and drop the old
unused platform data.
As we're just dropping platform data, and the early platform data
init is based on the custom ti,hwmods property, we want to drop
both the platform data and ti,hwmods property in a single patch.
Since the dmtimer can use both 32k clock and system clock as the
source, let's also configure the SoC specific default values. The
board specific dts files can reconfigure these with assigned-clocks
and assigned-clock-parents as needed.
Let's also update the dts file to use #include while at it.
Cc: devicetree@vger.kernel.org
Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Keerthy <j-keerthy@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We can now init system timers using the dmtimer and 32k counter
based on only devicetree data and drivers/clocksource timers.
Let's configure the clocksource and clockevent, and drop the old
unused platform data.
As we're just dropping platform data, and the early platform data
init is based on the custom ti,hwmods property, we want to drop
both the platform data and ti,hwmods property in a single patch.
Since the dmtimer can use both 32k clock and system clock as the
source, let's also configure the SoC specific default values. The
board specific dts files can reconfigure these with assigned-clocks
and assigned-clock-parents as needed.
Note that for ti81xx, also timer1 is of type 2 unlike on am335x
where timer1 is type1 while the rest of the timers are type 2.
Cc: devicetree@vger.kernel.org
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Graeme Smecher <gsmecher@threespeedlogic.com>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Keerthy <j-keerthy@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We can now init system timers using the dmtimer and 32k counter
based on only devicetree data and drivers/clocksource timers.
Let's configure the clocksource and clockevent, and drop the old
unused platform data.
As we're just dropping platform data, and the early platform data
init is based on the custom ti,hwmods property, we want to drop
both the platform data and ti,hwmods property in a single patch.
Since the dmtimer can use both 32k clock and system clock as the
source, let's also configure the SoC specific default values. The
board specific dts files can reconfigure these with assigned-clocks
and assigned-clock-parents as needed.
Let's also update the dts file to use #include while at it.
Cc: devicetree@vger.kernel.org
Cc: Adam Ford <aford173@gmail.com>
Cc: Andreas Kemnade <andreas@kemnade.info>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: "H. Nikolaus Schaller" <hns@goldelico.com>
Cc: Keerthy <j-keerthy@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We can now init system timers using the dmtimer and 32k counter
based on only devicetree data and drivers/clocksource timers.
Let's configure the clocksource and clockevent, and drop the old
unused platform data.
As we're just dropping platform data, and the early platform data
init is based on the custom ti,hwmods property, we want to drop
both the platform data and ti,hwmods property in a single patch.
Since the dmtimer can use both 32k clock and system clock as the
source, let's also configure the SoC specific default values. The
board specific dts files can reconfigure these with assigned-clocks
and assigned-clock-parents as needed.
Note that similar to omap_init_time_of(), we now need to call
omap_clk_init() also from omap5_realtime_timer_init().
Cc: devicetree@vger.kernel.org
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Keerthy <j-keerthy@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We can now init system timers using the dmtimer and 32k counter
based on only devicetree data and drivers/clocksource timers.
Let's configure the clocksource and clockevent, and drop the old
unused platform data.
As we're just dropping platform data, and the early platform data
init is based on the custom ti,hwmods property, we want to drop
both the platform data and ti,hwmods property in a single patch.
Since the dmtimer can use both 32k clock and system clock as the
source, let's also configure the SoC specific default values. The
board specific dts files can reconfigure these with assigned-clocks
and assigned-clock-parents as needed.
Cc: devicetree@vger.kernel.org
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Keerthy <j-keerthy@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We can now init system timers using the dmtimer and 32k counter
based on only devicetree data and drivers/clocksource timers.
Let's configure the clocksource and clockevent, and drop the old
unused platform data.
As we're just dropping platform data, and the early platform data
init is based on the custom ti,hwmods property, we want to drop
both the platform data and ti,hwmods property in a single patch.
Since the dmtimer can use both 32k clock and system clock as the
source, let's also configure the SoC specific default values. The
board specific dts files can reconfigure these with assigned-clocks
and assigned-clock-parents as needed.
Cc: devicetree@vger.kernel.org
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Keerthy <j-keerthy@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We can now init system timers using the dmtimer and 32k counter
based on only devicetree data and drivers/clocksource timers.
Let's configure the clocksource and clockevent, and drop the old
unused platform data.
As we're just dropping platform data, and the early platform data
init is based on the custom ti,hwmods property, we want to drop
both the platform data and ti,hwmods property in a single patch.
Since the dmtimer can use both 32k clock and system clock as the
source, let's also configure the SoC specific default values. The
board specific dts files can reconfigure these with assigned-clocks
and assigned-clock-parents as needed.
Cc: devicetree@vger.kernel.org
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Keerthy <j-keerthy@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This allows us to move the SoCs to probe system timers one SoC
at at time. As arch/arm/mach-omap2/timer.c will be eventually gone,
let's just add omap_init_time_of() to board-generic.c directly.
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Keerthy <j-keerthy@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The decompressor can load from anywhere in memory, and the only reason
the EFI stub code relocates it is to ensure it appears within the first
128 MiB of memory, so that the uncompressed kernel ends up at the right
offset in memory.
We can short circuit this, and simply jump into the decompressor startup
code at the point where it knows where the base of memory lives. This
also means there is no need to disable the MMU and caches, create new
page tables and re-enable them.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Nicolas Pitre <nico@fluxnic.net>
We will be running the decompressor in place after a future patch,
instead of copying it around first. This means we no longer have to
disable and re-enable the MMU and caches either. However, this means
we will be loaded with the restricted permissions set by the UEFI
firmware, which means that we have to move the GOT table into the
data section in order for the contents to be writable by the code
itself.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Nicolas Pitre <nico@fluxnic.net>
The remaining contents of LC0 are only used after the point in the
decompressor startup code where we enter via 'wont_overwrite'. So
move the loading of the LC0 structure after it. This will allow us
to jump to wont_overwrite directly from the EFI stub, and execute
the decompressor in place at the offset it was loaded by the UEFI
firmware.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Nicolas Pitre <nico@fluxnic.net>
In preparation of moving the handling of the LC0 object to a later stage
in the decompressor startup code, move out _edata and the initial value
of the stack pointer, which are needed earlier than the remaining
contents of LC0.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Nicolas Pitre <nico@fluxnic.net>
Move mmc nodes to be compatible with the sdhci-omap driver. The following
modifications are required for omap_hsmmc specific properties:
ti,non-removable: convert to the generic mmc non-removable
ti,needs-special-reset: co-opted into the sdhci-omap driver
ti,dual-volt: removed. Legacy property not used in am335x or am43xx
ti,needs-special-hs-handling: removed. Legacy property not used in am335x
or am43xx
Also since the sdhci-omap driver does not support runtime PM, explicitly
disable the mmc3 instance in the dtsi.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Before breaking up LC0 into different pieces, move out the variable
that is already place-relative (given that it subtracts 'restart' in
the expression) and so its value does not need to be added to the
runtime address of the LC0 symbol itself.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Nicolas Pitre <nico@fluxnic.net>
Unwind information for init sections is placed in .ARM.exidx.init.text
and .ARM.extab.init.text. The module core doesn't know that these are
init sections so they are allocated along with the core sections, and if
the core and init sections get allocated in different memory regions
(which is possible with CONFIG_ARM_MODULE_PLTS=y) and they can't reach
each other, relocation fails:
final section addresses:
...
0x7f800000 .init.text
..
0xcbb54078 .ARM.exidx.init.text
..
section 16 reloc 0 sym '': relocation 42 out of range (0xcbb54078 ->
0x7f800000)
Fix this by informing the module core that these sections are init
sections, and by removing the init unwind tables before the module core
frees the init sections.
Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
call_undef_hook() in traps.c applies the same instr_mask for both 16-bit
and 32-bit thumb instructions. If instr_mask then is only 16 bits wide
(0xffff as opposed to 0xffffffff), the first half-word of 32-bit thumb
instructions will be masked out. This makes the function match 32-bit
thumb instructions where the second half-word is equal to instr_val,
regardless of the first half-word.
The result in this case is that all undefined 32-bit thumb instructions
with the second half-word equal to 0xde01 (udf #1) work as breakpoints
and will raise a SIGTRAP instead of a SIGILL, instead of just the one
intended 16-bit instruction. An example of such an instruction is
0xeaa0de01, which is unallocated according to Arm ARM and should raise a
SIGILL, but instead raises a SIGTRAP.
This patch fixes the issue by setting all the bits in instr_mask, which
will still match the intended 16-bit thumb instruction (where the
upper half is always 0), but not any 32-bit thumb instructions.
Cc: Oleg Nesterov <oleg@redhat.com>
Signed-off-by: Fredrik Strupe <fredrik@strupe.net>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
The commit 3e347261a8 ("[PATCH] sparsemem extreme implementation")
made SPARSMEM_EXTREME the default option for configurations that enable
SPARSEMEM.
For ARM systems with handful of memory banks SPARSEMEM_EXTREME is an
overkill.
Ensure that SPARSMEM_STATIC is enabled in the configurations that use
SPARSEMEM.
Fixes: 3e347261a8 ("[PATCH] sparsemem extreme implementation")
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Mike Rapoport <rppt@linux.ibm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Remove the disable-wp attribute from &emmc as it is, according to
Documentation/devicetree/bindings/mmc/mmc-controller.yaml:
"Not used in combination with eMMC or SDIO."
Suggested-by: Johan Jonker <jbx6244@gmail.com>
Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za>
Link: https://lore.kernel.org/r/20200406135006.23759-2-justin.swartz@risingedge.co.za
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The Mecer Xtreme Mini S6 features a wireless module, based on a
Realtek 8723BS, which provides WLAN and Bluetooth connectivity via
SDIO and UART interfaces respectively.
Define a simple MMC power sequence that declares the GPIO pins
connected to the module's WLAN Disable and Bluetooth Disable pins
as active low reset signals, because both signals must be deasserted
for WLAN radio operation.
Configure the host's SDIO interface for High Speed mode with 1.8v
I/O signalling and IRQ detection over a 4-bit wide bus.
Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za>
Link: https://lore.kernel.org/r/20200406135006.23759-1-justin.swartz@risingedge.co.za
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Current dts files with 'gpio-led' nodes were manually verified.
In order to automate this process leds-gpio.txt
has been converted to yaml. With this conversion a check
for pattern properties was added. A test with the command
below gives a screen full of warnings like:
arch/arm/boot/dts/rk3188-radxarock.dt.yaml: gpio-leds:
'blue', 'green', 'sleep'
do not match any of the regexes:
'(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
Fix these errors with help of the following rules:
1: Add nodename in the preferred form.
2: Always add a label that ends with '_led' to prevent conflicts
with other labels such as 'power' and 'mmc'
3: If leds need pinctrl add a label that ends with '_led_pin'
also to prevent conflicts with other labels.
patternProperties:
# The first form is preferred, but fall back to just 'led'
# anywhere in the node name to at least catch some child nodes.
"(^led-[0-9a-f]$|led)":
make ARCH=arm dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/leds/
leds-gpio.yaml
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20200428144933.10953-1-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The common LED binding wants the LED node names to start with led- and
then have just a single number.
Changing the naming for the 8 user LEDs from using user<x> to led-<x>.
Also there is no default-trigger named "mmc0" in the kernel, so use the
more generic "disk-activity".
Link: https://lore.kernel.org/r/20200513103016.130417-18-andre.przywara@arm.com
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Most Arm Ltd. boards are employing a layered bus structure, to map
the hardware design (SoC, motherboard, IOFPGA) and structure the DTs.
The "simple-bus" nodes only allow a limited set of node names. Switch
to use *-bus to be binding compliant.
This relies on a pending dt-schema.git fix for now:
https://github.com/devicetree-org/dt-schema/pull/38
Link: https://lore.kernel.org/r/20200513103016.130417-16-andre.przywara@arm.com
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
The UARTs for all Arm Ltd. boards were using "uart" as their node name
stub.
Replace that with the required "serial" string, to comply with the PL011
DT binding.
Link: https://lore.kernel.org/r/20200513103016.130417-14-andre.przywara@arm.com
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
The sama5d2 SoC has two dedicated I2C IPs that are enabled on
sama5d2_xplained. Add alias for the i2c devices to not rely on
probe order for the i2c device numbering.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200518114802.253660-1-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
The devicetree compiler complains when DT nodes without a reg property
live inside a (simple) bus node:
Warning (simple_bus_reg): Node /bus@8000000/motherboard-bus/refclk32khz
missing or empty reg/ranges property
Move the fixed clocks, the fixed regulator, the leds and the config bus
subtree to the root node, since they do not depend on any busses.
Link: https://lore.kernel.org/r/20200513103016.130417-5-andre.przywara@arm.com
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
The Arm Ltd. boards were using an outdated address convention in the DT
node names, by separating the high from the low 32-bits of an address by
a comma.
Remove the comma from the node name suffix to be DT spec compliant.
Link: https://lore.kernel.org/r/20200513103016.130417-3-andre.przywara@arm.com
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
The NV+ v2 has a WH1602 LCD panel (which is just a rebranded HD44780),
similar to the Netgear RN104, just with different GPIO assignments.
Signed-off-by: Brian J. Tarricone <brian@tarricone.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The timeout-ms property for i2c master nodes is undocumented, and as
never been supported. Drop it.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This round of fixes is almost exclusively device tree changes,
with trivial defconfig fixes and one compiler warning fix
added in.
A number of patches are to fix dtc warnings, in particular on
Amlogic, i.MX and Rockchips.
Other notable changes include:
Renesas:
- Fix a wrong clock configuration on R-Mobile A1,
- Fix IOMMU support on R-Car V3H
Allwinner
- Multiple audio fixes
Qualcomm
- Use a safe CPU voltage on MSM8996
- Fixes to match a late audio driver change
Rockchip:
- Some fixes for the newly added Pinebook Pro
NXP i.MX:
- Fix I2C1 pinctrl configuration for i.MX27 phytec-phycard board.
- Fix imx6dl-yapp4-ursa board Ethernet connection.
OMAP:
- A regression fix for non-existing can device on am534x-idk
- Fix flakey wlan on droid4 where some devices would not connect
at all because of internal pull being used with an external pull
- Fix occasional missed wake-up events on droid4 modem uart
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAl6/Dx8ACgkQmmx57+YA
GNmRJw/+MjrVUuD+KHjkfOX68zJ4puLluj1PGn//t0DnQPkrmPnDMP0gs/62cMNc
4U3SIlYCivSOiz6N6gyvEU+j/sMqzCn7J3jBsUqCEvcOBm0X3b1T6OAwK8kp1TVq
zAbEs/YaHBYKPIUOrstZwLkTCDLUXQlqPs7aEubyZ+awqa+EW9joGDyrus53jCIP
pbaLV+52TGpOENfKRv05k6eJrtLfNM6Yt5qoCPRE4DYvbSumwXarPT/WOC1V5C/9
KUwh3bVi6bRUEuhIHomnKqLK+GA8DMVw+HU9vNHDHexbdSQGsIMuFrCyWktwEizq
7FTAKpEiuFJkOD6eyNCe3x5f2W5isDRvV8ehULaCRa8CbiBJUGY9wOdllMAYLuna
haFGjJ8aKIPwgmoxjFL534hXprAMAGAAm8ZUcULIS+X8/8R2c+fzIadJ6ZS+VmNh
2Nq4qNAPh8pTJJXzM9oNtI7HQLwOkAp49/r5FOrSReUFQVt84ofHy/QxAUdDMTkq
7250L8G+SrpDQiNxck2pOYIKNqQcRUeJU60fTlkQlljBIjKOTn9zUrEhYLpujD3g
vKLBmpek67fHfXB/sBpFOALCYw7prRacIyZrDHUKgEhP85WnkXXoZ+NQL5edgZGC
qZ+h5xeRc6eBFYSP30HYQYL4fhTYokvWSdu5AbWBdJlAoAHk1mQ=
=fXzR
-----END PGP SIGNATURE-----
Merge tag 'arm-soc-fixes-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC/dt fixes from Arnd Bergmann:
"This round of fixes is almost exclusively device tree changes, with
trivial defconfig fixes and one compiler warning fix added in.
A number of patches are to fix dtc warnings, in particular on Amlogic,
i.MX and Rockchips.
Other notable changes include:
Renesas:
- Fix a wrong clock configuration on R-Mobile A1
- Fix IOMMU support on R-Car V3H
Allwinner
- Multiple audio fixes
Qualcomm
- Use a safe CPU voltage on MSM8996
- Fixes to match a late audio driver change
Rockchip:
- Some fixes for the newly added Pinebook Pro
NXP i.MX:
- Fix I2C1 pinctrl configuration for i.MX27 phytec-phycard board
- Fix imx6dl-yapp4-ursa board Ethernet connection
OMAP:
- A regression fix for non-existing can device on am534x-idk
- Fix flakey wlan on droid4 where some devices would not connect at
all because of internal pull being used with an external pull
- Fix occasional missed wake-up events on droid4 modem uart"
* tag 'arm-soc-fixes-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (51 commits)
ARM: dts: iwg20d-q7-dbcm-ca: Remove unneeded properties in hdmi@39
ARM: dts: renesas: Make hdmi encoder nodes compliant with DT bindings
arm64: dts: renesas: Make hdmi encoder nodes compliant with DT bindings
arm64: defconfig: add MEDIA_PLATFORM_SUPPORT
arm64: defconfig: ARCH_R8A7795: follow changed config symbol name
arm64: defconfig: add DRM_DISPLAY_CONNECTOR
arm64: defconfig: DRM_DUMB_VGA_DAC: follow changed config symbol name
ARM: oxnas: make ox820_boot_secondary static
ARM: dts: r8a7740: Add missing extal2 to CPG node
ARM: dts: omap4-droid4: Fix occasional lost wakeirq for uart1
ARM: dts: omap4-droid4: Fix flakey wlan by disabling internal pull for gpio
arm64: dts: allwinner: a64: Remove unused SPDIF sound card
arm64: dts: allwinner: a64: pinetab: Fix cpvdd supply name
arm64: dts: meson-g12: remove spurious blank line
arm64: dts: meson-g12b-khadas-vim3: add missing frddr_a status property
arm64: dts: meson-g12-common: fix dwc2 clock names
arm64: dts: meson-g12b-ugoos-am6: fix usb vbus-supply
arm64: dts: freescale: imx8mp: update input_val for AUDIOMIX_BIT_STREAM
ARM: dts: r7s9210: Remove bogus clock-names from OSTM nodes
ARM: dts: rockchip: fix pinctrl sub nodename for spi in rk322x.dtsi
...
Support for Altera SOCFPGA systems depends on ARCH_MULTI_V7, and thus on
ARCH_MULTIPLATFORM.
As the latter selects PCI_DOMAINS_GENERIC, there is no need for
ARCH_SOCFPGA to select PCI_DOMAINS_GENERIC.
Link: https://lore.kernel.org/r/20200505150722.1575-16-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Support for CSR SiRF SoCs depends on ARCH_MULTI_V7.
As the latter selects HAVE_SMP, there is no need for ARCH_ATLAS7 to
select HAVE_SMP.
Link: https://lore.kernel.org/r/20200505150722.1575-14-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Barry Song <baohua@kernel.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Support for Marvell Armada 375, 380, 385, and 39x SoCs depends on
ARCH_MULTI_V7.
As the latter selects HAVE_SMP, there is no need for MACH_ARMADA_375,
MACH_ARMADA_38X, and MACH_ARMADA_39X to select HAVE_SMP.
Link: https://lore.kernel.org/r/20200505150722.1575-12-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@bootlin.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Support for Marvell MMP ARMv5 platforms depends on ARCH_MULTI_V5, and
thus on ARCH_MULTIPLATFORM.
As the latter selects COMMON_CLK, there is no need for MACH_MMP_DT to
select COMMON_CLK.
Link: https://lore.kernel.org/r/20200505150722.1575-11-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Support for TI DaVinci SoCs depends on ARCH_MULTI_V5, and thus on
ARCH_MULTIPLATFORM.
As the latter selects TIMER_OF, there is no need for MACH_DA8XX_DT to
select TIMER_OF.
Link: https://lore.kernel.org/r/20200505150722.1575-9-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Support for Cirrus Logic EP721x/EP731x-based SoCs depends on
ARCH_MULTI_V7, and thus on ARCH_MULTIPLATFORM.
As the latter selects AUTO_ZRELADDR, TIMER_OF, COMMON_CLK,
GENERIC_CLOCKEVENTS, and USE_OF, there is no need for ARCH_CLPS711X to
select any of them.
Link: https://lore.kernel.org/r/20200505150722.1575-8-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Support for Marvell Berlin SoCs depends on ARCH_MULTI_V7.
As the latter selects HAVE_SMP, there is no need for MACH_BERLIN_BG2 to
select HAVE_SMP.
Link: https://lore.kernel.org/r/20200505150722.1575-7-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Support for the 6th generation Aspeed SoCs depends on ARCH_MULTI_V7.
As the latter selects HAVE_SMP, there is no need for MACH_ASPEED_G6 to
select HAVE_SMP.
Link: https://lore.kernel.org/r/20200505150722.1575-6-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Joel Stanley <joel@jms.id.au>
Cc: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Support for the Alphascale ASM9260 platform depends on ARCH_MULTI_V5,
and thus on ARCH_MULTIPLATFORM.
As the latter selects GENERIC_CLOCKEVENTS, there is no need for
MACH_ASM9260 to select GENERIC_CLOCKEVENTS.
Link: https://lore.kernel.org/r/20200505150722.1575-5-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Oleksij Rempel <linux@rempel-privat.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Support for Annapurna Labs Alpine platforms depends on ARCH_MULTI_V7.
As the latter selects HAVE_SMP, there is no need for ARCH_ALPINE to
select HAVE_SMP.
Link: https://lore.kernel.org/r/20200505150722.1575-4-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Tsahee Zidenberg <tsahee@annapurnalabs.com>
Cc: Antoine Tenart <antoine.tenart@bootlin.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Support for Actions Semi SoCs depends on ARCH_MULTI_V7, and thus on
ARCH_MULTIPLATFORM.
As the latter selects COMMON_CLK, there is no need for ARCH_ACTIONS to
select COMMON_CLK.
Link: https://lore.kernel.org/r/20200505150722.1575-3-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Andreas Färber <afaerber@suse.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The ARM Architected timer is available on ARMv7 SoCs only.
As both ARCH_MULTIPLATFORM and ARM_SINGLE_ARMV7M select
GENERIC_CLOCKEVENTS, there is no need for HAVE_ARM_ARCH_TIMER to select
GENERIC_CLOCKEVENTS.
Link: https://lore.kernel.org/r/20200505150722.1575-2-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Fix a wrong clock configuration on R-Mobile A1,
- Minor fixes that are fast-tracked to avoid introducing regressions
during conversion of DT bindings to json-schema.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCXr5jTgAKCRCKwlD9ZEnx
cKSMAQCGIyrVtXHISZSFlp3poR1bBMejfxvZWmLIBzIPSw28SQEAqGTxP7dONrXY
JIbYmduRiRfWK6h0ghr769xp/KQPIAQ=
=dl06
-----END PGP SIGNATURE-----
Merge tag 'renesas-fixes-for-v5.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes
Renesas fixes for v5.7 (take two)
- Fix a wrong clock configuration on R-Mobile A1,
- Minor fixes that are fast-tracked to avoid introducing regressions
during conversion of DT bindings to json-schema.
* tag 'renesas-fixes-for-v5.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
ARM: dts: iwg20d-q7-dbcm-ca: Remove unneeded properties in hdmi@39
ARM: dts: renesas: Make hdmi encoder nodes compliant with DT bindings
arm64: dts: renesas: Make hdmi encoder nodes compliant with DT bindings
ARM: dts: r8a7740: Add missing extal2 to CPG node
Link: https://lore.kernel.org/r/20200515125043.22811-1-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This contains core changes needed for the CPU frequency scaling and CPU
idle drivers on Tegra20 and Tegra30.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl6+pNMTHHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zoYq9EACR0PciY3lTiQdmNqUGqEXp044Fg9CE
CpnjcyJh9a+3wzwtx8ZjEng7KhwUyj3trKW6gpazjaNFTzNgOqVoYEZIetOJIc5u
ZHFF7OYr+ZO5xmy4jYRuj6ZHSznn7ImrLLL8JVuYQHFHgxTlM1enSCRG3HN7Z2c7
MUmM9wnio0amREKZXgnSkN87OO1r8kaKqWFUjwqs6K8j5NvTGVYW+5YIf4Zlc7PB
5yKTt2EdPx1LpoVA+b8K/sRe8rNDwC4vxuVoDpXzBvM0s2kMIy+tIEx1plQLwkDV
dHSMT8sk6XD9yVAuzEqai341w5dm02GTfKvSy/gLoZ2NTshF99CnpLaUd3aicq/n
/9lkRtxYtb8uvlB+vKlv/LaUsDqA6casXXKstpGTUD5Oc2pSsXNGGTBhGfqwNO+v
VLNPNYLDKZbXx4HEhn7vH0c43WXTD8ydxa91HZf1GcL6hcrnklI/rbnX7QCKuVzc
IsYZPfQ1YclvaoC4wRMBhR5Hj3AW7l3N2k5oTPD+F8cIfxF5e+eELYdGOvs27ncM
SnaNve9x1IOAZmCKEQhxQorjT1nDSDd7quasXQ9nzx7bTgIa7H+QsFOYkrIPLNHi
ld7TpnK6/M4b6gaXqb6rvWnYKHTfNuP59843AUQafpnWhYHZJvrjg6n6XJNUe5g6
bvXlQIbx/fhfdQ==
=7XEQ
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-5.8-arm-core' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/soc
ARM: tegra: Core changes for v5.8-rc1
This contains core changes needed for the CPU frequency scaling and CPU
idle drivers on Tegra20 and Tegra30.
* tag 'tegra-for-5.8-arm-core' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Create tegra20-cpufreq platform device on Tegra30
ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30
ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124
ARM: tegra: Correct PL310 Auxiliary Control Register initialization
ARM: tegra: Do not fully reinitialize L2 on resume
ARM: tegra: Initialize r0 register for firmware wake-up
firmware: tf: Different way of L2 cache enabling after LP2 suspend
firmware: tegra: Make BPMP a regular driver
Link: https://lore.kernel.org/r/20200515145311.1580134-10-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add debug-ll support for RZ/G1H.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCXr5h7AAKCRCKwlD9ZEnx
cNCQAQCDwAbM0cVFjv8anAImZEVXrekVFqMTM4NG2WewPPfuvAD/W6UAgwvGJFeY
FzRJOu4RUrlLozQpyh7F2sd5lw9JHws=
=fTm6
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-soc-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/soc
Renesas ARM SoC updates for v5.8 (take two)
- Add debug-ll support for RZ/G1H.
* tag 'renesas-arm-soc-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
ARM: debug-ll: Add support for r8a7742
Link: https://lore.kernel.org/r/20200515100547.14671-4-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This series enables building various Versatile Express platform drivers
as modules. The primary target is the Fast Model FVP which is supported
in Android. As Android is moving towards their GKI, or generic kernel,
the hardware support has to be in modules. Currently ARCH_VEXPRESS
enables several built-in only drivers. Some of these are needed, but
some are only needed for older 32-bit VExpress platforms and can just
be disabled.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAl68MeUQHHJvYmhAa2Vy
bmVsLm9yZwAKCRD6+121jbxhw/96EACb8MVXgss/RBPfcfKeb46tgdP6XfxlDqma
/lWdd88KM3YZI0ym8uBQZX/XwUmuU1bcbxv9E/j0i+i/YER7qrdbsYfeU5CLhAbA
vidC1fRuqXNPZRsnc5PnVP913PvRiNgNfGM4BUxz5i7aLfl9IGcujdY/uekEoo2i
9nyAYxMmZBZsHU28y0nXuZaUK7mC7YDZFXM4z6u6Q0nnbS4r5C8b+cUCeTk0w8Ex
pA1pTWjRFvnpT1wZZU65FRaxv33dO3MbReT84rbQvrRo/IDKFi+VfAw4/UJFWBoF
Ck1cmEchjPcTf7ut/clET+LqCuCVESwmDGmOhJ78m7m8WxsdoaUSfJSsPNMF7dxE
+ePIvl/jovqMnCCR+RKbpcIzQvOckk6zp1xnqQNDii46BSCayXQEYtoxRj0B0X3k
c4izH58Z7NTUa+IbVf02bwqOl2qMlGSp2KocXNTrBqznRkmCiWB+HHmrX/TQusWL
22sDHuxGRjOhD2yINOMQGeol7fXmIH7M2rjjpoGR1cWGRT/Xj7xU3Eme/VAE0nQv
VHFoWW6YDVAfsuwJePgPrHysZcH96mhTCRVo9Gx1xC0IaZpcxFPQkk0LTKtu5CWY
jYA1ml1vLDCl7l/yzfQjdtSm6lLg15ihZ+M6jbPdPacdBqmBL5UmPf30sW53XXAG
BagmwNHCNQ==
=c5eS
-----END PGP SIGNATURE-----
Merge tag 'vexpress-modules-for-soc-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux into arm/soc
VExpress modularization
This series enables building various Versatile Express platform drivers
as modules. The primary target is the Fast Model FVP which is supported
in Android. As Android is moving towards their GKI, or generic kernel,
the hardware support has to be in modules. Currently ARCH_VEXPRESS
enables several built-in only drivers. Some of these are needed, but
some are only needed for older 32-bit VExpress platforms and can just
be disabled.
* tag 'vexpress-modules-for-soc-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
ARM: vexpress: Don't select VEXPRESS_CONFIG
bus: vexpress-config: Support building as module
vexpress: Move setting master site to vexpress-config bus
bus: vexpress-config: simplify config bus probing
bus: vexpress-config: Merge vexpress-syscfg into vexpress-config
mfd: vexpress-sysreg: Support building as a module
mfd: vexpress-sysreg: Use devres API variants
mfd: vexpress-sysreg: Drop unused syscon child devices
mfd: vexpress-sysreg: Drop selecting CONFIG_CLKSRC_MMIO
clk: vexpress-osc: Support building as a module
clk: vexpress-osc: Use the devres clock API variants
clk: versatile: Only enable SP810 on 32-bit by default
clk: versatile: Rework kconfig structure
amba: Retry adding deferred devices at late_initcall
arm64: vexpress: Don't select CONFIG_POWER_RESET_VEXPRESS
ARM: vexpress: Move vexpress_flags_set() into arch code
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
SoC related changes for omaps:
- Use ard instead of adrl for sleep34xx.S for clang
- Stop selecting MIGHT_HAVE_CACHE_L2X0, it's already selected
by ARCH_MULTI_V6_V7
- Make omap5_erratum_workaround_801819() and am43xx_get_rtc_base_addr()
static
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAl68IZcRHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXOg2hAA2iwf9m/4RS/Lhcgs0yyNc93//rtudAnS
QuRzpqwfAfmSbxMxVKbz8Qn3RfEpNOKFb9WBoZZK4jvBn1o8ydpo1k7EXN4TZoEA
Kea3UzGUJGYzgPxacaupG40uWy0cV1DvvzI9oRp2UMr8y6UcZ8EcPAb1JE6kWSi0
0YfSjLqU1uq5FZmxI5dGVznDx87fh4EBmZ8PHjhE+MQFZn5HRDeKUQs6bSGNjT9r
+ie8YNCOuE68GAvNsUTtW2cCjBye2mgl2sVGath2CoUHX/VxUQ/vc0b+0J36OfmV
ZatL9yYQTDjZ4KHofo153Vc0RYjOCh8TipypXDxr5F+PMlYfV/SxuzLSpSWXh2VA
/gyo9RarF3n1MQmfsmB1QDxUJ/A+3QPnR3m1OiZ5s+oMjpGgzoAHZ8+gMmcTd6c/
7d5EqsH3S209zjZo48jpPceHatKwa4fqMx8MvcP+pE3w0LgKVMoW+bxc/MtVrVnp
9+7eI23Jor3i4HLVUEZUEVvbRN4pR2+nk0K5IyPnmvmaQN0eL7LyLLAKUMD/X0W6
RcN6SIQTTQmGWRKVxbHxg7Q1uBzrnpmPLaEZ3yMn/PSat5jnvyAe2ykUHPosyxSh
TNabTOwK7YPjMnMgQqp0saCcSSD73m8XsOOGezMuy8bJQVia59H/cq4dyXcrYdOC
TkgWctOI1g0=
=FJKz
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v5.8/soc-signed-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/soc
SoC changes for omaps for v5.8 merge window
SoC related changes for omaps:
- Use ard instead of adrl for sleep34xx.S for clang
- Stop selecting MIGHT_HAVE_CACHE_L2X0, it's already selected
by ARCH_MULTI_V6_V7
- Make omap5_erratum_workaround_801819() and am43xx_get_rtc_base_addr()
static
* tag 'omap-for-v5.8/soc-signed-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: pm33xx-core: Make am43xx_get_rtc_base_addr static
ARM: omap2: make omap5_erratum_workaround_801819 static
ARM: omap2plus: Drop unneeded select of MIGHT_HAVE_CACHE_L2X0
ARM: OMAP2+: drop unnecessary adrl
Link: https://lore.kernel.org/r/pull-1589387719-605999@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
v5.8, please pull the following:
- Florian removes a print of a kernel virtual address in the Brahma-B15
read-ahead cache driver
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAl64W5oACgkQh9CWnEQH
BwR59A//YTPFE7IkO6fwEi9DDSgvaSk5nPQPjtsfRuv3sWii2RV1WOZGlfi+GGmc
cnfRerhv+90RzKW5kSb1wQSgQ7Irj0T5jzsFR5mw0NBM2507+1ixBZGM18dD/fn3
ddNCEGDsafFf0Z5rxgORS4hR8eA6z2b5M5vowVDrSeWO/fcL6yP031CEYhe87l5V
UTAWQGbdV5ZN+Ye3vm5t46+/kxYIEMTb7k0ORWNUBEHRZV1gVMwELG6OJanP1yWr
cKbxwaMOp0T43ecjb50slu3IRemaiW+PO/kNWbEGy7cqVvC72QUhh+K6YJKXrxqm
pl0Hh/LjeH+/AbMODPOvJ+41Gm8aYchJFnbFAMB6AOs6Ioe2txRqDXdGWEgIXR1V
xAPErzgc4VWsd6kH2axl1gH4AWxtlB3q6DH4WK1SESIpT6MyBlIW+H17TFQZSAAQ
gFF90QaBfY79OZUxsS+g/vOzmC+2RrJdf6HUYgO/pLjXQZoFqjJU4X/3ETftop18
RqtNpeA4AW7yHil056Hck0YLYbi1+mhbiJRuv8ujnAPtdfB1y6oc8gUZECP7g88C
Gz5KbFW43xKl1fiylGnJSkTqcpEqSK+rvhfP8U+clA6ox1+9kN3sC3J7szeQiK61
rlmSwa0x8DoPfvxh9Kb8Z9nm8xNlgUWpnUslvvj7apUyGpnuERg=
=Pb95
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-5.8/soc' of https://github.com/Broadcom/stblinux into arm/soc
This pull request contains Broadcom ARM-based machine/SoC changes for
v5.8, please pull the following:
- Florian removes a print of a kernel virtual address in the Brahma-B15
read-ahead cache driver
* tag 'arm-soc/for-5.8/soc' of https://github.com/Broadcom/stblinux:
ARM: mm: Remove virtual address print from B15 RAC driver
Link: https://lore.kernel.org/r/20200511210522.28243-4-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Introduce ARCH_REALTEK also for 32-bit arm, and update MAINTAINERS.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEF08DRxvMIhphdW+W+i7RLT5+AT8FAl64c90RHGFmYWVyYmVy
QHN1c2UuZGUACgkQ+i7RLT5+AT9zeg//UDUtCIqGo/KFlYlcpDwNFpQRgHUAiFGK
DttJLYmuyL7qHEUIBJfHKp4mjDUVb4zn7DWgvr4Kob+ilbokpqToRiSRKUyFB2ja
00U6IGV0x9B3azLSb3M4WbqVpGsum/YfGIW6C+vW0bOgIdlSy7oZpgPy+2WS8n5l
Kg5b55wtVRduLp3e9VwGCg/IEMB5OxNDFeEoNMck2lU7aqhdlSkPn+UKHnm4NF+p
JirYfloarGNOOAglxbzAHSNzl6UzxA3WoIaDN1SyXGVqhtJ7qbYv30MkIGeC9TCE
4xn9A4Qz2ViZsg+kLH5PyshDmRzOsccuxzajjws+c25zD35fnEz4nO7EXGogS2oN
nOEOFvYTVHOFyQX06hPBeAJWSZ/exWArD71gxxjT5irLawdKQKsuqDecPhehryHK
4tURsSMSDEaoj/VFUyQCmpN8yuXhFYdahqLVvDF7m6OxmvODTwI63faQOuzZ9YnB
i0krrZu8xG6eY3/ukpHYxzo0Mz5Si36c65duy1cJsfqxmNkhZnIbnsRGIzkeNRyA
lvqEqBNZKrawE9MTTEgLGBo73o2vMSL8ikc+J9055K9rKeWZKYC8X//vXmToIm4e
wNXZHlDVkVEzpZrnakWCz8x0TFdSIx9T1Jhc2OaWPmYZvhMFJCW7zogZsm+65iKQ
54Rwb7l+Cv8=
=0APm
-----END PGP SIGNATURE-----
Merge tag 'realtek-soc-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek into arm/soc
Realtek Arm based SoC for v5.8
Introduce ARCH_REALTEK also for 32-bit arm, and update MAINTAINERS.
* tag 'realtek-soc-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek:
MAINTAINERS: Add Realtek arm DT files
ARM: Prepare Realtek RTD1195
Link: https://lore.kernel.org/r/20200510232158.18477-1-afaerber@suse.de
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The Marvell MMP platform code is not a clock provider, and just needs to
call of_clk_init().
Hence it can include <linux/of_clk.h> instead of <linux/clk-provider.h>.
Link: https://lore.kernel.org/r/20200505154536.4099-4-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The Mediatek platform code is not a clock provider, and just needs to
call of_clk_init().
Hence it can include <linux/of_clk.h> instead of <linux/clk-provider.h>.
Link: https://lore.kernel.org/r/20200505154536.4099-3-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The ARM time code is not a clock provider, and just needs to call
of_clk_init().
Hence it can include <linux/of_clk.h> instead of <linux/clk-provider.h>.
Link: https://lore.kernel.org/r/20200505154536.4099-2-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add Basic support for the new RZ/G1H SoC.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCXqqFRQAKCRCKwlD9ZEnx
cJbfAP9NprK6JzvJlvPXukIK8Q85oyKgabu1F702IWt956CHAwD/dEMzMPtxFKjg
HxbNb/OoyZA0wf4lpveF1Ai3qMy5oAE=
=FLj8
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-soc-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/soc
Renesas ARM SoC updates for v5.8
- Add Basic support for the new RZ/G1H SoC.
* tag 'renesas-arm-soc-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
ARM: shmobile: r8a7742: Basic SoC support
Link: https://lore.kernel.org/r/20200430084849.1457-4-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Drop unneeded SPARSE_IRQ selection.
- Drop a bunch of other unneed selections already
selected by multiplatform overall Kconfig.
- Remove the dead sched_clock() code in plat-versatile.
- Drop the mapping of the IB2 registers. Now handled
by the PL11x DRM driver.
- Add a bus driver for the Integrator/AP logic modules,
along with its device tree bindings.
- Retire the LM and IM-PD1 boardfile code: we now handle
this with the bus driver and device tree.
- Select some Integrator features needed for boot in
its KConfig.
- Fix a minor MAINTAINERS entry.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAl6oiR4ACgkQQRCzN7AZ
XXNsHQ//bIMJb/WlfhCc5AqQQ58iPQvyh3zhaus7M9OvNy+OO/qQCRl6yVYlMVb+
qDS5iVWn5jG5ntGK0j/TYJn4C5R3pf/1k2cbN6YbNd4vtdz4hRftqQ3Lnvsz11qT
HeAOQhXGoGe1kLBrUC5jVf+bUmYogOFXwKTfBeVSenwzRvi15yCpqkoCS0G7Q8K0
tzwP291LGlXx4XSWwxa93Y8fbj2tOtokOqKlsHWzb0FH1YJkDt9SXQ754Tl/Igaw
9ya9DtFF5JcufPVVgVY7qkp9VAxrUXOhs8VvFUQ4VeODMODiY8/fw0BFcZ6nQoJw
5AZSJ9x6MeaDw3Pp00TUbnVdzL3OIvffdUcqD+nU83GMhZCVBluxGF/9Aamwl19e
eImdOk9+qhi84hidQ+iuP7ecsglAJPBJAuejU/8IovX7B96oWr0oT7Ttrpuv/xJZ
wRs7DcfcgyWxIyQYsv/tFwuhSGqveFPzMGgaZ/3wFzzaxSAtwdzmVMPOb8YVrrAx
AzZltlwFg4U9lgY9FfCW8gPNbN94w6nhRvzkJVFD+GQXVtOCf/jzLH3YDsyFRkND
QgnXkJ84weAoDdBtbc4yG2h0KoKAdd85gf37vTtwCrSWMKmPFPLTJeip46ahDTLk
KYxKAvhyuu73JldojRF8odo0E8z34wtkIZt/DcgbOu+C4mC029M=
=ylIo
-----END PGP SIGNATURE-----
Merge tag 'versatile-v5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into arm/soc
Versatile family updates for the v5.8 kernel series:
- Drop unneeded SPARSE_IRQ selection.
- Drop a bunch of other unneed selections already
selected by multiplatform overall Kconfig.
- Remove the dead sched_clock() code in plat-versatile.
- Drop the mapping of the IB2 registers. Now handled
by the PL11x DRM driver.
- Add a bus driver for the Integrator/AP logic modules,
along with its device tree bindings.
- Retire the LM and IM-PD1 boardfile code: we now handle
this with the bus driver and device tree.
- Select some Integrator features needed for boot in
its KConfig.
- Fix a minor MAINTAINERS entry.
* tag 'versatile-v5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
MAINTAINERS: adjust to renaming physmap_of_versatile.c
ARM: integrator: Add some Kconfig selections
ARM: integrator: Retire LM and IM-PD1 boardfile code
bus: Add driver for Integrator/AP logic modules
bus: Add DT bindings for Integrator/AP logic modules
ARM: versatile: Drop mapping IB2 module registers
ARM: versatile: Remove dead sched_clock code
ARM: realview: Drop unneeded select of multi-platform features
ARM: integrator: Drop unneeded select of SPARSE_IRQ
Link: https://lore.kernel.org/r/CACRpkdZR5LnnvrCnXodaTsam9-BuW+LkYSc+6jq-EisrRsq2eQ@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Move the bpf verifier trace check into the new switch statement in
HEAD.
Resolve the overlapping changes in hinic, where bug fixes overlap
the addition of VF support.
Signed-off-by: David S. Miller <davem@davemloft.net>
Pull networking fixes from David Miller:
1) Fix sk_psock reference count leak on receive, from Xiyu Yang.
2) CONFIG_HNS should be invisible, from Geert Uytterhoeven.
3) Don't allow locking route MTUs in ipv6, RFCs actually forbid this,
from Maciej Żenczykowski.
4) ipv4 route redirect backoff wasn't actually enforced, from Paolo
Abeni.
5) Fix netprio cgroup v2 leak, from Zefan Li.
6) Fix infinite loop on rmmod in conntrack, from Florian Westphal.
7) Fix tcp SO_RCVLOWAT hangs, from Eric Dumazet.
8) Various bpf probe handling fixes, from Daniel Borkmann.
* git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net: (68 commits)
selftests: mptcp: pm: rm the right tmp file
dpaa2-eth: properly handle buffer size restrictions
bpf: Restrict bpf_trace_printk()'s %s usage and add %pks, %pus specifier
bpf: Add bpf_probe_read_{user, kernel}_str() to do_refine_retval_range
bpf: Restrict bpf_probe_read{, str}() only to archs where they work
MAINTAINERS: Mark networking drivers as Maintained.
ipmr: Add lockdep expression to ipmr_for_each_table macro
ipmr: Fix RCU list debugging warning
drivers: net: hamradio: Fix suspicious RCU usage warning in bpqether.c
net: phy: broadcom: fix BCM54XX_SHD_SCR3_TRDDAPD value for BCM54810
tcp: fix error recovery in tcp_zerocopy_receive()
MAINTAINERS: Add Jakub to networking drivers.
MAINTAINERS: another add of Karsten Graul for S390 networking
drivers: ipa: fix typos for ipa_smp2p structure doc
pppoe: only process PADT targeted at local interfaces
selftests/bpf: Enforce returning 0 for fentry/fexit programs
bpf: Enforce returning 0 for fentry/fexit progs
net: stmmac: fix num_por initialization
security: Fix the default value of secid_to_secctx hook
libbpf: Fix register naming in PT_REGS s390 macros
...
Given the legacy bpf_probe_read{,str}() BPF helpers are broken on archs
with overlapping address ranges, we should really take the next step to
disable them from BPF use there.
To generally fix the situation, we've recently added new helper variants
bpf_probe_read_{user,kernel}() and bpf_probe_read_{user,kernel}_str().
For details on them, see 6ae08ae3de ("bpf: Add probe_read_{user, kernel}
and probe_read_{user,kernel}_str helpers").
Given bpf_probe_read{,str}() have been around for ~5 years by now, there
are plenty of users at least on x86 still relying on them today, so we
cannot remove them entirely w/o breaking the BPF tracing ecosystem.
However, their use should be restricted to archs with non-overlapping
address ranges where they are working in their current form. Therefore,
move this behind a CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE and
have x86, arm64, arm select it (other archs supporting it can follow-up
on it as well).
For the remaining archs, they can workaround easily by relying on the
feature probe from bpftool which spills out defines that can be used out
of BPF C code to implement the drop-in replacement for old/new kernels
via: bpftool feature probe macro
Suggested-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
Reviewed-by: Masami Hiramatsu <mhiramat@kernel.org>
Acked-by: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Brendan Gregg <brendan.d.gregg@gmail.com>
Cc: Christoph Hellwig <hch@lst.de>
Link: https://lore.kernel.org/bpf/20200515101118.6508-2-daniel@iogearbox.net
Users can choose which flexcom function to use. Describe the I2C
Flexcom0 function. Add alias for the i2c2 node in order to not rely
on probe order for the i2c device numbering. The sama5d2 SoC has
two dedicated i2c buses and five flexcoms that can function as i2c.
The i2c0 and i2c1 aliases are kept for the dedicated i2c buses,
the i2c flexcom functions can be numbered in order starting from i2c2.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-16-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Indicate which i2c alias is for which connector on the board.
Specify that serial0 is for DBGU. This eases tester's life.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-17-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
The aliases should be defined in the board dts rather than in the
SoC dtsi. Don't rely on the aliases defined in the SoC dtsi and define
the alias for the Serial DBGU in the board dts file. sama5d2 boards use
the "serial0" alias for the Serial DBGU, do the same for sama5d2_xplained.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-15-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Device aliases are board-specific, if needed one should define them
in board dts rather than in the SoC dtsi. If an alias from the SoC
dtsi is addressed by a driver that does not use any of the of_alias*()
methods, we can drop it. This is the case for the i2s aliases, drop
them. tcb aliases point to nodes that are not enabled in any of the
sama5d2 based platforms. atmel_tclib.c is scheduled to go away, any
board using that alias is already broken, so get rid of the tcb aliases
too.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-14-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Spare boards of duplicating the DMA bindings. Describe the flx0
DMA bindings in the SoC dtsi. Users that don't want to use DMA
for their flexcom functions have to overwrite the flexcom DMA
bindings in their board device tree.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-12-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Spare boards of duplicating the DMA bindings. Describe the flx1
DMA bindings in the SoC dtsi. Users that don't want to use DMA
for their flexcom functions have to overwrite the flexcom DMA
bindings in their board device tree.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-11-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Spare boards of duplicating the DMA bindings. Describe the flx3
DMA bindings in the SoC dtsi. Users that don't want to use DMA
for their flexcom functions have to overwrite the flexcom DMA
bindings in their board device tree.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-10-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Spare boards of duplicating the DMA bindings. Describe the flx4
DMA bindings in the SoC dtsi. Users that don't want to use DMA
for their flexcom functions have to overwrite the flexcom DMA
bindings in their board device tree.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-9-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
The UART submodule in Flexcom has 32-byte Transmit and Receive FIFOs.
Tested uart7 on sama5d2-icp, which has both DMA and FIFO enabled.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-8-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
There is a single functional change in this patch. With the move of the
flx0 uart5 definition in the SoC dtsi, the uart5 from
at91-sama5d27_wlsom1_ek.dts inherits the following optional property:
atmel,fifo-size = <32>;
This particular change was tested by Codrin.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-7-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-6-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
The Flexcom IP is part of the sama5d2 SoC. Move the flx2 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-5-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
The Flexcom IP is part of the sama5d2 SoC. Move the flx3 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-4-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-3-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Remove the adi,input-style and adi,input-justification properties of
hdmi@39 to make it compliant with the "adi,adv7511w" DT binding.
Signed-off-by: Ricardo Cañuelo <ricardo.canuelo@collabora.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20200511110611.3142-6-ricardo.canuelo@collabora.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Small fixes to make these DTs compliant with the adi,adv7511w and
adi,adv7513 bindings:
r8a7745-iwg22d-sodimm-dbhd-ca.dts
r8a7790-lager.dts
r8a7790-stout.dts
r8a7791-koelsch.dts
r8a7791-porter.dts
r8a7792-blanche.dts
r8a7793-gose.dts
r8a7794-silk.dts:
Remove the adi,input-style and adi,input-justification properties.
r8a7792-wheat.dts:
Reorder the I2C slave addresses of hdmi@3d and hdmi@39 and remove
the adi,input-style and adi,input-justification properties.
Signed-off-by: Ricardo Cañuelo <ricardo.canuelo@collabora.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20200511110611.3142-3-ricardo.canuelo@collabora.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Alexei Starovoitov says:
====================
pull-request: bpf-next 2020-05-14
The following pull-request contains BPF updates for your *net-next* tree.
The main changes are:
1) Merged tag 'perf-for-bpf-2020-05-06' from tip tree that includes CAP_PERFMON.
2) support for narrow loads in bpf_sock_addr progs and additional
helpers in cg-skb progs, from Andrey.
3) bpf benchmark runner, from Andrii.
4) arm and riscv JIT optimizations, from Luke.
5) bpf iterator infrastructure, from Yonghong.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
POSIX defines faccessat() as having a fourth "flags" argument, while the
linux syscall doesn't have it. Glibc tries to emulate AT_EACCESS and
AT_SYMLINK_NOFOLLOW, but AT_EACCESS emulation is broken.
Add a new faccessat(2) syscall with the added flags argument and implement
both flags.
The value of AT_EACCESS is defined in glibc headers to be the same as
AT_REMOVEDIR. Use this value for the kernel interface as well, together
with the explanatory comment.
Also add AT_EMPTY_PATH support, which is not documented by POSIX, but can
be useful and is trivial to implement.
Signed-off-by: Miklos Szeredi <mszeredi@redhat.com>
The Avenger96 is in fact an assembly of DH Electronics DHCOR SoM on top
of an Avenger96 reference board. The DHCOR SoM can be populated with any
STM32MP15xx. Split the DTs to reflect this such that the common SoM and
Avenger96 parts are now in stm32mp15xx-dhcor-*dtsi and a specific example
implementation of STM32MP157A SoM and Avenger96 board is separated into
stm32mp157a-dhcor-*dts* . The stm32mp157a-avenger96.dts is retained for
the sake of backward naming compatibility.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
The DH Electronics PDK2 can be populated with SoM with any STM32MP15xx
variant. Split the SoC-independent parts of the SoM and PDK2 into the
stm32mp15xx-dhcom-*.dtsi and reduce stm32mp157c-dhcom-*dts* to example
of adding STM32MP157C variant of the SoM into a PDK2 carrier board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Add bindings for the four GPIO LEDs on DH PDK2 board. Note that LED5
GPIO-E may conflict with touchscreen interrupt, hence LED5 must be
disabled when using the DH 560-200 display unit with touchscreen.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Add bindings for the four GPIO keys on DH PDK2 board. Note that TA1
key is polled because it's IRQ line conflicts with ethernet IRQ, the
rest of the GPIO keys, TA2, TA3, TA4, are interrupt-driven and wake
up sources.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
IoT Box is an IoT gateway device based on Stinger96 board powered by
STM32MP1 SoC, designed and manufactured by Shiratech Solutions. This
device makes use of Stinger96 board by having it as a base board with
one additional mezzanine on top.
Following are the features exposed by this device in addition to the
Stinger96 board:
* WiFi/BT
* CCS811 VOC sensor
* 2x Digital microphones IM69D130
* 12x WS2812B LEDs
Following peripherals are tested and known to work:
* WiFi/BT
* CCS811
More information about this device can be found in Shiratech website:
https://www.shiratech-solutions.com/products/iot-box/
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Stinger96 is a 96Boards IoT Extended edition board designed and
manufactured by Shiratech solutions based on STM32MP1 SoC. Following
are the features of this board:
* 256MB DDR
* 125MB NAND Flash
* Onboard BG96 modem
* 1x uSD
* 2x USB (1 available as external connector and another connected to BG96)
* 1x SPI
* 1x PCM
* 2x UART (apart from serial console)
* 2x I2C (apart from one connected to PMIC)
Following peripherals are tested and known to work:
* BG96 modem
* 1x I2C (LS-I2C0)
* 1x SPI
* 1x UART (LS-UART0)
* USB (Only Gadget mode)
* uSD
More information about this board can be found in Shiratech website:
https://www.shiratech-solutions.com/products/stinger96/
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
These pinctrl definitions will be used by Stinger96/IoTBox boards
from Shiratech.
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Few device tree fixes for various devices:
- A regression fix for non-existing can device on am534x-idk
- Fix missing dma-ranges for dra7 pcie
- Fix flakey wlan on droid4 where some devices would not connect
at all because of internal pull being used with an external pull
- Fix occasional missed wake-up events on droid4 modem uart
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAl60Rf8RHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXOX6A/9EswTZAAALWG/e4NsXFQ+qejz0vV7ssnY
wVgqaN9syo8QzADOompSl00KK6OS4+kykanM4LV6WeqLX+IyMHH29C1V2Phi8GxT
A6clVAspS9VsJeR1XC46JxGdR3+wBHKIA3GywPliWqONG8NmEVKQM4SMIRgUqrh4
Ed+GJg5O3ZU9IuamJgetrWh5M2/VCGQTcUsJZvi80aa8sQtf0fFdDb+0v9Ze1Cl6
LQ2SYPcYtwEQspnPMFS2LKYg2M25jcquAhNZFyFepLSmg8qu6db//8gSaBPnZmpO
q1Vp9lkB19zUlkLImoEFp0u62lPuHkdTPfAI/S+kDU8g/KAz8IZfK1oXTW8pyuRi
NB1OthbNXSv7MGmS7bC2/1WOtirNQV6NTlpb/A8GOtYc/pApW11xokw2OqdvbpV/
MuMoH2HiDgcxyDLujXkS+u4dWF20570uWh0GyYNHT3aJzGbhanQnwJp8Fq2zmByE
h3o/zyF9SR2XK6f2YOW96hEPeCU8g95VZnGo9jJfkUVi5qXFhFOs7Yd5KVnN0VeA
irHBm66E0t/xgioCRquAvev83u8gXzPu9eXpebB6/D2wdw7y1SFTpIRnlzKeajws
A/oldWXxkEAMa8UN+g46bkgFpIIjMQo5BjWlXXhbYmAIBdOXLpiYcrUbQ8ecFVkG
DuCV/UwycrM=
=umsu
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v5.6/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/fixes
Fixes for omaps for v5.6-rc cycle
Few device tree fixes for various devices:
- A regression fix for non-existing can device on am534x-idk
- Fix missing dma-ranges for dra7 pcie
- Fix flakey wlan on droid4 where some devices would not connect
at all because of internal pull being used with an external pull
- Fix occasional missed wake-up events on droid4 modem uart
* tag 'omap-for-v5.6/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: omap4-droid4: Fix occasional lost wakeirq for uart1
ARM: dts: omap4-droid4: Fix flakey wlan by disabling internal pull for gpio
ARM: dts: dra7: Fix bus_dma_limit for PCIe
ARM: dts: am574x-idk: Disable m_can node
Link: https://lore.kernel.org/r/pull-1588872844-804667@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
make dtc and the new dtscheck against yaml bindings happy.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAl6yA9QQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgeX0CACEwXPa8ChfXg+N4846D/wcwkpMVQqnTbMR
WrnqVLUNHf71h7Yej/aXpBSgEq5er1Q/HVgbjvkAAYNw633MNWgaNMi9AFl03gTF
uSOSUoiwauUUlvWt2aZ44IHxHS/WC0FB9/wIROpnD0SJvmYX9MJF8AVITNDsTDGv
EsSswwAXiBxILDWWdBM2QgAZxEhan3MwBbHQrmPRePDAWylluT3tMGjEfLgIapcW
9w44tw0kR8g7Zwgq+MYcfyHoNhUXOr1iMlCCA0LWOOtNBJAbXKM4XDp4cWwHLiI3
nktZSWXN7B08dx4hi/++18izC6N/ZwoGycMN4wG9kvdaRnpwh3KN
=vkl2
-----END PGP SIGNATURE-----
Merge tag 'v5.7-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
Some fixes for the newly added Pinebook Pro and other fixes to
make dtc and the new dtscheck against yaml bindings happy.
* tag 'v5.7-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: fix pinctrl sub nodename for spi in rk322x.dtsi
arm64: dts: rockchip: Fix Pinebook Pro FUSB302 interrupt
ARM: dts: rockchip: swap clock-names of gpu nodes
arm64: dts: rockchip: swap interrupts interrupt-names rk3399 gpu node
arm64: dts: rockchip: fix status for &gmac2phy in rk3328-evb.dts
arm64: dts: rockchip: remove extra assigned-clocks property from &gmac2phy node in rk3328-evb.dts
ARM: dts: rockchip: fix phy nodename for rk3229-xms6
ARM: dts: rockchip: fix phy nodename for rk3228-evb
arm64: dts: rockchip: Rename dwc3 device nodes on rk3399 to make dtc happy
arm64: dts: rockchip: drop #address-cells, #size-cells from rk3399 pmugrf node
arm64: dts: rockchip: drop #address-cells, #size-cells from rk3328 grf node
arm64: dts: rockchip: drop non-existent gmac2phy pinmux options from rk3328
arm64: dts: rockchip: Replace RK805 PMIC node name with "pmic" on rk3328 boards
arm64: dts: rockchip: enable DC charger detection pullup on Pinebook Pro
arm64: dts: rockchip: fix inverted headphone detection on Pinebook Pro
arm64: dts: rockchip: Correct PMU compatibles for PX30 and RK3308
Link: https://lore.kernel.org/r/1738941.6LdaBJIBqS@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Fix IOMMU support on R-Car V3H,
- Minor fixes that are fast-tracked to avoid introducing regressions
during conversion of DT bindings to json-schema.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCXqqEEQAKCRCKwlD9ZEnx
cK6VAQDEYT5s4bzgLANPkTuvz3n5NgmS1nSC9tGrUX9co4OEUgD+OkwEnFJgLF1+
LbwisW1fNfCz1looPeyyZTl9Q8o5Yg0=
=cIRT
-----END PGP SIGNATURE-----
Merge tag 'renesas-fixes-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes
Renesas fixes for v5.7
- Fix IOMMU support on R-Car V3H,
- Minor fixes that are fast-tracked to avoid introducing regressions
during conversion of DT bindings to json-schema.
* tag 'renesas-fixes-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
ARM: dts: r7s9210: Remove bogus clock-names from OSTM nodes
arm64: dts: renesas: r8a77980: Fix IPMMU VIP[01] nodes
ARM: dts: r8a73a4: Add missing CMT1 interrupts
Link: https://lore.kernel.org/r/20200430084834.1384-1-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Set correct AHB clock for i.MX8MN SDMA1 device to fix a "Timeout
waiting for CH0" error.
- Fix a linker error for i.MX6 configurations that have ARM_CPU_SUSPEND=n,
which can happen if neither CONFIG_PM, CONFIG_CPU_IDLE, nor ARM_PSCI_FW
are selected.
- Fix I2C1 pinctrl configuration for i.MX27 phytec-phycard board.
- Fix i.MX8M AIPS 'reg' properties to remove DTC simple_bus_reg
warnings.
- Add missing compatible "fsl,vf610-edma" for LS1028A EDMA device, so
that bootloader can fix up the IOMMU entries there. Otherwise, EDMA
just doesn't work on LS1028A with shipped bootloader.
- Fix imx6dl-yapp4-ursa board Ethernet connection.
- Fix input_val for AUDIOMIX_BIT_STREAM pinctrl defines on i.MX8MP
according to Reference Manual.
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAl6pHtIUHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM69sAgAp/H4BASI7SAbrjYsFjCP+ymPVgeS
Y9oeLm09Q2XEF6GiRhK4SDqN56BOUelRI6nqWx3k6sU5A7SuZMqGSaZZEhCtHhjl
iixyxSccxh4prUWSEDQPHyIJ6yjBt+QkKhycOVLwq7FFLdlrSaRuameNQAkjEU4a
YPSL0oBd1xNbz75RaqgmyI0lzOuQg1P+GMQqmVOYfrucK94bq62FMSezyEBQxKU+
0MVG/hEkeLtxFgzE6OpkBs1p1m+KgXE7qvV0W84VyZOKgri1qJ74V1Pl/RJNNVA0
p46c3PH66OATAU7+pbshC0x/hsN8ZVAoBhPit5oLF7ugDNpi377jT/zRrw==
=z3sI
-----END PGP SIGNATURE-----
Merge tag 'imx-fixes-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
i.MX fixes for 5.7:
- Set correct AHB clock for i.MX8MN SDMA1 device to fix a "Timeout
waiting for CH0" error.
- Fix a linker error for i.MX6 configurations that have ARM_CPU_SUSPEND=n,
which can happen if neither CONFIG_PM, CONFIG_CPU_IDLE, nor ARM_PSCI_FW
are selected.
- Fix I2C1 pinctrl configuration for i.MX27 phytec-phycard board.
- Fix i.MX8M AIPS 'reg' properties to remove DTC simple_bus_reg
warnings.
- Add missing compatible "fsl,vf610-edma" for LS1028A EDMA device, so
that bootloader can fix up the IOMMU entries there. Otherwise, EDMA
just doesn't work on LS1028A with shipped bootloader.
- Fix imx6dl-yapp4-ursa board Ethernet connection.
- Fix input_val for AUDIOMIX_BIT_STREAM pinctrl defines on i.MX8MP
according to Reference Manual.
* tag 'imx-fixes-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: freescale: imx8mp: update input_val for AUDIOMIX_BIT_STREAM
arm64: dts: imx8m: Fix AIPS reg properties
arm64: dts: imx8mn: Change SDMA1 ahb clock for imx8mn
ARM: dts: imx27-phytec-phycard-s-rdk: Fix the I2C1 pinctrl entries
ARM: imx: provide v7_cpu_resume() only on ARM_CPU_SUSPEND=y
ARM: dts: imx6dl-yapp4: Fix Ursa board Ethernet connection
arm64: dts: ls1028a: add "fsl,vf610-edma" compatible
dt-bindings: dma: fsl-edma: fix ls1028a-edma compatible
Link: https://lore.kernel.org/r/20200429063226.GT32592@dragon
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
CONFIG_VEXPRESS_CONFIG has 'default y if ARCH_VEXPRESS', so selecting is
unnecessary. Selecting it also prevents setting CONFIG_VEXPRESS_CONFIG
to a module.
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Rob Herring <robh@kernel.org>
The only thing that vexpress-syscfg does is provide a regmap to
vexpress-config bus child devices. There's little reason to have 2
components for this. The current structure with initcall ordering
requirements makes turning these components into modules more difficult.
So let's start to simplify things and merge vexpress-syscfg into
vexpress-config. There's no functional change in this commit and it's
still separate components until subsequent commits.
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Rob Herring <robh@kernel.org>
The GW552x-B board revision adds USB OTG support.
Enable the device-tree node and configure the OTG_ID pin.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Remove all the legacy clk code that supports a non-common clk framework
implementation of 'struct clk' in mach-mmp. This code doesn't look to be
compiled anymore given that the MMP is fully supported in the
multi-platform config via ARCH_MULTIPLATFORM as of commit 377524dc4d
("ARM: mmp: move into ARCH_MULTIPLATFORM"). The ARCH_MULTIPLATFORM
config selects COMMON_CLK and therefore the Makefile rule can never
actually compile the code in these files.
Cc: Lubomir Rintel <lkundrak@v3.sk>
Cc: Russell King <linux@armlinux.org.uk>
Cc: <linux-arm-kernel@lists.infradead.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200409064416.83340-9-sboyd@kernel.org
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
[sboyd@kernel.org: Squash in a clock.h include removal found by Stephen
Rothwell <sfr@canb.auug.org.au>]
Recent PTP-specific cpsw driver changes started exposing an issue on at
at least j5eco-evm:
Unhandled fault: external abort on non-linefetch (0x1008) at 0xf0169004
...
(davinci_mdio_runtime_suspend) from [<c063f2a4>] (__rpm_callback+0x84/0x154)
(__rpm_callback) from [<c063f394>] (rpm_callback+0x20/0x80)
(rpm_callback) from [<c063f4f0>] (rpm_suspend+0xfc/0x6ac)
(rpm_suspend) from [<c0640af0>] (pm_runtime_work+0x88/0xa4)
(pm_runtime_work) from [<c0155338>] (process_one_work+0x228/0x568)
...
Let's fix the issue by using the correct mdio clock as suggested by
Grygorii Strashko <grygorii.strashko@ti.com>.
The DM814_ETHERNET_CPGMAC0_CLKCTRL clock is the interconnect target module
clock and managed by ti-sysc.
Fixes: 6398f3478e ("ARM: dts: Configure interconnect target module for dm814x cpsw")
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
My recent commit b6d49cab44 ("net: Make PTP-specific drivers depend on
PTP_1588_CLOCK") exposes a missing dependency in defconfigs that select
TI_CPTS without selecting PTP_1588_CLOCK, leading to linker errors of the
form:
drivers/net/ethernet/ti/cpsw.o: in function `cpsw_ndo_stop':
cpsw.c:(.text+0x680): undefined reference to `cpts_unregister'
...
That's because TI_CPTS_MOD (which is the symbol gating the _compilation_ of
cpts.c) now depends on PTP_1588_CLOCK, and so is not enabled in these
configurations, but TI_CPTS (which is the symbol gating _calls_ to the cpts
functions) _is_ enabled. So we end up compiling calls to functions that
don't exist, resulting in the linker errors.
This patch fixes build errors and restores previous behavior by:
- ensure PTP_1588_CLOCK=y in TI specific configs and CPTS will be built
- remove TI_CPTS_MOD and, instead, add dependencies from CPTS in
TI_CPSW/TI_KEYSTONE_NETCP/TI_CPSW_SWITCHDEV as below:
config TI_CPSW_SWITCHDEV
...
depends on TI_CPTS || !TI_CPTS
which will ensure proper dependencies PTP_1588_CLOCK -> TI_CPTS ->
TI_CPSW/TI_KEYSTONE_NETCP/TI_CPSW_SWITCHDEV and build type selection.
Note. For NFS boot + CPTS all of above configs have to be built-in.
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Dan Murphy <dmurphy@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Fixes: b6d49cab44 ("net: Make PTP-specific drivers depend on PTP_1588_CLOCK")
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Clay McClure <clay@daemons.net>
[grygorii.strashko@ti.com: rewording, add deps cpsw/netcp from cpts, drop IS_REACHABLE]
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Currently we have architecture-specific fd_inb() and fd_outb() functions
or macros, taking just a port which is in fact made of a base address and
a register. The base address is FDC-specific and derived from the local or
global "fdc" variable through the FD_IOPORT macro used in the base address
calculation.
This change splits this by explicitly passing the FDC's base address and
the register separately to fd_outb() and fd_inb(). It affects the
following archs:
- x86, alpha, mips, powerpc, parisc, arm, m68k:
simple remap of port -> base+reg
- sparc32: use of reg only, since the base address was already masked
out and the FDC controller is known from a static struct.
- sparc64: like x86 for PCI, like sparc32 for 82077
Some archs use inline functions and others macros. This was not
unified in order to minimize the number of changes to review. For the
same reason checkpatch still spews a few warnings about things that
were already there before.
The parisc still uses hard-coded register values and could be cleaned up
by taking the register definitions.
The sparc per-controller inb/outb functions could further be refined
to explicitly take an FDC register instead of a port in argument but it
was not needed yet and may be cleaned later.
Link: https://lore.kernel.org/r/20200331094054.24441-2-w@1wt.eu
Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Matt Turner <mattst88@gmail.com>
Cc: Ian Molton <spyro@f2s.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Helge Deller <deller@gmx.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: x86@kernel.org
Signed-off-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Denis Efremov <efremov@linux.com>
Fix the following sparse warning:
arch/arm/mach-omap2/pm33xx-core.c:270:14: warning: symbol 'am43xx_get_rtc_base_addr' was not declared.
The am43xx_get_rtc_base_addr has only call site within pm33xx-core.c
It should be static
Fixes: 8c5a916f4c ("ARM: OMAP2+: sleep33/43xx: Add RTC-Mode support")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Samuel Zou <zou_wei@huawei.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Fix sparse warning:
arch/arm/mach-omap2/omap-smp.c:75:6: warning: symbol
'omap5_erratum_workaround_801819' was not declared. Should it be static?
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Ma Feng <mafeng.ma@huawei.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Fix sparse warning:
arch/arm/mach-oxnas/platsmp.c:30:12: warning: symbol 'ox820_boot_secondary' was
not declared. Should it be static?
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Ma Feng <mafeng.ma@huawei.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Fixes: af76e806b5 ("ARM: oxnas: Add OX820 SMP support")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/1589247973-29728-1-git-send-email-mafeng.ma@huawei.com
$(AS) is not used anywhere in the kernel build, hence commit
aa824e0c96 ("kbuild: remove AS variable") killed it.
Remove the left-over code in arch/{arm,arm64}/Makefile.
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Reviewed-by: Nathan Chancellor <natechancellor@gmail.com>
Acked-by: Will Deacon <will@kernel.org>
The Clock Pulse Generator (CPG) device node lacks the extal2 clock.
This may lead to a failure registering the "r" clock, or to a wrong
parent for the "usb24s" clock, depending on MD_CK2 pin configuration and
boot loader CPG_USBCKCR register configuration.
This went unnoticed, as this does not affect the single upstream board
configuration, which relies on the first clock input only.
Fixes: d9ffd583bf ("ARM: shmobile: r8a7740: add SoC clocks to DTS")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20200508095918.6061-1-geert+renesas@glider.be
Since commit bcf3440c6d ("net: phy: micrel: add phy-mode support for the
KSZ9031 PHY") the networking is broken on boards:
am437x-gp-evm
am437x-sk-evm
am437x-idk-evm
All above boards have phy-mode = "rgmii" and this is worked before, because
KSZ9031 PHY started with default RGMII internal delays configuration (TX
off, RX on 1.2 ns) and MAC provided TX delay. After above commit, the
KSZ9031 PHY starts handling phy mode properly and disables RX delay, as
result networking is become broken.
Fix it by switching to phy-mode = "rgmii-rxid" to reflect previous
behavior.
Cc: Oleksij Rempel <o.rempel@pengutronix.de>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Philippe Schenker <philippe.schenker@toradex.com>
Fixes: bcf3440c6d ("net: phy: micrel: add phy-mode support for the KSZ9031 PHY")
Reviewed-by: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
<linux/cryptohash.h> sounds very generic and important, like it's the
header to include if you're doing cryptographic hashing in the kernel.
But actually it only includes the library implementation of the SHA-1
compression function (not even the full SHA-1). This should basically
never be used anymore; SHA-1 is no longer considered secure, and there
are much better ways to do cryptographic hashing in the kernel.
Most files that include this header don't actually need it. So in
preparation for removing it, remove all these unneeded includes of it.
Signed-off-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Before commit 874f9c7da9 ("printk: create pr_<level> functions"),
pr_*() calls without a trailing newline characters would be printed with
a newline character appended, both on the console and in the output of
the dmesg command.
After that commit, no new line character is appended, and the output of
the next pr_*() call of the same type may be appended:
-No ATAGs?
-hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
+No ATAGs?hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
While this commit has been reverted in commit a0cba2179e ("Revert
"printk: create pr_<level> functions""), it's still good practice to
terminate kernel messages with newlines.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Since commit bcf3440c6d ("net: phy: micrel: add phy-mode support for the
KSZ9031 PHY") the networking is broken on boards:
am571x-idk
am572x-idk
am574x-idk
am57xx-beagle-x15
All above boards have phy-mode = "rgmii" and this is worked before because
KSZ9031 PHY started with default RGMII internal delays configuration (TX
off, RX on 1.2 ns) and MAC provided TX delay. After above commit, the
KSZ9031 PHY starts handling phy mode properly and disables RX delay, as
result networking is become broken.
Fix it by switching to phy-mode = "rgmii-rxid" to reflect previous
behavior.
Cc: Oleksij Rempel <o.rempel@pengutronix.de>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Philippe Schenker <philippe.schenker@toradex.com>
Fixes: bcf3440c6d ("net: phy: micrel: add phy-mode support for the KSZ9031 PHY")
Reviewed-by: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Support for TI AM43x SoCs depends on ARCH_MULTI_V7, which selects
ARCH_MULTI_V6_V7.
As the latter selects MIGHT_HAVE_CACHE_L2X0, there is no need for
SOC_AM43XX to select MIGHT_HAVE_CACHE_L2X0.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Tony Lindgren <tony@atomide.com>
Cc: linux-omap@vger.kernel.org
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add SPI2 bindings to AV96 DT, the SPI2 IOs are present on
low-speed expansion connector X6. This is disabled by default
and can be enabled if something is connected there.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Add another mux option for SPI2 pins, this is used on AV96 board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Add another mux option for ADC pins, this is used on AV96 board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Add FDCAN2 bindings to AV96 DT, the FDCAN2 is present on low-speed
expansion connector X6. This is disabled by default to match the
96boards specification though.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Add another mux option for FDCAN2 pins, this is used on AV96 board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Add FDCAN1 bindings to AV96 DT, the FDCAN1 is present on low-speed
expansion connector X6. This is disabled by default to match the
96boards specification though.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Add another mux option for FDCAN1 pins, this is used on AV96 board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
The I2C2 uses different pinmux on AV96, use correct pinmux and
also add comments about the I2C being present on the "low-speed"
expansion connector X6.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Add another mux option for I2C2 pins, this is used on AV96 board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Declare PSCI v1.0 support instead of v0.1 as the former is supported
by the PSCI firmware stacks stm32mp15x relies on.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Stephen reported the following build warning on a ARM multi_v7_defconfig
build with GCC 9.2.1:
kernel/futex.c: In function 'do_futex':
kernel/futex.c:1676:17: warning: 'oldval' may be used uninitialized in this function [-Wmaybe-uninitialized]
1676 | return oldval == cmparg;
| ~~~~~~~^~~~~~~~~
kernel/futex.c:1652:6: note: 'oldval' was declared here
1652 | int oldval, ret;
| ^~~~~~
introduced by commit a08971e948 ("futex: arch_futex_atomic_op_inuser()
calling conventions change").
While that change should not make any difference it confuses GCC which
fails to work out that oldval is not referenced when the return value is
not zero.
GCC fails to properly analyze arch_futex_atomic_op_inuser(). It's not the
early return, the issue is with the assembly macros. GCC fails to detect
that those either set 'ret' to 0 and set oldval or set 'ret' to -EFAULT
which makes oldval uninteresting. The store to the callsite supplied oldval
pointer is conditional on ret == 0.
The straight forward way to solve this is to make the store unconditional.
Aside of addressing the build warning this makes sense anyway because it
removes the conditional from the fastpath. In the error case the stored
value is uninteresting and the extra store does not matter at all.
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/87pncao2ph.fsf@nanos.tec.linutronix.de
We would be trying to print the kernel virtual address of the base
register address which is not very useful and is not displayed by
default because of pointer restriction. Print the Device Tree node name
instead which is what was originally intended.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Pull crypto fixes from Herbert Xu:
"This fixes a potential scheduling latency problem for the algorithms
used by WireGuard"
* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6:
crypto: arch/nhpoly1305 - process in explicit 4k chunks
crypto: arch/lib - limit simd usage to 4k chunks
Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on beaver.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Set min/max voltage and couple CPU/CORE regulators.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The tegra20-cpufreq now instantiates cpufreq-dt and Tegra30 is fully
supported by that driver.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
PLLX may be kept disabled if cpufreq driver selects some other clock for
CPU. In that case PLLX will be disabled later in the resume path by the
CLK driver, which also can enable PLLX if necessary by itself. Thus there
is no need to enable PLLX early during resume. Tegra114/124 CLK drivers do
not manage PLLX on resume and thus they are left untouched by this patch.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The early-resume code shall not switch CPU to PLLX because PLLX
configuration could be unstable or PLLX should be simply disabled if
CPU enters into suspend running off some other PLL (the case if CPUFREQ
driver is active). The actual burst policy is restored by the clock
drivers.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The PL310 Auxiliary Control Register shouldn't have the "Full line of
zero" optimization bit being set before L2 cache is enabled. The L2X0
driver takes care of enabling the optimization by itself.
This patch fixes a noisy error message on Tegra20 and Tegra30 telling
that cache optimization is erroneously enabled without enabling it for
the CPU:
L2C-310: enabling full line of zeros but not enabled in Cortex-A9
Cc: <stable@vger.kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
ASUS TF300T device may not work properly if firmware is asked to fully
re-initialize L2 cache after resume from LP2 suspend. The downstream
kernel of TF300T uses different opcode to enable cache after resuming
from LP2, this opcode also works fine on Nexus 7 and Ouya devices.
Supposedly, this may be needed by an older firmware versions.
Reported-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Tested-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Downstream kernel of ASUS TF300T sets r0 to #3. There is no explanation in
downstream code whether this is really needed and some of T30 downstream
kernels have and explicit comment telling that all arguments are ignored
by firmware. Let's take a safe side by replicating behavior of the TF300T
downstream kernel. This change works fine on Ouya and Nexus 7 devices.
Tested-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enable build testing and configuration control of the common clk
framework so that more code coverage and testing can be done on the
common clk framework across various architectures. This also nicely
removes the requirement that architectures must select the framework
when they don't use it in architecture code.
There's one snag with doing this, and that's making sure that randconfig
builds don't select this option when some architecture or platform
implements 'struct clk' outside of the common clk framework. Introduce a
new config option 'HAVE_LEGACY_CLK' to indicate those platforms that
haven't migrated to the common clk framework and therefore shouldn't be
allowed to select this new config option. Also add a note that we hope
one day to remove this config entirely.
Based on a patch by Mark Brown <broonie@kernel.org>.
Cc: Mark Brown <broonie@kernel.org>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Mark Salter <msalter@redhat.com>
Cc: Aurelien Jacquiot <jacquiot.aurelien@gmail.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Guan Xuetao <gxt@pku.edu.cn>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: Rich Felker <dalias@libc.org>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: <linux-mips@vger.kernel.org>
Cc: <linux-c6x-dev@linux-c6x.org>
Cc: <linux-m68k@lists.linux-m68k.org>
Cc: <linux-arm-kernel@lists.infradead.org>
Cc: <linux-sh@vger.kernel.org>
Link: https://lore.kernel.org/r/1470915049-15249-1-git-send-email-broonie@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200409064416.83340-8-sboyd@kernel.org
Reviewed-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Lubomir Rintel