The current SPCR code does not check the access width of the MMIO, and
uses a default of 8bit register accesses. This prevents devices that
only do 16 or 32bit register accesses from working. By simply checking
this field and setting the MMIO string appropriately, this issue can be
corrected. To prevent any legacy issues, the code will default to 8bit
accesses if the value is anything but 16 or 32.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Loc Ho <lho@apm.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
ACPICA commit 08b83591c0db751769d61fa889f4f50f575aeffb
PinGroupConfig() is analogous to PinGroupFunction() but instead of mode
(muxing), it is used to apply specific fine-grained configuration to a
set of referenced pins.
The format of this new resource is:
PinGroupConfig (Shared/Exclusive, PinConfigType, PinConfigValue,
ResourceSource, ResourceSourceIndex, ResourceSourceLabel,
ResourceUsage, DescriptorName, VendorData)
The PinConfigType/PinConfigValue are the same used by PinConfig()
resource.
Here also the combination of ResourceSource and ResourceSourceLabel is
used to specify the PinGroup() this resource refers to.
Link: https://github.com/acpica/acpica/commit/08b83591
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Lv Zheng <lv.zheng@intel.com>
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
ACPICA commit bd9a745749eac7137cd23085e6bdeb322de14ea2
PinGroupFunction() is a new resource introduced with ACPI 6.2. It is
used with PinGroup() to configure specific mode for a set of pins
exposed by a GPIO controller.
The format of the resource is:
PinGroupFunction (Shared/Exclusive, FunctionNumber, ResourceSource,
ResourceSourceIndex, ResourceSourceLabel,
ResourceUsage, DescriptorName, VendorData)
The resource_source and ResourceSourceLabel fields are used to specify
the PinGroup() resource referenced by PinGroupFunction().
Device (GPIO)
{
Name (_CRS, ResourceTemplate () {
PinGroup ("group1") {2, 3}
PinGroup ("group2") {4, 5}
...
})
}
Device (I2C)
{
Name (_CRS, ResourceTemplate () {
PinGroupFunction (Exclusive, 6, "^GPIO", 0, "mygroup2")
})
}
In the above example the PinGroupFunction() references the second
PinGroup() resource (using label "mygroup2" and configures pins 4 and 5
into mode 6.
Link: https://github.com/acpica/acpica/commit/bd9a7457
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Lv Zheng <lv.zheng@intel.com>
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
ACPICA commit 7d928e3174fb19d7dc0066b03c30bea07c001563
ACPI 6.2 introduced a new resource that is used to declare set of pins
belonging to a GPIO controller. This resource is referenced by new
PinGroupFunction() and PinGroupConfig() resources using ResourceSource
and ResourceLabel fields.
The PinGroup() resource looks like this:
PinGroup (ResourceLabel, ResourceUsage, DescriptorName,
VendorData) {Pin List}
This resource should be listed in _CRS under the GPIO/pincontroller
device providing these pins.
Link: https://github.com/acpica/acpica/commit/7d928e31
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Lv Zheng <lv.zheng@intel.com>
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
ACPICA commit a06fdba686cefccd5dd5b93b52fa0f1e3f984906
ACPI 6.2 introduced a new resource that is used to specify fine-grained
configuration of a pin or set of pins used by a device. The ASL syntax of
this new resource looks like:
PinConfig (Shared/Exclusive, PinConfigType, PinConfigValue,
ResourceSource, ResourceSourceIndex, ResourceUsage,
DescriptorName, Vendordata) {Pin List}
PinConfigType is an integer with following accepted values:
0x00 (Default) - No configuration is applied to the pin
0x01 (Bias Pull-up) - Pin is pulled up using certain size resistor
0x02 (Bias Pull-down) - Pin is pulled down using certain size resistor
0x03 (Bias Default) - Set to default biasing
0x04 (Bias Disable) - All bias settings will be disabled
0x05 (Bias High Impedance) - Configure the pin as hi_z
0x06 (Bias Bus Hold) - Configure the pin in a weak latch state where
it drives the last value on a tristate bus
0x07 (Drive Open Drain) - Configure the pin into open drain state
0x08 (Drive Open Source) - Configure the pin into open source state
0x09 (Drive Push Pull) - Configure the pin into push-pull state
0x0a (Drive Strength) - How much the pin can supply current
0x0b (Slew Rate) - Configure slew rate of the pin
0x0c (Input Debounce) - Enable input debouncer for the pin
0x0d (Input Schmitt Trigger) - Enable schmitt trigger for the pin
0x0e - 0x7f - Reserved
0x80 - 0xff - Vendor defined types
The PinConfigValue depends on the type and is expressed as units
suitable for that type (for example bias uses Ohms).
Link: https://github.com/acpica/acpica/commit/a06fdba6
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Lv Zheng <lv.zheng@intel.com>
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
ACPICA commit 6bbc6357f7061f1243601adde0ea45f7a89274e0
ACPI 6.2 introduced a new resource that is used to describe how certain
pins are muxed for a device. The ASL syntax of this new resource looks
like below:
PinFunction(Shared, PinConfig, FunctionNumber, ResourceSource,
ResourceSourceIndex, ResourceUsage, DescriptorName,
VendorData) {Pin List}
Which is pretty similar to GpioIo()/GpioInt() resources.
Teach ACPICA about this new resource.
Link: https://github.com/acpica/acpica/commit/6bbc6357
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Lv Zheng <lv.zheng@intel.com>
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
ACPICA commit 16577e5265923f4999b4d2c0addb2343b18135e1
Affects all files.
Link: https://github.com/acpica/acpica/commit/16577e52
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Lv Zheng <lv.zheng@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
ACPICA commit 5a0555ece4ba9917e5842b21d88469ae06b4e815
Adds full support for:
i2c_serial_bus_v2
spi_serial_bus_v2
uart_serial_bus_v2
Compiler, Disassembler, Resource Manager, acpi_help.
Link: https://github.com/acpica/acpica/commit/5a0555ec
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Lv Zheng <lv.zheng@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
All tool/utility signons.
Dual-license module header.
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Lv Zheng <lv.zheng@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
ACPICA commit 8990e73ab2aa15d6a0068b860ab54feff25bee36
Link: https://github.com/acpica/acpica/commit/8990e73a
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Lv Zheng <lv.zheng@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
struct acpi_resource_address and struct acpi_resource_extended_address64 share substracts
just at different offsets. To unify the parsing functions, OSPMs like Linux
need a new ACPI_ADDRESS64_ATTRIBUTE as their substructs, so they can
extract the shared data.
This patch also synchronizes the structure changes to the Linux kernel.
The usages are searched by matching the following keywords:
1. acpi_resource_address
2. acpi_resource_extended_address
3. ACPI_RESOURCE_TYPE_ADDRESS
4. ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS
And we found and fixed the usages in the following files:
arch/ia64/kernel/acpi-ext.c
arch/ia64/pci/pci.c
arch/x86/pci/acpi.c
arch/x86/pci/mmconfig-shared.c
drivers/xen/xen-acpi-memhotplug.c
drivers/acpi/acpi_memhotplug.c
drivers/acpi/pci_root.c
drivers/acpi/resource.c
drivers/char/hpet.c
drivers/pnp/pnpacpi/rsparser.c
drivers/hv/vmbus_drv.c
Build tests are passed with defconfig/allnoconfig/allyesconfig and
defconfig+CONFIG_ACPI=n.
Original-by: Thomas Gleixner <tglx@linutronix.de>
Original-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Lv Zheng <lv.zheng@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This reverts commit aae576e5faefa8ba70647efa320d4747b6375f1e.
Push and Pop are not portable "enough", and caused problems for
some ACPICA customers.
Signed-off-by: Robert Moore <Robert.Moore@intel.com>
Signed-off-by: Lv Zheng <lv.zheng@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Use push and pop to both guarantee that the correct alignment is used,
and to restore the alignment to whatever it was before the header
was included.
It is reported that the #pragma pack(push/pop) directives are not supported
by the specific GCCs, but this patch still doesn't affect kernel build
as there are already #pragma pack([1]) directives used in the old ACPICA
headers, which means there shouldn't be GCCs that are currently used to
compile the ACPI kernels do not support #pragma pack() directives.
References: https://bugs.acpica.org/show_bug.cgi?id=1058
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Lv Zheng <lv.zheng@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Update ACPICA copyrights to 2014. Includes all source headers and
signons for the various tools.
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Lv Zheng <lv.zheng@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Includes all source headers and signons for the various tools.
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Lv Zheng <lv.zheng@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
These two bits are merged at the external interface level for the
IRQ, Interrupt, and GpioInt resource descriptors. However, these
bits are logically independent and there is no need to keep them
merged internally. Therefore, this change splits the bits into
"sharable" and "wake capable" fields within the resource manager.
This simplifies drive code that needs to examine these bits.
Aaron Lu, Bob Moore.
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Lv Zheng <lv.zheng@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cleanup the ACPI_NEXT_RESOURCE macro. Update AcpiWalkResources
to use ACPI_NEXT_RESOURCE. Lv Zheng.
Signed-off-by: Lv Zheng <lv.zheng@intel.com>
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Fixes issues like this:
i_aSL -> iASL
00-7_f -> 00-7F
local_fADT -> local_FADT
execute_oSI -> execute_OSI
Also, in function headers, the parameters are now translated to
lower case (with underscores if necessary.)
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
FixedDMA, GPIO descriptors, SerialBus descriptors
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
This type was introduced as the code was migrated from ACPI 1.0
(with 32-bit AML integers) to ACPI 2.0 (with 64-bit integers). It
is now obsolete and this change removes it from the ACPICA code
base, replaced by u64. The original typedef has been retained
for now for compatibility with existing device driver code.
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Add 2010 copyright to all module headers and signons, including
the Linux header. This affects virtually every file in the ACPICA
core subsystem, iASL compiler, and all utilities.
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
acpi.h now includes only the "public" acpica headers. All other
acpica headers are "private" and should not be included by acpica
users. One new file, accommon.h is used to include the commonly
used private headers for acpica code generation. Future plans
are to move all private headers to a new subdirectory.
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Rafael J. Wysocki