This patch introduces a new C state which allows MPU to go to WFI but keeps
the core domain active. This offers a much better wakeup latency (3us vs
10s of us for the current C1) at the cost of a higher power consumption.
Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Previously omap3_idle_init() was called in device_init, while
omap_pm_init() is called at late_initcall. This causes the cpu idle
driver to call omap_sram_idle before it is properly initialized. This
patch fixes the issue by moving omap3_idle_init into omap3_pm_init.
Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Use the activity check for states C2 and C3 as well. This is
primarily to prevent deeper states during UART activity.
Also, if a different state is chosen than the target state, update the
'last_state' accordingly so that CPUidle state accounting is coorect.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch adds support and enables state C4(MPU RET + CORE RET)
and MPU OFF states (C3 and C5.)
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Basic CPUidle driver for OMAP3 with deepest sleep state supported
being MPU CSWR.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Due to an OMAP3 errata (1.142), on HS/EMU devices SDRC should be
programed to issue automatic self refresh on timeout
of AUTO_CNT = 1 prior to any transition to OFF mode.
This is needed only on sil rev's ES3.0 and above.
This patch enables the above needed WA in the SDRC power register
value stored in scratchpad, so that ROM code restores this value
in SDRC POWER on the wakeup path.
The original SDRC POWER register value is stored and restored back
in omap_sram_idle() function.
This fixes some random crashes observed while stressing suspend
on HS/EMU devices.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
OMAP 3430 ES3.1 chips have a separate bit for IO daisy-chain
wake up enabling. It needs to be enabled when entering
retention or off state, otherwise waking up might not work
in all situations.
Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
MPU and CORE should stay awake if there is CAM domain ACTIVE. This is
because that module doesn't have wake-up capability.
This should replace the patch that is currently in the PM branch.
Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
OMAP3 can't generate wakeups in this state, thus it is not permitted.
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Using debugfs, export a configurable wakeup timer to be used to
wakeup system from suspend.
If a non-zero value is written to
/debug/pm_debug/wakeup_timer_seconds, A timer wakeup event will wake
the system and resume after the configured number of seconds.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Allow enable/disable of low-power states during idle. To
enable low-power idle:
echo 1 > /debug/pm_debug/sleep_while_idle
to disable:
echo 0 > /debug/pm_debug/sleep_while_idle
Also allow enable/disable of OFF-mode. To enable:
echo 1 > /debug/pm_debug/enable_off_mode
to disable:
echo 0 > /debug/pm_debug/enable_off_mode
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch improves the wakeup SRAM code polling the SDRC to become ready
instead of just waiting for a fixed amount of time.
Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The hardware SAVEANDRESTORE mechanism seems to leave
USB HOST power domain permanently into active state
after one transition from off to active state.
Disabling for now.
Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Errata: ES3.0, ES3.1 SDRC not sending auto-refresh when OMAP wakes-up
from OFF mode
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The reboot mode can be communicated to a bootloader (or the
kernel itself) with a scratchpad register. This functionality
is especially useful, if userspace is allowed to change
the reboot mode.
Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Clear DMA channel states so that users can assume a known initial
state.
Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The CM_CLKEN_PLL register saved in scratchpad memory
was wrongly using offset of 0x0004 instead of 0x0000.
The effect of this was that boot ROM code would
restore the wrong value when waking up from off mode.
This wrong value, however, will be overwritten by
prcm context restore. Still, a short period of wrong
clock settings in CM_CLKEN_PLL remained between ROM
code and prcm context restore. This is fixed by the
patch.
Problem reported by: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The SMS_SYSCONFIG register gets reset in off mode, added a
save/restore mechanism for that.
Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The secure sram context save uses dma channels 0 and 1.
In order to avoid collision between kernel DMA transfers and
ROM code dma transfers, we need to reserve DMA channels 0
1 on high security devices.
A bug in ROM code leaves dma irq status bits uncleared.
Hence those irq status bits need to be cleared when restoring
DMA context after off mode.
There was also a faulty parameter given to PPA in the secure
ram context save assembly code, which caused interrupts to
be enabled during secure ram context save. This caused the
save to fail sometimes, which resulted the saved context
to be corrupted, but also left DMA channels in secure mode.
The secure mode DMA channels caused "DMA secure error with
device 0" errors to be displayed.
Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
CM_CLKSEL1_PLL_IVA2 is not saved/restored currently. This patch is
adding save and restore for it.
Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Fix for ES3.0 bug: SDRC not sending auto-refresh when OMAP wakes-up
from OFF mode (warning for HS devices.)
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The function omap3_save_secure_ram() is now called only once during
the initialization of the device and consequent sleep cycles will
re-use the same saved contents for secure RAM. Users who need secure
services should do secure RAM saving before entering off-mode, if a
secure service has been accessed after last save.
There are both latency and reliability issues with saving secure RAM
context in the idle path. The context save uses a hardware resource
which takes an order of hundreds of milliseconds to initialize after a
wake up from off-mode, and also there is no way of checking whether it
is ready from kernel side or not. It just crashes if you use it too
quickly
Additional fix to ensure scratchpad save is done after secure
RAM by Roger Quadros.
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Roger Quadros <ext-roger.quadros@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
For HS/EMU devices, some additional resources need to be
saved/restored for off-mode support. Namely, saving the secure RAM
and a pointer to it in the scratchpad.
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
For HS/EMU devices, these additional features are also used:
- DMA interrupt disable routine added
- Added DMA controller reset to DMA context restore
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Add context save and restore for CORE powerdomain resources in order
to support off-mode.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Adds a 'save_state' option when calling into SRAM idle function
and adds some minor cleanups of SRAM asm code.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
During the MMU restoration on the restore path from MPU OFF, the page
table entry for the page consisting of the code being executed is
modified to make MMU return VA=PA.
The MMU is then enabled and the original entry is being stored in
scratchpad. This patch reads the original values stored in
scratchpad, and restores them back.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Expand the powerdomains handled in the idle path to include PER, NEON
and CORE. This includes properly clearing the previous powerstates,
linking NEON state to MPU state and calling the UART prepare functions
for only the appropraite powerdomain transitions (CORE for UART1,2,
PER for UART3.)
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Generalize the copy of SRAM functions into omap_push_sram_idle()
so it can be used on init but also after off-mode transitions.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Add context save and restore for the System Control Module to suport
off-mode.
ETK and debobs definitions added by Peter De Schrijver.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch populates the scratchpad contents as expected by the
bootROM code.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Add context save and restore for PRCM module to support off-mode.
Additional registers (CM_CLKSEL4, CM_CLKEN, CM_CLKEN2) added by Tero
Kristo.
Missing CM_CLKEN_PLL_IVA2 register added by Kalle Jokiniemi.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Add context save and restore for the INTC module to support off-mode.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Add context save and restore to enable off-mode.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch adds the context save and restore functions for GPMC to
enable off-mode.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* 'for-linus' of git://github.com/at91linux/linux-2.6-at91:
at91: at91sam9g45 family: identify several chip versions
avr32: add two new at91 to cpu.h definition
cpu_is_xxx() macros are identifying generic at91sam9g45 chip. This patch adds
the capacity to differentiate Engineering Samples and final lots through the
inclusion of at91_cpu_fully_identify() and the related chip IDs with chip
version field preserved.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
Somme common drivers will need those at91 cpu_is_xxx() definitions. As
at91sam9g10 and at91sam9g45 are on the way to linus' tree, here is the patch
that adds those chips to cpu.h in AVR32 architecture.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (38 commits)
MIPS: O32: Fix ppoll
MIPS: Oprofile: Rename cpu_type from godson2 to loongson2
MIPS: Alchemy: Fix hang with high-frequency edge interrupts
MIPS: TXx9: Fix spi-baseclk value
MIPS: bcm63xx: Set the correct BCM3302 CPU name
MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_store
MIPS: Avoid potential hazard on Context register
MIPS: Octeon: Use lockless interrupt controller operations when possible.
MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinity
MIPS: Set S-cache linesize to 64-bytes for MTI's S-cache
MIPS: SMTC: Avoid queing multiple reschedule IPIs
MIPS: GCMP: Avoid accessing registers when they are not present
MIPS: GIC: Random fixes and enhancements.
MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_start
MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands
MIPS: SPRAM: Clean up support code a little
MIPS: 1004K: Enable SPRAM support.
MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4
MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT.
MIPS: MTI: Fix accesses to device registers on MIPS boards
...
* 'fixes-s3c-2632-rc5' of git://git.fluff.org/bjdooks/linux:
ARM: S3C2410: Fix sparse warnings in arch/arm/mach-s3c2410/gpio.c
ARM: S3C2440: mini2440: Fix spare warnings
ARM: S3C24XX: Fix warnings in arch/arm/plat-s3c24xx/gpio.c
ARM: S3C2440: mini2440: Fix missing CONFIG_S3C_DEV_USB_HOST
ARM: S3C24XX: arch/arm/plat-s3c24xx: Move dereference after NULL test
ARM: S3C: Fix adc function exports
ARM: S3C2410: Fix link if CONFIG_S3C2410_IOTIMING is not set
ARM: S3C24XX: Introduce S3C2442B CPU
ARM: S3C24XX: Define a macro to avoid compilation error
ARM: S3C: Add info for supporting circular DMA buffers
ARM: S3C64XX: Set rate of crystal mux
ARM: S3C64XX: Fix S3C64XX_CLKDIV0_ARM_MASK value
* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6:
Revert "[IA64] fix percpu warnings"
[IA64] fix percpu warnings
[IA64] SMT friendly version of spin_unlock_wait()
[IA64] use printk_once() unaligned.c/io_common.c
[IA64] Require SAL 3.2 in order to do extended config space ops
[IA64] unsigned cannot be less than 0 in sn_hwperf_ioctl()
[IA64] Restore registers in the stack on INIT
[IA64] Re-implement spinaphores using ticket lock concepts
[IA64] Squeeze ticket locks back into 4 bytes.
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm:
ARM: ensure initial page tables are setup for SMP systems
ARM: 5776/1: Check compiler version and EABI support when adding ARM unwind support.
ARM: 5774/1: Fix Realview ARM1176PB board reboot
ARM: Fix errata 411920 workarounds
ARM: Fix sparsemem with SPARSEMEM_EXTREME enabled
ARM: Use GFP_DMA only for masks _less_ than 32-bit
ARM: integrator: allow Integrator to be built with highmem
ARM: Fix signal restart issues with NX and OABI compat
* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
x86: Make EFI RTC function depend on 32bit again
x86-64: Fix register leak in 32-bit syscall audting
x86: crash_dump: Fix non-pae kdump kernel memory accesses
x86: Side-step lguest problem by only building cmpxchg8b_emu for pre-Pentium
x86: Remove STACKPROTECTOR_ALL
This reverts commit b94b08081f.
genksyms currently cannot handle complicated types for exported
percpu variables. Drop this patch for now as it prevents a
module from being loaded on sn2 systems:
xpc: no symbol version for per_cpu____sn_cnodeid_to_nasid
xpc: Unknown symbol per_cpu____sn_cnodeid_to_nasid
Signed-off-by: Tony Luck <tony.luck@intel.com>
Mapping the same memory using two different attributes (memory
type, shareability, cacheability) is unpredictable. During boot,
we encounter a situation when we're updating the kernel's page
tables which can lead to dirty cache lines existing in the cache
which are subsequently missed. This causes stack corruption,
and therefore a crash.
Therefore, ensure that the shared and cacheability settings
matches the configuration that will be used later; this together
with the restriction in early_cachepolicy() ensures that we won't
create a mismatch during boot.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM unwind is known to compile only with EABI and not-buggy compilers.
The problem is not the unwinding information but the -fno-frame-pointer
option added as a result of !CONFIG_FRAME_POINTER. Now we check the
compiler and raise a #warning in case of wrong compiler.
Signed-off-by: Claudio Scordino <claudio@evidence.eu.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Peter 'p2' De Schrijver