Commit Graph

23 Commits

Author SHA1 Message Date
Paul Mundt 65d517eb72 sh64: asm/pgtable.h needs asm/mmu.h
Needed to satisfy the __in_29bit_mode() check.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-05-31 14:37:44 +09:00
Paul Mundt 8f82f0c702 sh: Fix up breakage from asm-generic/pgtable.h changes.
We require a forward declaration for mm_struct:

In file included from arch/sh/include/asm/pgtable.h:163,
                 from arch/sh/include/asm/io.h:21,
                 from arch/sh/kernel/machvec.c:20:
include/asm-generic/pgtable.h:104: error: 'struct mm_struct' declared inside parameter list
include/asm-generic/pgtable.h: In function 'ptep_get_and_clear_full':
include/asm-generic/pgtable.h:107: error: passing argument 1 of 'ptep_get_and_clear' from incompatible pointer type
include/asm-generic/pgtable.h:70: note: expected 'struct mm_struct *' but argument is of type 'struct mm_struct *'

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-01-14 15:46:50 +09:00
Paul Mundt ccedb20c68 sh: Simplify phys_addr_mask()/PTE_PHYS_MASK for 29/32-bit.
Given that __in_29bit_mode() is a constant for the non-PMB case, we can
simply use the PMB-facing version of phys_addr_mask() and drop the other
variants.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-11-04 12:51:08 +09:00
Paul Mundt a16382ce1c sh64: _PAGE_SPECIAL support.
Now that sh64 has grown extended page flag support we finally have a free
bit for _PAGE_SPECIAL. Wire it up.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-10-27 16:40:19 +09:00
Linus Torvalds ac0f6f927d Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (100 commits)
  ARM: Eliminate decompressor -Dstatic= PIC hack
  ARM: 5958/1: ARM: U300: fix inverted clk round rate
  ARM: 5956/1: misplaced parentheses
  ARM: 5955/1: ep93xx: move timer defines into core.c and document
  ARM: 5954/1: ep93xx: move gpio interrupt support to gpio.c
  ARM: 5953/1: ep93xx: fix broken build of clock.c
  ARM: 5952/1: ARM: MM: Add ARM_L1_CACHE_SHIFT_6 for handle inside each ARCH Kconfig
  ARM: 5949/1: NUC900 add gpio virtual memory map
  ARM: 5948/1: Enable timer0 to time4 clock support for nuc910
  ARM: 5940/2: ARM: MMCI: remove custom DBG macro and printk
  ARM: make_coherent(): fix problems with highpte, part 2
  MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself
  ARM: 5945/1: ep93xx: include correct irq.h in core.c
  ARM: 5933/1: amba-pl011: support hardware flow control
  ARM: 5930/1: Add PKMAP area description to memory.txt.
  ARM: 5929/1: Add checks to detect overlap of memory regions.
  ARM: 5928/1: Change type of VMALLOC_END to unsigned long.
  ARM: 5927/1: Make delimiters of DMA area globally visibly.
  ARM: 5926/1: Add "Virtual kernel memory..." printout.
  ARM: 5920/1: OMAP4: Enable L2 Cache
  ...

Fix up trivial conflict in arch/arm/mach-mx25/clock.c
2010-03-01 09:15:15 -08:00
Russell King 4b3073e1c5 MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself
On VIVT ARM, when we have multiple shared mappings of the same file
in the same MM, we need to ensure that we have coherency across all
copies.  We do this via make_coherent() by making the pages
uncacheable.

This used to work fine, until we allowed highmem with highpte - we
now have a page table which is mapped as required, and is not available
for modification via update_mmu_cache().

Ralf Beache suggested getting rid of the PTE value passed to
update_mmu_cache():

  On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables
  to construct a pointer to the pte again.  Passing a pte_t * is much
  more elegant.  Maybe we might even replace the pte argument with the
  pte_t?

Ben Herrenschmidt would also like the pte pointer for PowerPC:

  Passing the ptep in there is exactly what I want.  I want that
  -instead- of the PTE value, because I have issue on some ppc cases,
  for I$/D$ coherency, where set_pte_at() may decide to mask out the
  _PAGE_EXEC.

So, pass in the mapped page table pointer into update_mmu_cache(), and
remove the PTE value, updating all implementations and call sites to
suit.

Includes a fix from Stephen Rothwell:

  sparc: fix fallout from update_mmu_cache API change

  Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>

Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-02-20 16:41:46 +00:00
Paul Mundt e44d6c4010 sh: Rename split-level pgtable headers.
These were originally named _nopmd and _pmd to follow their asm-generic
counterparts, but we rename them to -2level and -3level for general
consistency.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-01-13 19:18:39 +09:00
Paul Mundt 782bb5a532 sh: default to extended TLB support.
All SH-X2 and SH-X3 parts support an extended TLB mode, which has been
left as experimental since support was originally merged. Now that it's
had some time to stabilize and get some exposure to various platforms,
we can drop it as an option and default enable it across the board.

This is also good future proofing for newer parts that will drop support
for the legacy TLB mode completely.

This will also force 3-level page tables for all newer parts, which is
necessary both for the varying page sizes and larger memories.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-01-13 19:11:14 +09:00
Matt Fleming 2a5eacca85 sh: Move page table allocation out of line
We also switched away from quicklists and instead moved to slab
caches. After benchmarking both implementations the difference is
negligible. The slab caches suit us better though because the size of a
pgd table is just 4 entries when we're using a 3-level page table layout
and quicklists always deal with pages.

Signed-off-by: Matt Fleming <matt@console-pimps.org>
2010-01-02 01:02:25 +00:00
Matt Fleming 5d9b4b19f1 sh: Definitions for 3-level page table layout
If using 64-bit PTEs and 4K pages then each page table has 512 entries
(as opposed to 1024 entries with 32-bit PTEs). Unlike MIPS, SH follows
the convention that all structures in the page table (pgd_t, pmd_t,
pgprot_t, etc) must be the same size. Therefore, 64-bit PTEs require
64-bit PGD entries, etc. Using 2-levels of page tables and 64-bit PTEs
it is only possible to map 1GB of virtual address space.

In order to map all 4GB of virtual address space we need to adopt a
3-level page table layout. This actually works out better for
CONFIG_SUPERH32 because we only waste 2 PGD entries on the P1 and P2
areas (which are untranslated) instead of 256.

Signed-off-by: Matt Fleming <matt@console-pimps.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-12-17 14:31:20 +09:00
Matt Fleming b73c806341 sh: Abstract the number of page table levels
Keep the dimensions of the page tables in a separate header file in
preparation for allowing a three level page table structure.

Signed-off-by: Matt Fleming <matt@console-pimps.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-12-17 14:31:15 +09:00
Paul Mundt 2a8bc92345 sh: Shut up CONFIG_32BIT=n compiler warnings.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-10-10 22:24:55 +09:00
Matt Fleming 1f69b6af91 sh: Prepare for dynamic PMB support
To allow the MMU to be switched between 29bit and 32bit mode at runtime
some constants need to swapped for functions that return a runtime
value.

Signed-off-by: Matt Fleming <matt@console-pimps.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-10-10 21:51:12 +09:00
Paul Mundt 2739742c24 sh: Provide the kmap_coherent() interface generically.
This plugs in kmap_coherent() for the non-SH4 cases to permit the
pg-mmu.c bits to be used generically across all CPUs. SH-5 is still in
the TODO state, but will move over to fixmap and the generic interface
gradually.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-08-15 09:19:19 +09:00
Paul Mundt c7914834ef sh: Tidy up NEFF-based sign extension for SH-5.
This consolidates all of the NEFF-based sign extension for SH-5.
In the future the other SH code will need to make use of this as well,
so make it generic in preparation for more 32/64 consolidation.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-08-04 17:14:39 +09:00
Paul Mundt 9cef749269 sh: update_mmu_cache() consolidation.
This splits out a separate __update_cache()/__update_tlb() for
update_mmu_cache() to wrap in to. This lets us share the common
__update_cache() bits while keeping special __update_tlb() handling
broken out.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-07-29 00:12:17 +09:00
Paul Mundt 0dfae7d5a2 sh: Use the now generic SH-4 clear/copy page ops for all MMU platforms.
Now that the SH-4 page clear/copy ops are generic, they can be used for
all platforms with CONFIG_MMU=y. SH-5 remains the odd one out, but it too
will gradually be converted over to using this interface.

SH-3 platforms which do not contain aliases will see no impact from this
change, while aliasing SH-3 platforms will get the same interface as
SH-4.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-07-27 21:30:17 +09:00
Paul Mundt dfff0fa65a sh: wire up clear_user_highpage() for sh4, convert sh7705.
This wires up clear_user_highpage() on SH-4 and subsequently converts the
SH7705 32kB cache mode over to using it. Now that the SH-4 implementation
handles all of the dcache purging directly in the aliasing case, there is
no need to do this in the default clear_page() implementation.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-07-27 20:53:22 +09:00
Paul Mundt 2277ab4a1d sh: Migrate from PG_mapped to PG_dcache_dirty.
This inverts the delayed dcache flush a bit to be more in line with other
platforms. At the same time this also gives us the ability to do some
more optimizations and cleanup. Now that the update_mmu_cache() callsite
only tests for the bit, the implementation can gradually be split out and
made generic, rather than relying on special implementations for each of
the peculiar CPU types.

SH7705 in 32kB mode and SH-4 still need slightly different handling, but
this is something that can remain isolated in the varying page copy/clear
routines. On top of that, SH-X3 is dcache coherent, so there is no need
to bother with any of these tests in the PTEAEX version of
update_mmu_cache(), so we kill that off too.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-07-22 19:20:49 +09:00
Paul Mundt ee1acbfabd sh: Handle shm_align_mask also for HAVE_ARCH_UNMAPPED_AREA_TOPDOWN.
Presently shm_align_mask is only looked at for the bottom up case, but we
still want this for proper colouring constraints in the topdown case.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-05-07 16:38:16 +09:00
Paul Mundt acca4f4d9b sh: Handle fixmap TLB eviction more coherently.
There was a race in the kmap_coherent() implementation. While we
guarded against preemption, there was nothing preventing eviction of
the pre-faulted fixmap entry from the UTLB. Under certain workloads
this would result in the fixmap entries used for cache colouring being
evicted from the UTLB in the midst of a copy_page().

In addition to pre-faulting, we also make sure to preserve the PTEs
in the kernel page table and introduce a cached PTE for kmap_coherent()
usage. This follows a similar change on MIPS ("[MIPS] Fix aliasing bug
in copy_to_user_page / copy_from_user_page").

Reported-by: Hideo Saito <saito@densan.co.jp>
Reported-by: CHIKAMA Masaki <masaki.chikama@gmail.com>
Tested-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-11-10 20:00:45 +09:00
Paul Mundt cb700aa4f1 sh: ioremap_prot support.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-09-12 20:41:05 +09:00
Paul Mundt f15cbe6f1a sh: migrate to arch/sh/include/
This follows the sparc changes a439fe51a1.

Most of the moving about was done with Sam's directions at:

http://marc.info/?l=linux-sh&m=121724823706062&w=2

with subsequent hacking and fixups entirely my fault.

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-07-29 08:09:44 +09:00