Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and 'clk-rockchip' into clk-next
* clk-renesas: clk: renesas: rcar-gen3: Add HS400 quirk for SD clock clk: renesas: rcar-gen3: Add documentation for SD clocks clk: renesas: rcar-gen3: Set state when registering SD clocks clk: renesas: r8a77995: Simplify PLL3 multiplier/divider clk: renesas: r8a77995: Add missing CPEX clock clk: renesas: r8a77995: Remove non-existent SSP clocks clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks clk: renesas: r8a77995: Correct parent clock of DU clk: renesas: r8a77990: Correct parent clock of DU clk: renesas: r8a77970: Add CPEX clock clk: renesas: r8a77965: Add CPEX clock clk: renesas: r8a7796: Add CPEX clock clk: renesas: r8a7795: Add CPEX clock clk: renesas: r8a774a1: Add CPEX clock dt-bindings: clock: r8a7796: Remove CSIREF clock dt-bindings: clock: r8a7795: Remove CSIREF clock clk: renesas: Mark rza2_cpg_clk_register static clk: renesas: r7s9210: Add USB clocks clk: renesas: r8a77970: Add RPC clocks clk: renesas: r7s9210: Add SDHI clocks * clk-allwinner: clk: sunxi-ng: a64: Allow parent change for VE clock clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLL clk: sunxi-ng: h3: Allow parent change for ve clock clk: sunxi-ng: add support for suniv F1C100s SoC dt-bindings: clock: Add Allwinner suniv F1C100s CCU clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output clk: sunxi-ng: sun50i: a64: Use sigma-delta modulation for audio PLL clk: sunxi-ng: a64: Fix gate bit of DSI DPHY clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I clk: sunxi-ng: Add support for H6 DE3 clocks dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description clk: sunxi-ng: h6: Set video PLLs limits clk: sunxi-ng: Use u64 for calculation of NM rate clk: sunxi-ng: Adjust MP clock parent rate when allowed clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clock * clk-tegra: clk: tegra: Return the exact clock rate from clk_round_rate clk: tegra30: Use Tegra CPU powergate helper function soc/tegra: pmc: Drop SMP dependency from CPU APIs clk: tegra: Fix maximum audio sync clock for Tegra124/210 clk: tegra: get rid of duplicate defines clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC clk: tegra20: Turn EMC clock gate into divider * clk-meson: (25 commits) clk: meson: axg-audio: use the clk input helper function clk: meson: add clk-input helper function clk: meson: Mark some things static clk: meson: meson8b: add the read-only video clock trees clk: meson: meson8b: add the fractional divider for vid_pll_dco clk: meson: meson8b: fix the offset of vid_pll_dco's N value clk: meson: Fix GXL HDMI PLL fractional bits width clk: meson: meson8b: add the CPU clock post divider clocks clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3 clk: meson: clk-regmap: add read-only gate ops clk: meson: meson8b: allow changing the CPU clock tree clk: meson: meson8b: run from the XTAL when changing the CPU frequency clk: meson: meson8b: add support for more M/N values in sys_pll clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICAL clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel clk: meson: clk-pll: check if the clock is already enabled clk: meson: meson8b: fix the width of the cpu_scale_div clock clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table clk: meson: meson8b: use the HHI syscon if available dt-bindings: clock: meson8b: use the registers from the HHI syscon ... * clk-rockchip: clk: rockchip: add clock-id to gate of ACODEC for rk3328 clk: rockchip: add clock ID of ACODEC for rk3328 clk: rockchip: fix ID of 8ch clock of I2S1 for rk3328 clk: rockchip: fix I2S1 clock gate register for rk3328 clk: rockchip: make rk3188 hclk_vio_bus critical clk: rockchip: fix rk3188 sclk_mac_lbtest parameter ordering clk: rockchip: fix rk3188 sclk_smc gate data clk: rockchip: fix typo in rk3188 spdif_frac parent
This commit is contained in:
Stephen Boyd
commit
ffe05540d1
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|
@ -9,15 +9,13 @@ Required Properties:
|
|||
- "amlogic,meson8-clkc" for Meson8 (S802) SoCs
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- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
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- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
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- reg: it must be composed by two tuples:
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0) physical base address of the xtal register and length of memory
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mapped region.
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1) physical base address of the clock controller and length of memory
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mapped region.
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- #clock-cells: should be 1.
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- #reset-cells: should be 1.
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Parent node should have the following properties :
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- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
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- reg: base address and size of the HHI system control register space.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
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@ -30,9 +28,8 @@ device tree sources).
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Example: Clock controller node:
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clkc: clock-controller@c1104000 {
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clkc: clock-controller {
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compatible = "amlogic,meson8b-clkc";
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reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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|
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@ -1,5 +1,5 @@
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Allwinner Display Engine 2.0 Clock Control Binding
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--------------------------------------------------
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Allwinner Display Engine 2.0/3.0 Clock Control Binding
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------------------------------------------------------
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Required properties :
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- compatible: must contain one of the following compatibles:
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@ -8,6 +8,7 @@ Required properties :
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- "allwinner,sun8i-v3s-de2-clk"
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- "allwinner,sun50i-a64-de2-clk"
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- "allwinner,sun50i-h5-de2-clk"
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- "allwinner,sun50i-h6-de3-clk"
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- reg: Must contain the registers base address and length
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- clocks: phandle to the clocks feeding the display engine subsystem.
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@ -22,6 +22,7 @@ Required properties :
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- "allwinner,sun50i-h5-ccu"
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- "allwinner,sun50i-h6-ccu"
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- "allwinner,sun50i-h6-r-ccu"
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- "allwinner,suniv-f1c100s-ccu"
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- "nextthing,gr8-ccu"
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- reg: Must contain the registers base address and length
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@ -2,7 +2,8 @@
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# Makefile for Meson specific clk
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#
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obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o
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obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o vid-pll-div.o
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obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-input.o
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obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o sclk-div.o
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obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
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obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
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|
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@ -631,22 +631,23 @@ static struct clk_regmap *const axg_audio_clk_regmaps[] = {
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&axg_tdmout_c_lrclk,
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};
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static struct clk *devm_clk_get_enable(struct device *dev, char *id)
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static int devm_clk_get_enable(struct device *dev, char *id)
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{
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struct clk *clk;
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int ret;
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clk = devm_clk_get(dev, id);
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if (IS_ERR(clk)) {
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if (PTR_ERR(clk) != -EPROBE_DEFER)
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ret = PTR_ERR(clk);
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "failed to get %s", id);
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return clk;
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return ret;
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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dev_err(dev, "failed to enable %s", id);
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return ERR_PTR(ret);
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return ret;
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}
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ret = devm_add_action_or_reset(dev,
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@ -654,74 +655,40 @@ static struct clk *devm_clk_get_enable(struct device *dev, char *id)
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clk);
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if (ret) {
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dev_err(dev, "failed to add reset action on %s", id);
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return ERR_PTR(ret);
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return ret;
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}
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return clk;
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}
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static const struct clk_ops axg_clk_no_ops = {};
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static struct clk_hw *axg_clk_hw_register_bypass(struct device *dev,
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const char *name,
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const char *parent_name)
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{
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struct clk_hw *hw;
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struct clk_init_data init;
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char *clk_name;
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int ret;
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hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL);
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if (!hw)
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return ERR_PTR(-ENOMEM);
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clk_name = kasprintf(GFP_KERNEL, "axg_%s", name);
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if (!clk_name)
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return ERR_PTR(-ENOMEM);
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init.name = clk_name;
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init.ops = &axg_clk_no_ops;
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init.flags = 0;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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hw->init = &init;
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ret = devm_clk_hw_register(dev, hw);
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kfree(clk_name);
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return ret ? ERR_PTR(ret) : hw;
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return 0;
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}
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static int axg_register_clk_hw_input(struct device *dev,
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const char *name,
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unsigned int clkid)
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{
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struct clk *parent_clk = devm_clk_get(dev, name);
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struct clk_hw *hw = NULL;
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char *clk_name;
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struct clk_hw *hw;
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int err = 0;
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if (IS_ERR(parent_clk)) {
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int err = PTR_ERR(parent_clk);
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clk_name = kasprintf(GFP_KERNEL, "axg_%s", name);
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if (!clk_name)
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return -ENOMEM;
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hw = meson_clk_hw_register_input(dev, name, clk_name, 0);
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if (IS_ERR(hw)) {
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/* It is ok if an input clock is missing */
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if (err == -ENOENT) {
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if (PTR_ERR(hw) == -ENOENT) {
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dev_dbg(dev, "%s not provided", name);
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} else {
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err = PTR_ERR(hw);
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if (err != -EPROBE_DEFER)
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dev_err(dev, "failed to get %s clock", name);
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return err;
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}
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} else {
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hw = axg_clk_hw_register_bypass(dev, name,
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__clk_get_name(parent_clk));
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axg_audio_hw_onecell_data.hws[clkid] = hw;
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}
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if (IS_ERR(hw)) {
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dev_err(dev, "failed to register %s clock", name);
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return PTR_ERR(hw);
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}
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axg_audio_hw_onecell_data.hws[clkid] = hw;
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return 0;
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kfree(clk_name);
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return err;
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}
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static int axg_register_clk_hw_inputs(struct device *dev,
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@ -759,7 +726,6 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
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struct regmap *map;
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struct resource *res;
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void __iomem *regs;
|
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struct clk *clk;
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struct clk_hw *hw;
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int ret, i;
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||||
|
|
@ -775,9 +741,9 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
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}
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/* Get the mandatory peripheral clock */
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clk = devm_clk_get_enable(dev, "pclk");
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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ret = devm_clk_get_enable(dev, "pclk");
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if (ret)
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return ret;
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|
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ret = device_reset(dev);
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if (ret) {
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|
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@ -786,8 +752,7 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
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}
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/* Register the peripheral input clock */
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hw = axg_clk_hw_register_bypass(dev, "audio_pclk",
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__clk_get_name(clk));
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hw = meson_clk_hw_register_input(dev, "pclk", "axg_audio_pclk", 0);
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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|
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|
|
|
|||
|
|
@ -0,0 +1,44 @@
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|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (c) 2018 BayLibre, SAS.
|
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
|
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|
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include "clkc.h"
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|
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static const struct clk_ops meson_clk_no_ops = {};
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|
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struct clk_hw *meson_clk_hw_register_input(struct device *dev,
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const char *of_name,
|
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const char *clk_name,
|
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unsigned long flags)
|
||||
{
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struct clk *parent_clk = devm_clk_get(dev, of_name);
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struct clk_init_data init;
|
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const char *parent_name;
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struct clk_hw *hw;
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int ret;
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|
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if (IS_ERR(parent_clk))
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return (struct clk_hw *)parent_clk;
|
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|
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hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL);
|
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if (!hw)
|
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return ERR_PTR(-ENOMEM);
|
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|
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parent_name = __clk_get_name(parent_clk);
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init.name = clk_name;
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init.ops = &meson_clk_no_ops;
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init.flags = flags;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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hw->init = &init;
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ret = devm_clk_hw_register(dev, hw);
|
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|
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return ret ? ERR_PTR(ret) : hw;
|
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}
|
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EXPORT_SYMBOL_GPL(meson_clk_hw_register_input);
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|
|
@ -200,11 +200,28 @@ static void meson_clk_pll_init(struct clk_hw *hw)
|
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}
|
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}
|
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|
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static int meson_clk_pll_is_enabled(struct clk_hw *hw)
|
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{
|
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struct clk_regmap *clk = to_clk_regmap(hw);
|
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struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
|
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|
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if (meson_parm_read(clk->map, &pll->rst) ||
|
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!meson_parm_read(clk->map, &pll->en) ||
|
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!meson_parm_read(clk->map, &pll->l))
|
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return 0;
|
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|
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return 1;
|
||||
}
|
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|
||||
static int meson_clk_pll_enable(struct clk_hw *hw)
|
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{
|
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struct clk_regmap *clk = to_clk_regmap(hw);
|
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struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
|
||||
|
||||
/* do nothing if the PLL is already enabled */
|
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if (clk_hw_is_enabled(hw))
|
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return 0;
|
||||
|
||||
/* Make sure the pll is in reset */
|
||||
meson_parm_write(clk->map, &pll->rst, 1);
|
||||
|
||||
|
|
@ -288,10 +305,12 @@ const struct clk_ops meson_clk_pll_ops = {
|
|||
.recalc_rate = meson_clk_pll_recalc_rate,
|
||||
.round_rate = meson_clk_pll_round_rate,
|
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.set_rate = meson_clk_pll_set_rate,
|
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.is_enabled = meson_clk_pll_is_enabled,
|
||||
.enable = meson_clk_pll_enable,
|
||||
.disable = meson_clk_pll_disable
|
||||
};
|
||||
|
||||
const struct clk_ops meson_clk_pll_ro_ops = {
|
||||
.recalc_rate = meson_clk_pll_recalc_rate,
|
||||
.is_enabled = meson_clk_pll_is_enabled,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -50,6 +50,11 @@ const struct clk_ops clk_regmap_gate_ops = {
|
|||
};
|
||||
EXPORT_SYMBOL_GPL(clk_regmap_gate_ops);
|
||||
|
||||
const struct clk_ops clk_regmap_gate_ro_ops = {
|
||||
.is_enabled = clk_regmap_gate_is_enabled,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_regmap_gate_ro_ops);
|
||||
|
||||
static unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long prate)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ clk_get_regmap_gate_data(struct clk_regmap *clk)
|
|||
}
|
||||
|
||||
extern const struct clk_ops clk_regmap_gate_ops;
|
||||
extern const struct clk_ops clk_regmap_gate_ro_ops;
|
||||
|
||||
/**
|
||||
* struct clk_regmap_div_data - regmap backed adjustable divider specific data
|
||||
|
|
|
|||
|
|
@ -90,6 +90,11 @@ struct meson_clk_phase_data {
|
|||
int meson_clk_degrees_from_val(unsigned int val, unsigned int width);
|
||||
unsigned int meson_clk_degrees_to_val(int degrees, unsigned int width);
|
||||
|
||||
struct meson_vid_pll_div_data {
|
||||
struct parm val;
|
||||
struct parm sel;
|
||||
};
|
||||
|
||||
#define MESON_GATE(_name, _reg, _bit) \
|
||||
struct clk_regmap _name = { \
|
||||
.data = &(struct clk_regmap_gate_data){ \
|
||||
|
|
@ -112,5 +117,11 @@ extern const struct clk_ops meson_clk_cpu_ops;
|
|||
extern const struct clk_ops meson_clk_mpll_ro_ops;
|
||||
extern const struct clk_ops meson_clk_mpll_ops;
|
||||
extern const struct clk_ops meson_clk_phase_ops;
|
||||
extern const struct clk_ops meson_vid_pll_div_ro_ops;
|
||||
|
||||
struct clk_hw *meson_clk_hw_register_input(struct device *dev,
|
||||
const char *of_name,
|
||||
const char *clk_name,
|
||||
unsigned long flags);
|
||||
|
||||
#endif /* __CLKC_H */
|
||||
|
|
|
|||
|
|
@ -199,6 +199,58 @@ static struct clk_regmap gxbb_hdmi_pll_dco = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxl_hdmi_pll_dco = {
|
||||
.data = &(struct meson_clk_pll_data){
|
||||
.en = {
|
||||
.reg_off = HHI_HDMI_PLL_CNTL,
|
||||
.shift = 30,
|
||||
.width = 1,
|
||||
},
|
||||
.m = {
|
||||
.reg_off = HHI_HDMI_PLL_CNTL,
|
||||
.shift = 0,
|
||||
.width = 9,
|
||||
},
|
||||
.n = {
|
||||
.reg_off = HHI_HDMI_PLL_CNTL,
|
||||
.shift = 9,
|
||||
.width = 5,
|
||||
},
|
||||
/*
|
||||
* On gxl, there is a register shift due to
|
||||
* HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
|
||||
* so we use the HHI_HDMI_PLL_CNTL2 define from GXBB
|
||||
* instead which is defined at the same offset.
|
||||
*/
|
||||
.frac = {
|
||||
.reg_off = HHI_HDMI_PLL_CNTL2,
|
||||
.shift = 0,
|
||||
.width = 10,
|
||||
},
|
||||
.l = {
|
||||
.reg_off = HHI_HDMI_PLL_CNTL,
|
||||
.shift = 31,
|
||||
.width = 1,
|
||||
},
|
||||
.rst = {
|
||||
.reg_off = HHI_HDMI_PLL_CNTL,
|
||||
.shift = 28,
|
||||
.width = 1,
|
||||
},
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "hdmi_pll_dco",
|
||||
.ops = &meson_clk_pll_ro_ops,
|
||||
.parent_names = (const char *[]){ "xtal" },
|
||||
.num_parents = 1,
|
||||
/*
|
||||
* Display directly handle hdmi pll registers ATM, we need
|
||||
* NOCACHE to keep our view of the clock as accurate as possible
|
||||
*/
|
||||
.flags = CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_hdmi_pll_od = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_HDMI_PLL_CNTL2,
|
||||
|
|
@ -1512,6 +1564,616 @@ static struct clk_regmap gxbb_vapb = {
|
|||
},
|
||||
};
|
||||
|
||||
/* Video Clocks */
|
||||
|
||||
static struct clk_regmap gxbb_vid_pll_div = {
|
||||
.data = &(struct meson_vid_pll_div_data){
|
||||
.val = {
|
||||
.reg_off = HHI_VID_PLL_CLK_DIV,
|
||||
.shift = 0,
|
||||
.width = 15,
|
||||
},
|
||||
.sel = {
|
||||
.reg_off = HHI_VID_PLL_CLK_DIV,
|
||||
.shift = 16,
|
||||
.width = 2,
|
||||
},
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vid_pll_div",
|
||||
.ops = &meson_vid_pll_div_ro_ops,
|
||||
.parent_names = (const char *[]){ "hdmi_pll" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
static const char * const gxbb_vid_pll_parent_names[] = { "vid_pll_div", "hdmi_pll" };
|
||||
|
||||
static struct clk_regmap gxbb_vid_pll_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_VID_PLL_CLK_DIV,
|
||||
.mask = 0x1,
|
||||
.shift = 18,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vid_pll_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
/*
|
||||
* bit 18 selects from 2 possible parents:
|
||||
* vid_pll_div or hdmi_pll
|
||||
*/
|
||||
.parent_names = gxbb_vid_pll_parent_names,
|
||||
.num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_names),
|
||||
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_vid_pll = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VID_PLL_CLK_DIV,
|
||||
.bit_idx = 19,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vid_pll",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vid_pll_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
static const char * const gxbb_vclk_parent_names[] = {
|
||||
"vid_pll", "fclk_div4", "fclk_div3", "fclk_div5", "vid_pll",
|
||||
"fclk_div7", "mpll1",
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_vclk_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_VID_CLK_CNTL,
|
||||
.mask = 0x7,
|
||||
.shift = 16,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
/*
|
||||
* bits 16:18 selects from 8 possible parents:
|
||||
* vid_pll, fclk_div4, fclk_div3, fclk_div5,
|
||||
* vid_pll, fclk_div7, mp1
|
||||
*/
|
||||
.parent_names = gxbb_vclk_parent_names,
|
||||
.num_parents = ARRAY_SIZE(gxbb_vclk_parent_names),
|
||||
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_vclk2_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_VIID_CLK_CNTL,
|
||||
.mask = 0x7,
|
||||
.shift = 16,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk2_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
/*
|
||||
* bits 16:18 selects from 8 possible parents:
|
||||
* vid_pll, fclk_div4, fclk_div3, fclk_div5,
|
||||
* vid_pll, fclk_div7, mp1
|
||||
*/
|
||||
.parent_names = gxbb_vclk_parent_names,
|
||||
.num_parents = ARRAY_SIZE(gxbb_vclk_parent_names),
|
||||
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_vclk_input = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VID_CLK_DIV,
|
||||
.bit_idx = 16,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vclk_input",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vclk_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_vclk2_input = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VIID_CLK_DIV,
|
||||
.bit_idx = 16,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vclk2_input",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vclk2_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_vclk_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_VID_CLK_DIV,
|
||||
.shift = 0,
|
||||
.width = 8,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "vclk_input" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_vclk2_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_VIID_CLK_DIV,
|
||||
.shift = 0,
|
||||
.width = 8,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk2_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "vclk2_input" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_vclk = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VID_CLK_CNTL,
|
||||
.bit_idx = 19,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vclk",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vclk_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_vclk2 = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VIID_CLK_CNTL,
|
||||
.bit_idx = 19,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vclk2",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vclk2_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_vclk_div1 = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VID_CLK_CNTL,
|
||||
.bit_idx = 0,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vclk_div1",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vclk" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_vclk_div2_en = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VID_CLK_CNTL,
|
||||
.bit_idx = 1,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vclk_div2_en",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vclk" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_vclk_div4_en = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VID_CLK_CNTL,
|
||||
.bit_idx = 2,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vclk_div4_en",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vclk" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_vclk_div6_en = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VID_CLK_CNTL,
|
||||
.bit_idx = 3,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vclk_div6_en",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vclk" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_vclk_div12_en = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VID_CLK_CNTL,
|
||||
.bit_idx = 4,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vclk_div12_en",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vclk" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_vclk2_div1 = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VIID_CLK_CNTL,
|
||||
.bit_idx = 0,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vclk2_div1",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vclk2" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_vclk2_div2_en = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VIID_CLK_CNTL,
|
||||
.bit_idx = 1,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vclk2_div2_en",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vclk2" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_vclk2_div4_en = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VIID_CLK_CNTL,
|
||||
.bit_idx = 2,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vclk2_div4_en",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vclk2" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_vclk2_div6_en = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VIID_CLK_CNTL,
|
||||
.bit_idx = 3,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vclk2_div6_en",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vclk2" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_vclk2_div12_en = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VIID_CLK_CNTL,
|
||||
.bit_idx = 4,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vclk2_div12_en",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vclk2" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor gxbb_vclk_div2 = {
|
||||
.mult = 1,
|
||||
.div = 2,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk_div2",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "vclk_div2_en" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor gxbb_vclk_div4 = {
|
||||
.mult = 1,
|
||||
.div = 4,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk_div4",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "vclk_div4_en" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor gxbb_vclk_div6 = {
|
||||
.mult = 1,
|
||||
.div = 6,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk_div6",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "vclk_div6_en" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor gxbb_vclk_div12 = {
|
||||
.mult = 1,
|
||||
.div = 12,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk_div12",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "vclk_div12_en" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor gxbb_vclk2_div2 = {
|
||||
.mult = 1,
|
||||
.div = 2,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk2_div2",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "vclk2_div2_en" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor gxbb_vclk2_div4 = {
|
||||
.mult = 1,
|
||||
.div = 4,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk2_div4",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "vclk2_div4_en" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor gxbb_vclk2_div6 = {
|
||||
.mult = 1,
|
||||
.div = 6,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk2_div6",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "vclk2_div6_en" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor gxbb_vclk2_div12 = {
|
||||
.mult = 1,
|
||||
.div = 12,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk2_div12",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "vclk2_div12_en" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
|
||||
static const char * const gxbb_cts_parent_names[] = {
|
||||
"vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
|
||||
"vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
|
||||
"vclk2_div6", "vclk2_div12"
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_cts_enci_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_VID_CLK_DIV,
|
||||
.mask = 0xf,
|
||||
.shift = 28,
|
||||
.table = mux_table_cts_sel,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_enci_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = gxbb_cts_parent_names,
|
||||
.num_parents = ARRAY_SIZE(gxbb_cts_parent_names),
|
||||
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_cts_encp_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_VID_CLK_DIV,
|
||||
.mask = 0xf,
|
||||
.shift = 20,
|
||||
.table = mux_table_cts_sel,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_encp_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = gxbb_cts_parent_names,
|
||||
.num_parents = ARRAY_SIZE(gxbb_cts_parent_names),
|
||||
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_cts_vdac_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_VIID_CLK_DIV,
|
||||
.mask = 0xf,
|
||||
.shift = 28,
|
||||
.table = mux_table_cts_sel,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_vdac_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = gxbb_cts_parent_names,
|
||||
.num_parents = ARRAY_SIZE(gxbb_cts_parent_names),
|
||||
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
/* TOFIX: add support for cts_tcon */
|
||||
static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
|
||||
static const char * const gxbb_cts_hdmi_tx_parent_names[] = {
|
||||
"vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
|
||||
"vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
|
||||
"vclk2_div6", "vclk2_div12"
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_hdmi_tx_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_HDMI_CLK_CNTL,
|
||||
.mask = 0xf,
|
||||
.shift = 16,
|
||||
.table = mux_table_hdmi_tx_sel,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "hdmi_tx_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
/*
|
||||
* bits 31:28 selects from 12 possible parents:
|
||||
* vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
|
||||
* vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
|
||||
* cts_tcon
|
||||
*/
|
||||
.parent_names = gxbb_cts_hdmi_tx_parent_names,
|
||||
.num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_names),
|
||||
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_cts_enci = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VID_CLK_CNTL2,
|
||||
.bit_idx = 0,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cts_enci",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "cts_enci_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_cts_encp = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VID_CLK_CNTL2,
|
||||
.bit_idx = 2,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cts_encp",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "cts_encp_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_cts_vdac = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VID_CLK_CNTL2,
|
||||
.bit_idx = 4,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cts_vdac",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "cts_vdac_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_hdmi_tx = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VID_CLK_CNTL2,
|
||||
.bit_idx = 5,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "hdmi_tx",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "hdmi_tx_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
/* HDMI Clocks */
|
||||
|
||||
static const char * const gxbb_hdmi_parent_names[] = {
|
||||
"xtal", "fclk_div4", "fclk_div3", "fclk_div5"
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_hdmi_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_HDMI_CLK_CNTL,
|
||||
.mask = 0x3,
|
||||
.shift = 9,
|
||||
.flags = CLK_MUX_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "hdmi_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = gxbb_hdmi_parent_names,
|
||||
.num_parents = ARRAY_SIZE(gxbb_hdmi_parent_names),
|
||||
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_hdmi_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_HDMI_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "hdmi_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "hdmi_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap gxbb_hdmi = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_HDMI_CLK_CNTL,
|
||||
.bit_idx = 8,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "hdmi",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "hdmi_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
/* VDEC clocks */
|
||||
|
||||
static const char * const gxbb_vdec_parent_names[] = {
|
||||
|
|
@ -1923,6 +2585,46 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
|
|||
[CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw,
|
||||
[CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
|
||||
[CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw,
|
||||
[CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
|
||||
[CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
|
||||
[CLKID_VID_PLL] = &gxbb_vid_pll.hw,
|
||||
[CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
|
||||
[CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
|
||||
[CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
|
||||
[CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
|
||||
[CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
|
||||
[CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
|
||||
[CLKID_VCLK] = &gxbb_vclk.hw,
|
||||
[CLKID_VCLK2] = &gxbb_vclk2.hw,
|
||||
[CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
|
||||
[CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
|
||||
[CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
|
||||
[CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
|
||||
[CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
|
||||
[CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
|
||||
[CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
|
||||
[CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
|
||||
[CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
|
||||
[CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
|
||||
[CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
|
||||
[CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
|
||||
[CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
|
||||
[CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
|
||||
[CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
|
||||
[CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
|
||||
[CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
|
||||
[CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
|
||||
[CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
|
||||
[CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
|
||||
[CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
|
||||
[CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
|
||||
[CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
|
||||
[CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
|
||||
[CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
|
||||
[CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
|
||||
[CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
|
||||
[CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
|
||||
[CLKID_HDMI] = &gxbb_hdmi.hw,
|
||||
[NR_CLKS] = NULL,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
|
|
@ -2089,11 +2791,51 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
|
|||
[CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
|
||||
[CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
|
||||
[CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
|
||||
[CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw,
|
||||
[CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw,
|
||||
[CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw,
|
||||
[CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw,
|
||||
[CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
|
||||
[CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw,
|
||||
[CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
|
||||
[CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
|
||||
[CLKID_VID_PLL] = &gxbb_vid_pll.hw,
|
||||
[CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
|
||||
[CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
|
||||
[CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
|
||||
[CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
|
||||
[CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
|
||||
[CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
|
||||
[CLKID_VCLK] = &gxbb_vclk.hw,
|
||||
[CLKID_VCLK2] = &gxbb_vclk2.hw,
|
||||
[CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
|
||||
[CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
|
||||
[CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
|
||||
[CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
|
||||
[CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
|
||||
[CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
|
||||
[CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
|
||||
[CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
|
||||
[CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
|
||||
[CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
|
||||
[CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
|
||||
[CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
|
||||
[CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
|
||||
[CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
|
||||
[CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
|
||||
[CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
|
||||
[CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
|
||||
[CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
|
||||
[CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
|
||||
[CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
|
||||
[CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
|
||||
[CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
|
||||
[CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
|
||||
[CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
|
||||
[CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
|
||||
[CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
|
||||
[CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
|
||||
[CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
|
||||
[CLKID_HDMI] = &gxbb_hdmi.hw,
|
||||
[NR_CLKS] = NULL,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
|
|
@ -2104,6 +2846,7 @@ static struct clk_regmap *const gxbb_clk_regmaps[] = {
|
|||
&gxbb_hdmi_pll,
|
||||
&gxbb_hdmi_pll_od,
|
||||
&gxbb_hdmi_pll_od2,
|
||||
&gxbb_hdmi_pll_dco,
|
||||
};
|
||||
|
||||
static struct clk_regmap *const gxl_clk_regmaps[] = {
|
||||
|
|
@ -2111,6 +2854,7 @@ static struct clk_regmap *const gxl_clk_regmaps[] = {
|
|||
&gxl_hdmi_pll,
|
||||
&gxl_hdmi_pll_od,
|
||||
&gxl_hdmi_pll_od2,
|
||||
&gxl_hdmi_pll_dco,
|
||||
};
|
||||
|
||||
static struct clk_regmap *const gx_clk_regmaps[] = {
|
||||
|
|
@ -2266,9 +3010,40 @@ static struct clk_regmap *const gx_clk_regmaps[] = {
|
|||
&gxbb_gen_clk_div,
|
||||
&gxbb_gen_clk,
|
||||
&gxbb_fixed_pll_dco,
|
||||
&gxbb_hdmi_pll_dco,
|
||||
&gxbb_sys_pll_dco,
|
||||
&gxbb_gp0_pll,
|
||||
&gxbb_vid_pll,
|
||||
&gxbb_vid_pll_sel,
|
||||
&gxbb_vid_pll_div,
|
||||
&gxbb_vclk,
|
||||
&gxbb_vclk_sel,
|
||||
&gxbb_vclk_div,
|
||||
&gxbb_vclk_input,
|
||||
&gxbb_vclk_div1,
|
||||
&gxbb_vclk_div2_en,
|
||||
&gxbb_vclk_div4_en,
|
||||
&gxbb_vclk_div6_en,
|
||||
&gxbb_vclk_div12_en,
|
||||
&gxbb_vclk2,
|
||||
&gxbb_vclk2_sel,
|
||||
&gxbb_vclk2_div,
|
||||
&gxbb_vclk2_input,
|
||||
&gxbb_vclk2_div1,
|
||||
&gxbb_vclk2_div2_en,
|
||||
&gxbb_vclk2_div4_en,
|
||||
&gxbb_vclk2_div6_en,
|
||||
&gxbb_vclk2_div12_en,
|
||||
&gxbb_cts_enci,
|
||||
&gxbb_cts_enci_sel,
|
||||
&gxbb_cts_encp,
|
||||
&gxbb_cts_encp_sel,
|
||||
&gxbb_cts_vdac,
|
||||
&gxbb_cts_vdac_sel,
|
||||
&gxbb_hdmi_tx,
|
||||
&gxbb_hdmi_tx_sel,
|
||||
&gxbb_hdmi_sel,
|
||||
&gxbb_hdmi_div,
|
||||
&gxbb_hdmi,
|
||||
};
|
||||
|
||||
struct clkc_data {
|
||||
|
|
|
|||
|
|
@ -165,8 +165,30 @@
|
|||
#define CLKID_HDMI_PLL_OD2 163
|
||||
#define CLKID_SYS_PLL_DCO 164
|
||||
#define CLKID_GP0_PLL_DCO 165
|
||||
#define CLKID_VID_PLL_SEL 167
|
||||
#define CLKID_VID_PLL_DIV 168
|
||||
#define CLKID_VCLK_SEL 169
|
||||
#define CLKID_VCLK2_SEL 170
|
||||
#define CLKID_VCLK_INPUT 171
|
||||
#define CLKID_VCLK2_INPUT 172
|
||||
#define CLKID_VCLK_DIV 173
|
||||
#define CLKID_VCLK2_DIV 174
|
||||
#define CLKID_VCLK_DIV2_EN 177
|
||||
#define CLKID_VCLK_DIV4_EN 178
|
||||
#define CLKID_VCLK_DIV6_EN 179
|
||||
#define CLKID_VCLK_DIV12_EN 180
|
||||
#define CLKID_VCLK2_DIV2_EN 181
|
||||
#define CLKID_VCLK2_DIV4_EN 182
|
||||
#define CLKID_VCLK2_DIV6_EN 183
|
||||
#define CLKID_VCLK2_DIV12_EN 184
|
||||
#define CLKID_CTS_ENCI_SEL 195
|
||||
#define CLKID_CTS_ENCP_SEL 196
|
||||
#define CLKID_CTS_VDAC_SEL 197
|
||||
#define CLKID_HDMI_TX_SEL 198
|
||||
#define CLKID_HDMI_SEL 203
|
||||
#define CLKID_HDMI_DIV 204
|
||||
|
||||
#define NR_CLKS 166
|
||||
#define NR_CLKS 206
|
||||
|
||||
/* include the CLKIDs that have been made part of the DT binding */
|
||||
#include <dt-bindings/clock/gxbb-clkc.h>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -19,20 +19,26 @@
|
|||
*
|
||||
* [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
|
||||
*/
|
||||
#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
|
||||
#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
|
||||
#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
|
||||
#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
|
||||
#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
|
||||
#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
|
||||
#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
|
||||
#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
|
||||
#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */
|
||||
#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
|
||||
#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
|
||||
#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
|
||||
#define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */
|
||||
#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
|
||||
#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */
|
||||
#define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet */
|
||||
#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
|
||||
#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
|
||||
#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
|
||||
#define HHI_VID_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */
|
||||
|
||||
/*
|
||||
* MPLL register offeset taken from the S905 datasheet. Vendor kernel source
|
||||
|
|
@ -63,8 +69,8 @@
|
|||
#define CLKID_MPLL1_DIV 97
|
||||
#define CLKID_MPLL2_DIV 98
|
||||
#define CLKID_CPU_IN_SEL 99
|
||||
#define CLKID_CPU_DIV2 100
|
||||
#define CLKID_CPU_DIV3 101
|
||||
#define CLKID_CPU_IN_DIV2 100
|
||||
#define CLKID_CPU_IN_DIV3 101
|
||||
#define CLKID_CPU_SCALE_DIV 102
|
||||
#define CLKID_CPU_SCALE_OUT_SEL 103
|
||||
#define CLKID_MPLL_PREDIV 104
|
||||
|
|
@ -76,10 +82,65 @@
|
|||
#define CLKID_NAND_SEL 110
|
||||
#define CLKID_NAND_DIV 111
|
||||
#define CLKID_PLL_FIXED_DCO 113
|
||||
#define CLKID_PLL_VID_DCO 114
|
||||
#define CLKID_HDMI_PLL_DCO 114
|
||||
#define CLKID_PLL_SYS_DCO 115
|
||||
#define CLKID_CPU_CLK_DIV2 116
|
||||
#define CLKID_CPU_CLK_DIV3 117
|
||||
#define CLKID_CPU_CLK_DIV4 118
|
||||
#define CLKID_CPU_CLK_DIV5 119
|
||||
#define CLKID_CPU_CLK_DIV6 120
|
||||
#define CLKID_CPU_CLK_DIV7 121
|
||||
#define CLKID_CPU_CLK_DIV8 122
|
||||
#define CLKID_ABP_SEL 123
|
||||
#define CLKID_PERIPH_SEL 125
|
||||
#define CLKID_AXI_SEL 127
|
||||
#define CLKID_L2_DRAM_SEL 129
|
||||
#define CLKID_HDMI_PLL_LVDS_OUT 131
|
||||
#define CLKID_HDMI_PLL_HDMI_OUT 132
|
||||
#define CLKID_VID_PLL_IN_SEL 133
|
||||
#define CLKID_VID_PLL_IN_EN 134
|
||||
#define CLKID_VID_PLL_PRE_DIV 135
|
||||
#define CLKID_VID_PLL_POST_DIV 136
|
||||
#define CLKID_VID_PLL_FINAL_DIV 137
|
||||
#define CLKID_VCLK_IN_SEL 138
|
||||
#define CLKID_VCLK_IN_EN 139
|
||||
#define CLKID_VCLK_DIV1 140
|
||||
#define CLKID_VCLK_DIV2_DIV 141
|
||||
#define CLKID_VCLK_DIV2 142
|
||||
#define CLKID_VCLK_DIV4_DIV 143
|
||||
#define CLKID_VCLK_DIV4 144
|
||||
#define CLKID_VCLK_DIV6_DIV 145
|
||||
#define CLKID_VCLK_DIV6 146
|
||||
#define CLKID_VCLK_DIV12_DIV 147
|
||||
#define CLKID_VCLK_DIV12 148
|
||||
#define CLKID_VCLK2_IN_SEL 149
|
||||
#define CLKID_VCLK2_IN_EN 150
|
||||
#define CLKID_VCLK2_DIV1 151
|
||||
#define CLKID_VCLK2_DIV2_DIV 152
|
||||
#define CLKID_VCLK2_DIV2 153
|
||||
#define CLKID_VCLK2_DIV4_DIV 154
|
||||
#define CLKID_VCLK2_DIV4 155
|
||||
#define CLKID_VCLK2_DIV6_DIV 156
|
||||
#define CLKID_VCLK2_DIV6 157
|
||||
#define CLKID_VCLK2_DIV12_DIV 158
|
||||
#define CLKID_VCLK2_DIV12 159
|
||||
#define CLKID_CTS_ENCT_SEL 160
|
||||
#define CLKID_CTS_ENCT 161
|
||||
#define CLKID_CTS_ENCP_SEL 162
|
||||
#define CLKID_CTS_ENCP 163
|
||||
#define CLKID_CTS_ENCI_SEL 164
|
||||
#define CLKID_CTS_ENCI 165
|
||||
#define CLKID_HDMI_TX_PIXEL_SEL 166
|
||||
#define CLKID_HDMI_TX_PIXEL 167
|
||||
#define CLKID_CTS_ENCL_SEL 168
|
||||
#define CLKID_CTS_ENCL 169
|
||||
#define CLKID_CTS_VDAC0_SEL 170
|
||||
#define CLKID_CTS_VDAC0 171
|
||||
#define CLKID_HDMI_SYS_SEL 172
|
||||
#define CLKID_HDMI_SYS_DIV 173
|
||||
#define CLKID_HDMI_SYS 174
|
||||
|
||||
#define CLK_NR_CLKS 116
|
||||
#define CLK_NR_CLKS 175
|
||||
|
||||
/*
|
||||
* include the CLKID and RESETID that have
|
||||
|
|
|
|||
|
|
@ -0,0 +1,91 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2018 BayLibre, SAS.
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include "clkc.h"
|
||||
|
||||
static inline struct meson_vid_pll_div_data *
|
||||
meson_vid_pll_div_data(struct clk_regmap *clk)
|
||||
{
|
||||
return (struct meson_vid_pll_div_data *)clk->data;
|
||||
}
|
||||
|
||||
/*
|
||||
* This vid_pll divided is a fully programmable fractionnal divider to
|
||||
* achieve complex video clock rates.
|
||||
*
|
||||
* Here are provided the commonly used fraction values provided by Amlogic.
|
||||
*/
|
||||
|
||||
struct vid_pll_div {
|
||||
unsigned int shift_val;
|
||||
unsigned int shift_sel;
|
||||
unsigned int divider;
|
||||
unsigned int multiplier;
|
||||
};
|
||||
|
||||
#define VID_PLL_DIV(_val, _sel, _ft, _fb) \
|
||||
{ \
|
||||
.shift_val = (_val), \
|
||||
.shift_sel = (_sel), \
|
||||
.divider = (_ft), \
|
||||
.multiplier = (_fb), \
|
||||
}
|
||||
|
||||
static const struct vid_pll_div vid_pll_div_table[] = {
|
||||
VID_PLL_DIV(0x0aaa, 0, 2, 1), /* 2/1 => /2 */
|
||||
VID_PLL_DIV(0x5294, 2, 5, 2), /* 5/2 => /2.5 */
|
||||
VID_PLL_DIV(0x0db6, 0, 3, 1), /* 3/1 => /3 */
|
||||
VID_PLL_DIV(0x36cc, 1, 7, 2), /* 7/2 => /3.5 */
|
||||
VID_PLL_DIV(0x6666, 2, 15, 4), /* 15/4 => /3.75 */
|
||||
VID_PLL_DIV(0x0ccc, 0, 4, 1), /* 4/1 => /4 */
|
||||
VID_PLL_DIV(0x739c, 2, 5, 1), /* 5/1 => /5 */
|
||||
VID_PLL_DIV(0x0e38, 0, 6, 1), /* 6/1 => /6 */
|
||||
VID_PLL_DIV(0x0000, 3, 25, 4), /* 25/4 => /6.25 */
|
||||
VID_PLL_DIV(0x3c78, 1, 7, 1), /* 7/1 => /7 */
|
||||
VID_PLL_DIV(0x78f0, 2, 15, 2), /* 15/2 => /7.5 */
|
||||
VID_PLL_DIV(0x0fc0, 0, 12, 1), /* 12/1 => /12 */
|
||||
VID_PLL_DIV(0x3f80, 1, 14, 1), /* 14/1 => /14 */
|
||||
VID_PLL_DIV(0x7f80, 2, 15, 1), /* 15/1 => /15 */
|
||||
};
|
||||
|
||||
#define to_meson_vid_pll_div(_hw) \
|
||||
container_of(_hw, struct meson_vid_pll_div, hw)
|
||||
|
||||
static const struct vid_pll_div *_get_table_val(unsigned int shift_val,
|
||||
unsigned int shift_sel)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0 ; i < ARRAY_SIZE(vid_pll_div_table) ; ++i) {
|
||||
if (vid_pll_div_table[i].shift_val == shift_val &&
|
||||
vid_pll_div_table[i].shift_sel == shift_sel)
|
||||
return &vid_pll_div_table[i];
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static unsigned long meson_vid_pll_div_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_regmap *clk = to_clk_regmap(hw);
|
||||
struct meson_vid_pll_div_data *pll_div = meson_vid_pll_div_data(clk);
|
||||
const struct vid_pll_div *div;
|
||||
|
||||
div = _get_table_val(meson_parm_read(clk->map, &pll_div->val),
|
||||
meson_parm_read(clk->map, &pll_div->sel));
|
||||
if (!div || !div->divider) {
|
||||
pr_info("%s: Invalid config value for vid_pll_div\n", __func__);
|
||||
return parent_rate;
|
||||
}
|
||||
|
||||
return DIV_ROUND_UP_ULL(parent_rate * div->multiplier, div->divider);
|
||||
}
|
||||
|
||||
const struct clk_ops meson_vid_pll_div_ro_ops = {
|
||||
.recalc_rate = meson_vid_pll_div_recalc_rate,
|
||||
};
|
||||
|
|
@ -87,6 +87,8 @@ static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = {
|
|||
DEF_MOD_STB("scif1", 46, R7S9210_CLK_P1C),
|
||||
DEF_MOD_STB("scif0", 47, R7S9210_CLK_P1C),
|
||||
|
||||
DEF_MOD_STB("usb1", 60, R7S9210_CLK_B),
|
||||
DEF_MOD_STB("usb0", 61, R7S9210_CLK_B),
|
||||
DEF_MOD_STB("ether1", 64, R7S9210_CLK_B),
|
||||
DEF_MOD_STB("ether0", 65, R7S9210_CLK_B),
|
||||
|
||||
|
|
@ -98,6 +100,11 @@ static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = {
|
|||
DEF_MOD_STB("spi2", 95, R7S9210_CLK_P1),
|
||||
DEF_MOD_STB("spi1", 96, R7S9210_CLK_P1),
|
||||
DEF_MOD_STB("spi0", 97, R7S9210_CLK_P1),
|
||||
|
||||
DEF_MOD_STB("sdhi11", 100, R7S9210_CLK_B),
|
||||
DEF_MOD_STB("sdhi10", 101, R7S9210_CLK_B),
|
||||
DEF_MOD_STB("sdhi01", 102, R7S9210_CLK_B),
|
||||
DEF_MOD_STB("sdhi00", 103, R7S9210_CLK_B),
|
||||
};
|
||||
|
||||
/* The clock dividers in the table vary based on DT and register settings */
|
||||
|
|
@ -148,7 +155,7 @@ static void __init r7s9210_update_clk_table(struct clk *extal_clk,
|
|||
}
|
||||
}
|
||||
|
||||
struct clk * __init rza2_cpg_clk_register(struct device *dev,
|
||||
static struct clk * __init rza2_cpg_clk_register(struct device *dev,
|
||||
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
|
||||
struct clk **clks, void __iomem *base,
|
||||
struct raw_notifier_head *notifiers)
|
||||
|
|
|
|||
|
|
@ -100,6 +100,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
|
|||
|
||||
DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A774A1_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
||||
DEF_DIV6P1("csi0", R8A774A1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
|
||||
DEF_DIV6P1("mso", R8A774A1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
|
|
|
|||
|
|
@ -104,6 +104,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
|
|||
DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1),
|
||||
DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A7795_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
||||
DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
|
||||
|
|
|
|||
|
|
@ -103,6 +103,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
|
|||
|
||||
DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A7796_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
||||
DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
|
||||
|
|
|
|||
|
|
@ -100,6 +100,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
|
|||
|
||||
DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A77965_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A77965_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
||||
DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
|
||||
|
|
|
|||
|
|
@ -91,8 +91,12 @@ static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
|
|||
CLK_PLL1_DIV2),
|
||||
DEF_BASE("sd0", R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2),
|
||||
|
||||
DEF_FIXED("rpc", R8A77970_CLK_RPC, CLK_PLL1_DIV2, 5, 1),
|
||||
DEF_FIXED("rpcd2", R8A77970_CLK_RPCD2, CLK_PLL1_DIV2, 10, 1),
|
||||
|
||||
DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A77970_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
||||
DEF_DIV6P1("canfd", R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
|
||||
DEF_DIV6P1("mso", R8A77970_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
|
|
@ -152,6 +156,7 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
|
|||
DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
|
||||
DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
|
||||
DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
|
||||
DEF_MOD("rpc-if", 917, R8A77970_CLK_RPC),
|
||||
DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
|
||||
DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
|
||||
DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
|
||||
|
|
|
|||
|
|
@ -183,8 +183,8 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
|
|||
DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
|
||||
DEF_MOD("du1", 723, R8A77990_CLK_S2D1),
|
||||
DEF_MOD("du0", 724, R8A77990_CLK_S2D1),
|
||||
DEF_MOD("du1", 723, R8A77990_CLK_S1D1),
|
||||
DEF_MOD("du0", 724, R8A77990_CLK_S1D1),
|
||||
DEF_MOD("lvds", 727, R8A77990_CLK_S2D1),
|
||||
|
||||
DEF_MOD("vin5", 806, R8A77990_CLK_S1D2),
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A77995_CLK_CP,
|
||||
LAST_DT_CORE_CLK = R8A77995_CLK_CPEX,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
|
|
@ -42,7 +42,6 @@ enum clk_ids {
|
|||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_SSPSRC,
|
||||
CLK_RINT,
|
||||
CLK_OCO,
|
||||
|
||||
|
|
@ -93,6 +92,7 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
|
|||
|
||||
DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A77995_CLK_CPEX, CLK_EXTAL, 4, 1),
|
||||
|
||||
DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
|
||||
|
||||
|
|
@ -146,12 +146,9 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
|
|||
DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
|
||||
DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("du1", 723, R8A77995_CLK_S2D1),
|
||||
DEF_MOD("du0", 724, R8A77995_CLK_S2D1),
|
||||
DEF_MOD("du1", 723, R8A77995_CLK_S1D1),
|
||||
DEF_MOD("du0", 724, R8A77995_CLK_S1D1),
|
||||
DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
|
||||
DEF_MOD("vin7", 804, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("vin6", 805, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("vin5", 806, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
|
||||
|
|
@ -194,14 +191,14 @@ static const unsigned int r8a77995_crit_mod_clks[] __initconst = {
|
|||
* MD19 EXTAL (MHz) PLL0 PLL1 PLL3
|
||||
*--------------------------------------------------------------------
|
||||
* 0 48 x 1 x250/4 x100/3 x100/3
|
||||
* 1 48 x 1 x250/4 x100/3 x116/6
|
||||
* 1 48 x 1 x250/4 x100/3 x58/3
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div */
|
||||
{ 1, 100, 3, 100, 3, },
|
||||
{ 1, 100, 3, 116, 6, },
|
||||
{ 1, 100, 3, 58, 3, },
|
||||
};
|
||||
|
||||
static int __init r8a77995_cpg_mssr_init(struct device *dev)
|
||||
|
|
|
|||
|
|
@ -232,16 +232,20 @@ struct sd_clock {
|
|||
* sd_srcfc sd_fc div
|
||||
* stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
|
||||
*-------------------------------------------------------------------
|
||||
* 0 0 0 (1) 1 (4) 4
|
||||
* 0 0 1 (2) 1 (4) 8
|
||||
* 1 0 2 (4) 1 (4) 16
|
||||
* 1 0 3 (8) 1 (4) 32
|
||||
* 0 0 0 (1) 1 (4) 4 : SDR104 / HS200 / HS400 (8 TAP)
|
||||
* 0 0 1 (2) 1 (4) 8 : SDR50
|
||||
* 1 0 2 (4) 1 (4) 16 : HS / SDR25
|
||||
* 1 0 3 (8) 1 (4) 32 : NS / SDR12
|
||||
* 1 0 4 (16) 1 (4) 64
|
||||
* 0 0 0 (1) 0 (2) 2
|
||||
* 0 0 1 (2) 0 (2) 4
|
||||
* 0 0 1 (2) 0 (2) 4 : SDR104 / HS200 / HS400 (4 TAP)
|
||||
* 1 0 2 (4) 0 (2) 8
|
||||
* 1 0 3 (8) 0 (2) 16
|
||||
* 1 0 4 (16) 0 (2) 32
|
||||
*
|
||||
* NOTE: There is a quirk option to ignore the first row of the dividers
|
||||
* table when searching for suitable settings. This is because HS400 on
|
||||
* early ES versions of H3 and M3-W requires a specific setting to work.
|
||||
*/
|
||||
static const struct sd_div_table cpg_sd_div_table[] = {
|
||||
/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
|
||||
|
|
@ -352,6 +356,12 @@ static const struct clk_ops cpg_sd_clock_ops = {
|
|||
.set_rate = cpg_sd_clock_set_rate,
|
||||
};
|
||||
|
||||
static u32 cpg_quirks __initdata;
|
||||
|
||||
#define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */
|
||||
#define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
|
||||
#define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */
|
||||
|
||||
static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
|
||||
void __iomem *base, const char *parent_name,
|
||||
struct raw_notifier_head *notifiers)
|
||||
|
|
@ -360,7 +370,7 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
|
|||
struct sd_clock *clock;
|
||||
struct clk *clk;
|
||||
unsigned int i;
|
||||
u32 sd_fc;
|
||||
u32 val;
|
||||
|
||||
clock = kzalloc(sizeof(*clock), GFP_KERNEL);
|
||||
if (!clock)
|
||||
|
|
@ -377,17 +387,14 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
|
|||
clock->div_table = cpg_sd_div_table;
|
||||
clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
|
||||
|
||||
sd_fc = readl(clock->csn.reg) & CPG_SD_FC_MASK;
|
||||
for (i = 0; i < clock->div_num; i++)
|
||||
if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
|
||||
break;
|
||||
|
||||
if (WARN_ON(i >= clock->div_num)) {
|
||||
kfree(clock);
|
||||
return ERR_PTR(-EINVAL);
|
||||
if (cpg_quirks & SD_SKIP_FIRST) {
|
||||
clock->div_table++;
|
||||
clock->div_num--;
|
||||
}
|
||||
|
||||
clock->cur_div_idx = i;
|
||||
val = readl(clock->csn.reg) & ~CPG_SD_FC_MASK;
|
||||
val |= CPG_SD_STP_MASK | (clock->div_table[0].val & CPG_SD_FC_MASK);
|
||||
writel(val, clock->csn.reg);
|
||||
|
||||
clock->div_max = clock->div_table[0].div;
|
||||
clock->div_min = clock->div_max;
|
||||
|
|
@ -412,23 +419,27 @@ free_clock:
|
|||
static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
|
||||
static unsigned int cpg_clk_extalr __initdata;
|
||||
static u32 cpg_mode __initdata;
|
||||
static u32 cpg_quirks __initdata;
|
||||
|
||||
#define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */
|
||||
#define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
|
||||
|
||||
static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
|
||||
{
|
||||
.soc_id = "r8a7795", .revision = "ES1.0",
|
||||
.data = (void *)(PLL_ERRATA | RCKCR_CKSEL),
|
||||
.data = (void *)(PLL_ERRATA | RCKCR_CKSEL | SD_SKIP_FIRST),
|
||||
},
|
||||
{
|
||||
.soc_id = "r8a7795", .revision = "ES1.*",
|
||||
.data = (void *)RCKCR_CKSEL,
|
||||
.data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
|
||||
},
|
||||
{
|
||||
.soc_id = "r8a7795", .revision = "ES2.0",
|
||||
.data = (void *)SD_SKIP_FIRST,
|
||||
},
|
||||
{
|
||||
.soc_id = "r8a7796", .revision = "ES1.0",
|
||||
.data = (void *)RCKCR_CKSEL,
|
||||
.data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
|
||||
},
|
||||
{
|
||||
.soc_id = "r8a7796", .revision = "ES1.1",
|
||||
.data = (void *)SD_SKIP_FIRST,
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
|
|
|||
|
|
@ -362,8 +362,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
|
|||
RK2928_CLKGATE_CON(2), 5, GFLAGS),
|
||||
MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(21), 4, 1, MFLAGS),
|
||||
GATE(0, "sclk_mac_lbtest", "sclk_macref",
|
||||
RK2928_CLKGATE_CON(2), 12, 0, GFLAGS),
|
||||
GATE(0, "sclk_mac_lbtest", "sclk_macref", 0,
|
||||
RK2928_CLKGATE_CON(2), 12, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
|
||||
RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
|
||||
|
|
@ -382,7 +382,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
|
|||
COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
|
||||
RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(0), 13, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pll", CLK_SET_RATE_PARENT,
|
||||
COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pre", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(9), 0,
|
||||
RK2928_CLKGATE_CON(0), 14, GFLAGS,
|
||||
&common_spdif_fracmux),
|
||||
|
|
@ -391,8 +391,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
|
|||
* Clock-Architecture Diagram 4
|
||||
*/
|
||||
|
||||
GATE(SCLK_SMC, "sclk_smc", "hclk_peri",
|
||||
RK2928_CLKGATE_CON(2), 4, 0, GFLAGS),
|
||||
GATE(SCLK_SMC, "sclk_smc", "hclk_peri", 0,
|
||||
RK2928_CLKGATE_CON(2), 4, GFLAGS),
|
||||
|
||||
COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0,
|
||||
RK2928_CLKSEL_CON(25), 0, 7, DFLAGS,
|
||||
|
|
@ -757,7 +757,8 @@ static const char *const rk3188_critical_clocks[] __initconst = {
|
|||
"hclk_peri",
|
||||
"pclk_cpu",
|
||||
"pclk_peri",
|
||||
"hclk_cpubus"
|
||||
"hclk_cpubus",
|
||||
"hclk_vio_bus",
|
||||
};
|
||||
|
||||
static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np)
|
||||
|
|
|
|||
|
|
@ -392,7 +392,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
|
|||
RK3328_CLKGATE_CON(1), 5, GFLAGS,
|
||||
&rk3328_i2s1_fracmux),
|
||||
GATE(SCLK_I2S1, "clk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKGATE_CON(0), 6, GFLAGS),
|
||||
RK3328_CLKGATE_CON(1), 6, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_I2S1_OUT, "i2s1_out", mux_i2s1out_p, 0,
|
||||
RK3328_CLKSEL_CON(8), 12, 1, MFLAGS,
|
||||
RK3328_CLKGATE_CON(1), 7, GFLAGS),
|
||||
|
|
@ -804,7 +804,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
|
|||
GATE(PCLK_USB3_GRF, "pclk_usb3_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 2, GFLAGS),
|
||||
GATE(PCLK_USB2_GRF, "pclk_usb2_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 14, GFLAGS),
|
||||
GATE(0, "pclk_ddrphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 13, GFLAGS),
|
||||
GATE(0, "pclk_acodecphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 5, GFLAGS),
|
||||
GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(17), 5, GFLAGS),
|
||||
GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 7, GFLAGS),
|
||||
GATE(0, "pclk_vdacphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 8, GFLAGS),
|
||||
GATE(0, "pclk_phy_niu", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(15), 15, GFLAGS),
|
||||
|
|
|
|||
|
|
@ -6,6 +6,11 @@ config SUNXI_CCU
|
|||
|
||||
if SUNXI_CCU
|
||||
|
||||
config SUNIV_F1C100S_CCU
|
||||
bool "Support for the Allwinner newer F1C100s CCU"
|
||||
default MACH_SUNIV
|
||||
depends on MACH_SUNIV || COMPILE_TEST
|
||||
|
||||
config SUN50I_A64_CCU
|
||||
bool "Support for the Allwinner A64 CCU"
|
||||
default ARM64 && ARCH_SUNXI
|
||||
|
|
@ -63,6 +68,7 @@ config SUN8I_V3S_CCU
|
|||
|
||||
config SUN8I_DE2_CCU
|
||||
bool "Support for the Allwinner SoCs DE2 CCU"
|
||||
default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
|
||||
|
||||
config SUN8I_R40_CCU
|
||||
bool "Support for the Allwinner R40 CCU"
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@ obj-y += ccu_nm.o
|
|||
obj-y += ccu_mp.o
|
||||
|
||||
# SoC support
|
||||
obj-$(CONFIG_SUNIV_F1C100S_CCU) += ccu-suniv-f1c100s.o
|
||||
obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
|
||||
obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o
|
||||
obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o
|
||||
|
|
|
|||
|
|
@ -51,18 +51,29 @@ static struct ccu_nkmp pll_cpux_clk = {
|
|||
* the base (2x, 4x and 8x), and one variable divider (the one true
|
||||
* pll audio).
|
||||
*
|
||||
* We don't have any need for the variable divider for now, so we just
|
||||
* hardcode it to match with the clock names
|
||||
* With sigma-delta modulation for fractional-N on the audio PLL,
|
||||
* we have to use specific dividers. This means the variable divider
|
||||
* can no longer be used, as the audio codec requests the exact clock
|
||||
* rates we support through this mechanism. So we now hard code the
|
||||
* variable divider to 1. This means the clock rates will no longer
|
||||
* match the clock names.
|
||||
*/
|
||||
#define SUN50I_A64_PLL_AUDIO_REG 0x008
|
||||
|
||||
static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
|
||||
"osc24M", 0x008,
|
||||
8, 7, /* N */
|
||||
0, 5, /* M */
|
||||
BIT(31), /* gate */
|
||||
BIT(28), /* lock */
|
||||
CLK_SET_RATE_UNGATE);
|
||||
static struct ccu_sdm_setting pll_audio_sdm_table[] = {
|
||||
{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
|
||||
{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
|
||||
};
|
||||
|
||||
static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
|
||||
"osc24M", 0x008,
|
||||
8, 7, /* N */
|
||||
0, 5, /* M */
|
||||
pll_audio_sdm_table, BIT(24),
|
||||
0x284, BIT(31),
|
||||
BIT(31), /* gate */
|
||||
BIT(28), /* lock */
|
||||
CLK_SET_RATE_UNGATE);
|
||||
|
||||
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
|
||||
"osc24M", 0x010,
|
||||
|
|
@ -162,7 +173,12 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
|
|||
#define SUN50I_A64_PLL_MIPI_REG 0x040
|
||||
|
||||
static struct ccu_nkm pll_mipi_clk = {
|
||||
.enable = BIT(31),
|
||||
/*
|
||||
* The bit 23 and 22 are called "LDO{1,2}_EN" on the SoC's
|
||||
* user manual, and by experiments the PLL doesn't work without
|
||||
* these bits toggled.
|
||||
*/
|
||||
.enable = BIT(31) | BIT(23) | BIT(22),
|
||||
.lock = BIT(28),
|
||||
.n = _SUNXI_CCU_MULT(8, 4),
|
||||
.k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
|
||||
|
|
@ -554,7 +570,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
|
|||
0x134, 0, 5, 8, 3, BIT(15), 0);
|
||||
|
||||
static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
|
||||
0x13c, 16, 3, BIT(31), 0);
|
||||
0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
|
||||
|
||||
static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
|
||||
0x140, BIT(31), CLK_SET_RATE_PARENT);
|
||||
|
|
@ -581,7 +597,7 @@ static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
|
|||
static const u8 dsi_dphy_table[] = { 0, 2, };
|
||||
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
|
||||
dsi_dphy_parents, dsi_dphy_table,
|
||||
0x168, 0, 4, 8, 2, BIT(31), CLK_SET_RATE_PARENT);
|
||||
0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);
|
||||
|
||||
static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
|
||||
0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
|
||||
|
|
@ -589,9 +605,9 @@ static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
|
|||
/* Fixed Factor clocks */
|
||||
static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0);
|
||||
|
||||
/* We hardcode the divider to 4 for now */
|
||||
/* We hardcode the divider to 1 for now */
|
||||
static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
|
||||
"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
|
||||
"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
|
||||
static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
|
||||
"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
|
||||
static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
|
||||
|
|
@ -911,10 +927,10 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
|
|||
if (IS_ERR(reg))
|
||||
return PTR_ERR(reg);
|
||||
|
||||
/* Force the PLL-Audio-1x divider to 4 */
|
||||
/* Force the PLL-Audio-1x divider to 1 */
|
||||
val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);
|
||||
val &= ~GENMASK(19, 16);
|
||||
writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
|
||||
writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
|
||||
|
||||
writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
|
||||
|
||||
|
|
|
|||
|
|
@ -120,6 +120,8 @@ static struct ccu_nm pll_video0_clk = {
|
|||
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
|
||||
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
|
||||
.fixed_post_div = 4,
|
||||
.min_rate = 288000000,
|
||||
.max_rate = 2400000000UL,
|
||||
.common = {
|
||||
.reg = 0x040,
|
||||
.features = CCU_FEATURE_FIXED_POSTDIV,
|
||||
|
|
@ -136,6 +138,8 @@ static struct ccu_nm pll_video1_clk = {
|
|||
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
|
||||
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
|
||||
.fixed_post_div = 4,
|
||||
.min_rate = 288000000,
|
||||
.max_rate = 2400000000UL,
|
||||
.common = {
|
||||
.reg = 0x048,
|
||||
.features = CCU_FEATURE_FIXED_POSTDIV,
|
||||
|
|
@ -411,7 +415,7 @@ static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x",
|
|||
static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830,
|
||||
0, 4, /* M */
|
||||
8, 2, /* N */
|
||||
24, 3, /* mux */
|
||||
24, 2, /* mux */
|
||||
BIT(31), /* gate */
|
||||
2, /* post-div */
|
||||
0);
|
||||
|
|
@ -419,7 +423,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830,
|
|||
static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
|
||||
0, 4, /* M */
|
||||
8, 2, /* N */
|
||||
24, 3, /* mux */
|
||||
24, 2, /* mux */
|
||||
BIT(31), /* gate */
|
||||
2, /* post-div */
|
||||
0);
|
||||
|
|
@ -427,7 +431,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
|
|||
static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838,
|
||||
0, 4, /* M */
|
||||
8, 2, /* N */
|
||||
24, 3, /* mux */
|
||||
24, 2, /* mux */
|
||||
BIT(31), /* gate */
|
||||
2, /* post-div */
|
||||
0);
|
||||
|
|
|
|||
|
|
@ -51,18 +51,29 @@ static struct ccu_nkmp pll_cpux_clk = {
|
|||
* the base (2x, 4x and 8x), and one variable divider (the one true
|
||||
* pll audio).
|
||||
*
|
||||
* We don't have any need for the variable divider for now, so we just
|
||||
* hardcode it to match with the clock names
|
||||
* With sigma-delta modulation for fractional-N on the audio PLL,
|
||||
* we have to use specific dividers. This means the variable divider
|
||||
* can no longer be used, as the audio codec requests the exact clock
|
||||
* rates we support through this mechanism. So we now hard code the
|
||||
* variable divider to 1. This means the clock rates will no longer
|
||||
* match the clock names.
|
||||
*/
|
||||
#define SUN8I_A33_PLL_AUDIO_REG 0x008
|
||||
|
||||
static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
|
||||
"osc24M", 0x008,
|
||||
8, 7, /* N */
|
||||
0, 5, /* M */
|
||||
BIT(31), /* gate */
|
||||
BIT(28), /* lock */
|
||||
CLK_SET_RATE_UNGATE);
|
||||
static struct ccu_sdm_setting pll_audio_sdm_table[] = {
|
||||
{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
|
||||
{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
|
||||
};
|
||||
|
||||
static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
|
||||
"osc24M", 0x008,
|
||||
8, 7, /* N */
|
||||
0, 5, /* M */
|
||||
pll_audio_sdm_table, BIT(24),
|
||||
0x284, BIT(31),
|
||||
BIT(31), /* gate */
|
||||
BIT(28), /* lock */
|
||||
CLK_SET_RATE_UNGATE);
|
||||
|
||||
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
|
||||
"osc24M", 0x010,
|
||||
|
|
@ -366,10 +377,10 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
|
|||
static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
|
||||
"pll-audio-2x", "pll-audio" };
|
||||
static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
|
||||
0x0b0, 16, 2, BIT(31), 0);
|
||||
0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
|
||||
|
||||
static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
|
||||
0x0b4, 16, 2, BIT(31), 0);
|
||||
0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
|
||||
|
||||
/* TODO: the parent for most of the USB clocks is not known */
|
||||
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
|
||||
|
|
@ -446,7 +457,7 @@ static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
|
|||
static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
|
||||
0x140, BIT(31), CLK_SET_RATE_PARENT);
|
||||
static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",
|
||||
0x140, BIT(30), 0);
|
||||
0x140, BIT(30), CLK_SET_RATE_PARENT);
|
||||
static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
|
||||
0x144, BIT(31), 0);
|
||||
|
||||
|
|
@ -576,9 +587,9 @@ static struct ccu_common *sun8i_a33_ccu_clks[] = {
|
|||
&ats_clk.common,
|
||||
};
|
||||
|
||||
/* We hardcode the divider to 4 for now */
|
||||
/* We hardcode the divider to 1 for now */
|
||||
static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
|
||||
"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
|
||||
"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
|
||||
static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
|
||||
"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
|
||||
static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
|
||||
|
|
@ -781,10 +792,10 @@ static void __init sun8i_a33_ccu_setup(struct device_node *node)
|
|||
return;
|
||||
}
|
||||
|
||||
/* Force the PLL-Audio-1x divider to 4 */
|
||||
/* Force the PLL-Audio-1x divider to 1 */
|
||||
val = readl(reg + SUN8I_A33_PLL_AUDIO_REG);
|
||||
val &= ~GENMASK(19, 16);
|
||||
writel(val | (3 << 16), reg + SUN8I_A33_PLL_AUDIO_REG);
|
||||
writel(val | (0 << 16), reg + SUN8I_A33_PLL_AUDIO_REG);
|
||||
|
||||
/* Force PLL-MIPI to MIPI mode */
|
||||
val = readl(reg + SUN8I_A33_PLL_MIPI_REG);
|
||||
|
|
|
|||
|
|
@ -31,6 +31,8 @@ static SUNXI_CCU_GATE(bus_mixer1_clk, "bus-mixer1", "bus-de",
|
|||
0x04, BIT(1), 0);
|
||||
static SUNXI_CCU_GATE(bus_wb_clk, "bus-wb", "bus-de",
|
||||
0x04, BIT(2), 0);
|
||||
static SUNXI_CCU_GATE(bus_rot_clk, "bus-rot", "bus-de",
|
||||
0x04, BIT(3), 0);
|
||||
|
||||
static SUNXI_CCU_GATE(mixer0_clk, "mixer0", "mixer0-div",
|
||||
0x00, BIT(0), CLK_SET_RATE_PARENT);
|
||||
|
|
@ -38,6 +40,8 @@ static SUNXI_CCU_GATE(mixer1_clk, "mixer1", "mixer1-div",
|
|||
0x00, BIT(1), CLK_SET_RATE_PARENT);
|
||||
static SUNXI_CCU_GATE(wb_clk, "wb", "wb-div",
|
||||
0x00, BIT(2), CLK_SET_RATE_PARENT);
|
||||
static SUNXI_CCU_GATE(rot_clk, "rot", "rot-div",
|
||||
0x00, BIT(3), CLK_SET_RATE_PARENT);
|
||||
|
||||
static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4,
|
||||
CLK_SET_RATE_PARENT);
|
||||
|
|
@ -45,6 +49,8 @@ static SUNXI_CCU_M(mixer1_div_clk, "mixer1-div", "de", 0x0c, 4, 4,
|
|||
CLK_SET_RATE_PARENT);
|
||||
static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4,
|
||||
CLK_SET_RATE_PARENT);
|
||||
static SUNXI_CCU_M(rot_div_clk, "rot-div", "de", 0x0c, 0x0c, 4,
|
||||
CLK_SET_RATE_PARENT);
|
||||
|
||||
static SUNXI_CCU_M(mixer0_div_a83_clk, "mixer0-div", "pll-de", 0x0c, 0, 4,
|
||||
CLK_SET_RATE_PARENT);
|
||||
|
|
@ -53,6 +59,24 @@ static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4,
|
|||
static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4,
|
||||
CLK_SET_RATE_PARENT);
|
||||
|
||||
static struct ccu_common *sun50i_h6_de3_clks[] = {
|
||||
&mixer0_clk.common,
|
||||
&mixer1_clk.common,
|
||||
&wb_clk.common,
|
||||
|
||||
&bus_mixer0_clk.common,
|
||||
&bus_mixer1_clk.common,
|
||||
&bus_wb_clk.common,
|
||||
|
||||
&mixer0_div_clk.common,
|
||||
&mixer1_div_clk.common,
|
||||
&wb_div_clk.common,
|
||||
|
||||
&bus_rot_clk.common,
|
||||
&rot_clk.common,
|
||||
&rot_div_clk.common,
|
||||
};
|
||||
|
||||
static struct ccu_common *sun8i_a83t_de2_clks[] = {
|
||||
&mixer0_clk.common,
|
||||
&mixer1_clk.common,
|
||||
|
|
@ -106,7 +130,7 @@ static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
|
|||
[CLK_MIXER1_DIV] = &mixer1_div_a83_clk.common.hw,
|
||||
[CLK_WB_DIV] = &wb_div_a83_clk.common.hw,
|
||||
},
|
||||
.num = CLK_NUMBER,
|
||||
.num = CLK_NUMBER_WITHOUT_ROT,
|
||||
};
|
||||
|
||||
static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = {
|
||||
|
|
@ -123,7 +147,7 @@ static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = {
|
|||
[CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw,
|
||||
[CLK_WB_DIV] = &wb_div_clk.common.hw,
|
||||
},
|
||||
.num = CLK_NUMBER,
|
||||
.num = CLK_NUMBER_WITHOUT_ROT,
|
||||
};
|
||||
|
||||
static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = {
|
||||
|
|
@ -137,7 +161,27 @@ static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = {
|
|||
[CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw,
|
||||
[CLK_WB_DIV] = &wb_div_clk.common.hw,
|
||||
},
|
||||
.num = CLK_NUMBER,
|
||||
.num = CLK_NUMBER_WITHOUT_ROT,
|
||||
};
|
||||
|
||||
static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = {
|
||||
.hws = {
|
||||
[CLK_MIXER0] = &mixer0_clk.common.hw,
|
||||
[CLK_MIXER1] = &mixer1_clk.common.hw,
|
||||
[CLK_WB] = &wb_clk.common.hw,
|
||||
[CLK_ROT] = &rot_clk.common.hw,
|
||||
|
||||
[CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,
|
||||
[CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,
|
||||
[CLK_BUS_WB] = &bus_wb_clk.common.hw,
|
||||
[CLK_BUS_ROT] = &bus_rot_clk.common.hw,
|
||||
|
||||
[CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw,
|
||||
[CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw,
|
||||
[CLK_WB_DIV] = &wb_div_clk.common.hw,
|
||||
[CLK_ROT_DIV] = &rot_div_clk.common.hw,
|
||||
},
|
||||
.num = CLK_NUMBER_WITH_ROT,
|
||||
};
|
||||
|
||||
static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
|
||||
|
|
@ -156,6 +200,13 @@ static struct ccu_reset_map sun50i_a64_de2_resets[] = {
|
|||
[RST_WB] = { 0x08, BIT(2) },
|
||||
};
|
||||
|
||||
static struct ccu_reset_map sun50i_h6_de3_resets[] = {
|
||||
[RST_MIXER0] = { 0x08, BIT(0) },
|
||||
[RST_MIXER1] = { 0x08, BIT(1) },
|
||||
[RST_WB] = { 0x08, BIT(2) },
|
||||
[RST_ROT] = { 0x08, BIT(3) },
|
||||
};
|
||||
|
||||
static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
|
||||
.ccu_clks = sun8i_a83t_de2_clks,
|
||||
.num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks),
|
||||
|
|
@ -186,6 +237,16 @@ static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
|
|||
.num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
|
||||
};
|
||||
|
||||
static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc = {
|
||||
.ccu_clks = sun50i_h6_de3_clks,
|
||||
.num_ccu_clks = ARRAY_SIZE(sun50i_h6_de3_clks),
|
||||
|
||||
.hw_clks = &sun50i_h6_de3_hw_clks,
|
||||
|
||||
.resets = sun50i_h6_de3_resets,
|
||||
.num_resets = ARRAY_SIZE(sun50i_h6_de3_resets),
|
||||
};
|
||||
|
||||
static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
|
||||
.ccu_clks = sun8i_v3s_de2_clks,
|
||||
.num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks),
|
||||
|
|
@ -296,6 +357,10 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
|
|||
.compatible = "allwinner,sun50i-h5-de2-clk",
|
||||
.data = &sun50i_a64_de2_clk_desc,
|
||||
},
|
||||
{
|
||||
.compatible = "allwinner,sun50i-h6-de3-clk",
|
||||
.data = &sun50i_h6_de3_clk_desc,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -22,7 +22,9 @@
|
|||
#define CLK_MIXER0_DIV 3
|
||||
#define CLK_MIXER1_DIV 4
|
||||
#define CLK_WB_DIV 5
|
||||
#define CLK_ROT_DIV 11
|
||||
|
||||
#define CLK_NUMBER (CLK_WB + 1)
|
||||
#define CLK_NUMBER_WITH_ROT (CLK_ROT_DIV + 1)
|
||||
#define CLK_NUMBER_WITHOUT_ROT (CLK_WB + 1)
|
||||
|
||||
#endif /* _CCU_SUN8I_DE2_H_ */
|
||||
|
|
|
|||
|
|
@ -476,12 +476,12 @@ static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
|
|||
static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
|
||||
0x134, 16, 4, 24, 3, BIT(31), 0);
|
||||
|
||||
static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", "pll-periph0" };
|
||||
static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", "pll-periph1" };
|
||||
static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
|
||||
0x134, 0, 5, 8, 3, BIT(15), 0);
|
||||
|
||||
static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
|
||||
0x13c, 16, 3, BIT(31), 0);
|
||||
0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
|
||||
|
||||
static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
|
||||
0x140, BIT(31), CLK_SET_RATE_PARENT);
|
||||
|
|
|
|||
|
|
@ -1284,6 +1284,9 @@ static struct regmap_config sun8i_r40_ccu_regmap_config = {
|
|||
.writeable_reg = sun8i_r40_ccu_regmap_accessible_reg,
|
||||
};
|
||||
|
||||
#define SUN8I_R40_SYS_32K_CLK_REG 0x310
|
||||
#define SUN8I_R40_SYS_32K_CLK_KEY (0x16AA << 16)
|
||||
|
||||
static int sun8i_r40_ccu_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
|
|
@ -1312,6 +1315,14 @@ static int sun8i_r40_ccu_probe(struct platform_device *pdev)
|
|||
val &= ~GENMASK(25, 20);
|
||||
writel(val, reg + SUN8I_R40_USB_CLK_REG);
|
||||
|
||||
/*
|
||||
* Force SYS 32k (otherwise known as LOSC throughout the CCU)
|
||||
* clock parent to LOSC output from RTC module instead of the
|
||||
* CCU's internal RC oscillator divided output.
|
||||
*/
|
||||
writel(SUN8I_R40_SYS_32K_CLK_KEY | BIT(8),
|
||||
reg + SUN8I_R40_SYS_32K_CLK_REG);
|
||||
|
||||
regmap = devm_regmap_init_mmio(&pdev->dev, reg,
|
||||
&sun8i_r40_ccu_regmap_config);
|
||||
if (IS_ERR(regmap))
|
||||
|
|
|
|||
|
|
@ -0,0 +1,541 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.io>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include "ccu_common.h"
|
||||
#include "ccu_reset.h"
|
||||
|
||||
#include "ccu_div.h"
|
||||
#include "ccu_gate.h"
|
||||
#include "ccu_mp.h"
|
||||
#include "ccu_mult.h"
|
||||
#include "ccu_nk.h"
|
||||
#include "ccu_nkm.h"
|
||||
#include "ccu_nkmp.h"
|
||||
#include "ccu_nm.h"
|
||||
#include "ccu_phase.h"
|
||||
|
||||
#include "ccu-suniv-f1c100s.h"
|
||||
|
||||
static struct ccu_nkmp pll_cpu_clk = {
|
||||
.enable = BIT(31),
|
||||
.lock = BIT(28),
|
||||
|
||||
.n = _SUNXI_CCU_MULT(8, 5),
|
||||
.k = _SUNXI_CCU_MULT(4, 2),
|
||||
.m = _SUNXI_CCU_DIV(0, 2),
|
||||
/* MAX is guessed by the BSP table */
|
||||
.p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
|
||||
|
||||
.common = {
|
||||
.reg = 0x000,
|
||||
.hw.init = CLK_HW_INIT("pll-cpu", "osc24M",
|
||||
&ccu_nkmp_ops,
|
||||
CLK_SET_RATE_UNGATE),
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
|
||||
* the base (2x, 4x and 8x), and one variable divider (the one true
|
||||
* pll audio).
|
||||
*
|
||||
* We don't have any need for the variable divider for now, so we just
|
||||
* hardcode it to match with the clock names
|
||||
*/
|
||||
#define SUNIV_PLL_AUDIO_REG 0x008
|
||||
|
||||
static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
|
||||
"osc24M", 0x008,
|
||||
8, 7, /* N */
|
||||
0, 5, /* M */
|
||||
BIT(31), /* gate */
|
||||
BIT(28), /* lock */
|
||||
CLK_SET_RATE_UNGATE);
|
||||
|
||||
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
|
||||
"osc24M", 0x010,
|
||||
8, 7, /* N */
|
||||
0, 4, /* M */
|
||||
BIT(24), /* frac enable */
|
||||
BIT(25), /* frac select */
|
||||
270000000, /* frac rate 0 */
|
||||
297000000, /* frac rate 1 */
|
||||
BIT(31), /* gate */
|
||||
BIT(28), /* lock */
|
||||
CLK_SET_RATE_UNGATE);
|
||||
|
||||
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
|
||||
"osc24M", 0x018,
|
||||
8, 7, /* N */
|
||||
0, 4, /* M */
|
||||
BIT(24), /* frac enable */
|
||||
BIT(25), /* frac select */
|
||||
270000000, /* frac rate 0 */
|
||||
297000000, /* frac rate 1 */
|
||||
BIT(31), /* gate */
|
||||
BIT(28), /* lock */
|
||||
CLK_SET_RATE_UNGATE);
|
||||
|
||||
static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr",
|
||||
"osc24M", 0x020,
|
||||
8, 5, /* N */
|
||||
4, 2, /* K */
|
||||
0, 2, /* M */
|
||||
BIT(31), /* gate */
|
||||
BIT(28), /* lock */
|
||||
CLK_IS_CRITICAL);
|
||||
|
||||
static struct ccu_nk pll_periph_clk = {
|
||||
.enable = BIT(31),
|
||||
.lock = BIT(28),
|
||||
.k = _SUNXI_CCU_MULT(4, 2),
|
||||
.n = _SUNXI_CCU_MULT(8, 5),
|
||||
.common = {
|
||||
.reg = 0x028,
|
||||
.hw.init = CLK_HW_INIT("pll-periph", "osc24M",
|
||||
&ccu_nk_ops, 0),
|
||||
},
|
||||
};
|
||||
|
||||
static const char * const cpu_parents[] = { "osc32k", "osc24M",
|
||||
"pll-cpu", "pll-cpu" };
|
||||
static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
|
||||
0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
|
||||
|
||||
static const char * const ahb_parents[] = { "osc32k", "osc24M",
|
||||
"cpu", "pll-periph" };
|
||||
static const struct ccu_mux_var_prediv ahb_predivs[] = {
|
||||
{ .index = 3, .shift = 6, .width = 2 },
|
||||
};
|
||||
static struct ccu_div ahb_clk = {
|
||||
.div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
|
||||
|
||||
.mux = {
|
||||
.shift = 12,
|
||||
.width = 2,
|
||||
|
||||
.var_predivs = ahb_predivs,
|
||||
.n_var_predivs = ARRAY_SIZE(ahb_predivs),
|
||||
},
|
||||
|
||||
.common = {
|
||||
.reg = 0x054,
|
||||
.features = CCU_FEATURE_VARIABLE_PREDIV,
|
||||
.hw.init = CLK_HW_INIT_PARENTS("ahb",
|
||||
ahb_parents,
|
||||
&ccu_div_ops,
|
||||
0),
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_div_table apb_div_table[] = {
|
||||
{ .val = 0, .div = 2 },
|
||||
{ .val = 1, .div = 2 },
|
||||
{ .val = 2, .div = 4 },
|
||||
{ .val = 3, .div = 8 },
|
||||
{ /* Sentinel */ },
|
||||
};
|
||||
static SUNXI_CCU_DIV_TABLE(apb_clk, "apb", "ahb",
|
||||
0x054, 8, 2, apb_div_table, 0);
|
||||
|
||||
static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb",
|
||||
0x060, BIT(6), 0);
|
||||
static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb",
|
||||
0x060, BIT(8), 0);
|
||||
static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb",
|
||||
0x060, BIT(9), 0);
|
||||
static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb",
|
||||
0x060, BIT(14), 0);
|
||||
static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb",
|
||||
0x060, BIT(20), 0);
|
||||
static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb",
|
||||
0x060, BIT(21), 0);
|
||||
static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb",
|
||||
0x060, BIT(24), 0);
|
||||
|
||||
static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb",
|
||||
0x064, BIT(0), 0);
|
||||
static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb",
|
||||
0x064, BIT(4), 0);
|
||||
static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb",
|
||||
0x064, BIT(5), 0);
|
||||
static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb",
|
||||
0x064, BIT(8), 0);
|
||||
static SUNXI_CCU_GATE(bus_tvd_clk, "bus-tvd", "ahb",
|
||||
0x064, BIT(9), 0);
|
||||
static SUNXI_CCU_GATE(bus_tve_clk, "bus-tve", "ahb",
|
||||
0x064, BIT(10), 0);
|
||||
static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb",
|
||||
0x064, BIT(12), 0);
|
||||
static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb",
|
||||
0x064, BIT(14), 0);
|
||||
|
||||
static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb",
|
||||
0x068, BIT(0), 0);
|
||||
static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb",
|
||||
0x068, BIT(1), 0);
|
||||
static SUNXI_CCU_GATE(bus_ir_clk, "bus-ir", "apb",
|
||||
0x068, BIT(2), 0);
|
||||
static SUNXI_CCU_GATE(bus_rsb_clk, "bus-rsb", "apb",
|
||||
0x068, BIT(3), 0);
|
||||
static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb",
|
||||
0x068, BIT(12), 0);
|
||||
static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb",
|
||||
0x068, BIT(16), 0);
|
||||
static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb",
|
||||
0x068, BIT(17), 0);
|
||||
static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb",
|
||||
0x068, BIT(18), 0);
|
||||
static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb",
|
||||
0x068, BIT(19), 0);
|
||||
static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb",
|
||||
0x068, BIT(20), 0);
|
||||
static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb",
|
||||
0x068, BIT(21), 0);
|
||||
static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb",
|
||||
0x068, BIT(22), 0);
|
||||
|
||||
static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
|
||||
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
|
||||
0, 4, /* M */
|
||||
16, 2, /* P */
|
||||
24, 2, /* mux */
|
||||
BIT(31), /* gate */
|
||||
0);
|
||||
|
||||
static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
|
||||
0x088, 20, 3, 0);
|
||||
static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
|
||||
0x088, 8, 3, 0);
|
||||
|
||||
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
|
||||
0, 4, /* M */
|
||||
16, 2, /* P */
|
||||
24, 2, /* mux */
|
||||
BIT(31), /* gate */
|
||||
0);
|
||||
|
||||
static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
|
||||
0x08c, 20, 3, 0);
|
||||
static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
|
||||
0x08c, 8, 3, 0);
|
||||
|
||||
static const char * const i2s_spdif_parents[] = { "pll-audio-8x",
|
||||
"pll-audio-4x",
|
||||
"pll-audio-2x",
|
||||
"pll-audio" };
|
||||
|
||||
static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_spdif_parents,
|
||||
0x0b0, 16, 2, BIT(31), 0);
|
||||
|
||||
static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents,
|
||||
0x0b4, 16, 2, BIT(31), 0);
|
||||
|
||||
/* The BSP header file has a CIR_CFG, but no mod clock uses this definition */
|
||||
|
||||
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
|
||||
0x0cc, BIT(8), 0);
|
||||
|
||||
static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
|
||||
0x100, BIT(0), 0);
|
||||
static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr",
|
||||
0x100, BIT(1), 0);
|
||||
static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace",
|
||||
"pll-ddr", 0x100, BIT(2), 0);
|
||||
static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "pll-ddr",
|
||||
0x100, BIT(3), 0);
|
||||
static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr",
|
||||
0x100, BIT(24), 0);
|
||||
static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr",
|
||||
0x100, BIT(26), 0);
|
||||
|
||||
static const char * const de_parents[] = { "pll-video", "pll-periph" };
|
||||
static const u8 de_table[] = { 0, 2, };
|
||||
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
|
||||
de_parents, de_table,
|
||||
0x104, 0, 4, 24, 3, BIT(31), 0);
|
||||
|
||||
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
|
||||
de_parents, de_table,
|
||||
0x10c, 0, 4, 24, 3, BIT(31), 0);
|
||||
|
||||
static const char * const tcon_parents[] = { "pll-video", "pll-video-2x" };
|
||||
static const u8 tcon_table[] = { 0, 2, };
|
||||
static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon_clk, "tcon",
|
||||
tcon_parents, tcon_table,
|
||||
0x118, 24, 3, BIT(31),
|
||||
CLK_SET_RATE_PARENT);
|
||||
|
||||
static const char * const deinterlace_parents[] = { "pll-video",
|
||||
"pll-video-2x" };
|
||||
static const u8 deinterlace_table[] = { 0, 2, };
|
||||
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(deinterlace_clk, "deinterlace",
|
||||
deinterlace_parents, deinterlace_table,
|
||||
0x11c, 0, 4, 24, 3, BIT(31), 0);
|
||||
|
||||
static const char * const tve_clk2_parents[] = { "pll-video",
|
||||
"pll-video-2x" };
|
||||
static const u8 tve_clk2_table[] = { 0, 2, };
|
||||
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(tve_clk2_clk, "tve-clk2",
|
||||
tve_clk2_parents, tve_clk2_table,
|
||||
0x120, 0, 4, 24, 3, BIT(31), 0);
|
||||
static SUNXI_CCU_M_WITH_GATE(tve_clk1_clk, "tve-clk1", "tve-clk2",
|
||||
0x120, 8, 1, BIT(15), 0);
|
||||
|
||||
static const char * const tvd_parents[] = { "pll-video", "osc24M",
|
||||
"pll-video-2x" };
|
||||
static SUNXI_CCU_M_WITH_MUX_GATE(tvd_clk, "tvd", tvd_parents,
|
||||
0x124, 0, 4, 24, 3, BIT(31), 0);
|
||||
|
||||
static const char * const csi_parents[] = { "pll-video", "osc24M" };
|
||||
static const u8 csi_table[] = { 0, 5, };
|
||||
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi", csi_parents, csi_table,
|
||||
0x120, 0, 4, 8, 3, BIT(15), 0);
|
||||
|
||||
/*
|
||||
* TODO: BSP says the parent is pll-audio, however common sense and experience
|
||||
* told us it should be pll-ve. pll-ve is totally not used in BSP code.
|
||||
*/
|
||||
static SUNXI_CCU_GATE(ve_clk, "ve", "pll-audio", 0x13c, BIT(31), 0);
|
||||
|
||||
static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio", 0x140, BIT(31), 0);
|
||||
|
||||
static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0);
|
||||
|
||||
static struct ccu_common *suniv_ccu_clks[] = {
|
||||
&pll_cpu_clk.common,
|
||||
&pll_audio_base_clk.common,
|
||||
&pll_video_clk.common,
|
||||
&pll_ve_clk.common,
|
||||
&pll_ddr0_clk.common,
|
||||
&pll_periph_clk.common,
|
||||
&cpu_clk.common,
|
||||
&ahb_clk.common,
|
||||
&apb_clk.common,
|
||||
&bus_dma_clk.common,
|
||||
&bus_mmc0_clk.common,
|
||||
&bus_mmc1_clk.common,
|
||||
&bus_dram_clk.common,
|
||||
&bus_spi0_clk.common,
|
||||
&bus_spi1_clk.common,
|
||||
&bus_otg_clk.common,
|
||||
&bus_ve_clk.common,
|
||||
&bus_lcd_clk.common,
|
||||
&bus_deinterlace_clk.common,
|
||||
&bus_csi_clk.common,
|
||||
&bus_tve_clk.common,
|
||||
&bus_tvd_clk.common,
|
||||
&bus_de_be_clk.common,
|
||||
&bus_de_fe_clk.common,
|
||||
&bus_codec_clk.common,
|
||||
&bus_spdif_clk.common,
|
||||
&bus_ir_clk.common,
|
||||
&bus_rsb_clk.common,
|
||||
&bus_i2s0_clk.common,
|
||||
&bus_i2c0_clk.common,
|
||||
&bus_i2c1_clk.common,
|
||||
&bus_i2c2_clk.common,
|
||||
&bus_pio_clk.common,
|
||||
&bus_uart0_clk.common,
|
||||
&bus_uart1_clk.common,
|
||||
&bus_uart2_clk.common,
|
||||
&mmc0_clk.common,
|
||||
&mmc0_sample_clk.common,
|
||||
&mmc0_output_clk.common,
|
||||
&mmc1_clk.common,
|
||||
&mmc1_sample_clk.common,
|
||||
&mmc1_output_clk.common,
|
||||
&i2s_clk.common,
|
||||
&spdif_clk.common,
|
||||
&usb_phy0_clk.common,
|
||||
&dram_ve_clk.common,
|
||||
&dram_csi_clk.common,
|
||||
&dram_deinterlace_clk.common,
|
||||
&dram_tvd_clk.common,
|
||||
&dram_de_fe_clk.common,
|
||||
&dram_de_be_clk.common,
|
||||
&de_be_clk.common,
|
||||
&de_fe_clk.common,
|
||||
&tcon_clk.common,
|
||||
&deinterlace_clk.common,
|
||||
&tve_clk2_clk.common,
|
||||
&tve_clk1_clk.common,
|
||||
&tvd_clk.common,
|
||||
&csi_clk.common,
|
||||
&ve_clk.common,
|
||||
&codec_clk.common,
|
||||
&avs_clk.common,
|
||||
};
|
||||
|
||||
static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
|
||||
"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
|
||||
static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
|
||||
"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
|
||||
static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
|
||||
"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
|
||||
static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
|
||||
"pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
|
||||
static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x",
|
||||
"pll-video", 1, 2, 0);
|
||||
|
||||
static struct clk_hw_onecell_data suniv_hw_clks = {
|
||||
.hws = {
|
||||
[CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
|
||||
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
|
||||
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
|
||||
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
|
||||
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
|
||||
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
|
||||
[CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
|
||||
[CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw,
|
||||
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
|
||||
[CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
|
||||
[CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
|
||||
[CLK_CPU] = &cpu_clk.common.hw,
|
||||
[CLK_AHB] = &ahb_clk.common.hw,
|
||||
[CLK_APB] = &apb_clk.common.hw,
|
||||
[CLK_BUS_DMA] = &bus_dma_clk.common.hw,
|
||||
[CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
|
||||
[CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
|
||||
[CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
|
||||
[CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
|
||||
[CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
|
||||
[CLK_BUS_OTG] = &bus_otg_clk.common.hw,
|
||||
[CLK_BUS_VE] = &bus_ve_clk.common.hw,
|
||||
[CLK_BUS_LCD] = &bus_lcd_clk.common.hw,
|
||||
[CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
|
||||
[CLK_BUS_CSI] = &bus_csi_clk.common.hw,
|
||||
[CLK_BUS_TVD] = &bus_tvd_clk.common.hw,
|
||||
[CLK_BUS_TVE] = &bus_tve_clk.common.hw,
|
||||
[CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw,
|
||||
[CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw,
|
||||
[CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
|
||||
[CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
|
||||
[CLK_BUS_IR] = &bus_ir_clk.common.hw,
|
||||
[CLK_BUS_RSB] = &bus_rsb_clk.common.hw,
|
||||
[CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
|
||||
[CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
|
||||
[CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
|
||||
[CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
|
||||
[CLK_BUS_PIO] = &bus_pio_clk.common.hw,
|
||||
[CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
|
||||
[CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
|
||||
[CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
|
||||
[CLK_MMC0] = &mmc0_clk.common.hw,
|
||||
[CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
|
||||
[CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
|
||||
[CLK_MMC1] = &mmc1_clk.common.hw,
|
||||
[CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
|
||||
[CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
|
||||
[CLK_I2S] = &i2s_clk.common.hw,
|
||||
[CLK_SPDIF] = &spdif_clk.common.hw,
|
||||
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
|
||||
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
|
||||
[CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
|
||||
[CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
|
||||
[CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
|
||||
[CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
|
||||
[CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
|
||||
[CLK_DE_BE] = &de_be_clk.common.hw,
|
||||
[CLK_DE_FE] = &de_fe_clk.common.hw,
|
||||
[CLK_TCON] = &tcon_clk.common.hw,
|
||||
[CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
|
||||
[CLK_TVE2_CLK] = &tve_clk2_clk.common.hw,
|
||||
[CLK_TVE1_CLK] = &tve_clk1_clk.common.hw,
|
||||
[CLK_TVD] = &tvd_clk.common.hw,
|
||||
[CLK_CSI] = &csi_clk.common.hw,
|
||||
[CLK_VE] = &ve_clk.common.hw,
|
||||
[CLK_CODEC] = &codec_clk.common.hw,
|
||||
[CLK_AVS] = &avs_clk.common.hw,
|
||||
},
|
||||
.num = CLK_NUMBER,
|
||||
};
|
||||
|
||||
static struct ccu_reset_map suniv_ccu_resets[] = {
|
||||
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
|
||||
|
||||
[RST_BUS_DMA] = { 0x2c0, BIT(6) },
|
||||
[RST_BUS_MMC0] = { 0x2c0, BIT(8) },
|
||||
[RST_BUS_MMC1] = { 0x2c0, BIT(9) },
|
||||
[RST_BUS_DRAM] = { 0x2c0, BIT(14) },
|
||||
[RST_BUS_SPI0] = { 0x2c0, BIT(20) },
|
||||
[RST_BUS_SPI1] = { 0x2c0, BIT(21) },
|
||||
[RST_BUS_OTG] = { 0x2c0, BIT(24) },
|
||||
[RST_BUS_VE] = { 0x2c4, BIT(0) },
|
||||
[RST_BUS_LCD] = { 0x2c4, BIT(4) },
|
||||
[RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
|
||||
[RST_BUS_CSI] = { 0x2c4, BIT(8) },
|
||||
[RST_BUS_TVD] = { 0x2c4, BIT(9) },
|
||||
[RST_BUS_TVE] = { 0x2c4, BIT(10) },
|
||||
[RST_BUS_DE_BE] = { 0x2c4, BIT(12) },
|
||||
[RST_BUS_DE_FE] = { 0x2c4, BIT(14) },
|
||||
[RST_BUS_CODEC] = { 0x2d0, BIT(0) },
|
||||
[RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
|
||||
[RST_BUS_IR] = { 0x2d0, BIT(2) },
|
||||
[RST_BUS_RSB] = { 0x2d0, BIT(3) },
|
||||
[RST_BUS_I2S0] = { 0x2d0, BIT(12) },
|
||||
[RST_BUS_I2C0] = { 0x2d0, BIT(16) },
|
||||
[RST_BUS_I2C1] = { 0x2d0, BIT(17) },
|
||||
[RST_BUS_I2C2] = { 0x2d0, BIT(18) },
|
||||
[RST_BUS_UART0] = { 0x2d0, BIT(20) },
|
||||
[RST_BUS_UART1] = { 0x2d0, BIT(21) },
|
||||
[RST_BUS_UART2] = { 0x2d0, BIT(22) },
|
||||
};
|
||||
|
||||
static const struct sunxi_ccu_desc suniv_ccu_desc = {
|
||||
.ccu_clks = suniv_ccu_clks,
|
||||
.num_ccu_clks = ARRAY_SIZE(suniv_ccu_clks),
|
||||
|
||||
.hw_clks = &suniv_hw_clks,
|
||||
|
||||
.resets = suniv_ccu_resets,
|
||||
.num_resets = ARRAY_SIZE(suniv_ccu_resets),
|
||||
};
|
||||
|
||||
static struct ccu_pll_nb suniv_pll_cpu_nb = {
|
||||
.common = &pll_cpu_clk.common,
|
||||
/* copy from pll_cpu_clk */
|
||||
.enable = BIT(31),
|
||||
.lock = BIT(28),
|
||||
};
|
||||
|
||||
static struct ccu_mux_nb suniv_cpu_nb = {
|
||||
.common = &cpu_clk.common,
|
||||
.cm = &cpu_clk.mux,
|
||||
.delay_us = 1, /* > 8 clock cycles at 24 MHz */
|
||||
.bypass_index = 1, /* index of 24 MHz oscillator */
|
||||
};
|
||||
|
||||
static void __init suniv_f1c100s_ccu_setup(struct device_node *node)
|
||||
{
|
||||
void __iomem *reg;
|
||||
u32 val;
|
||||
|
||||
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
|
||||
if (IS_ERR(reg)) {
|
||||
pr_err("%pOF: Could not map the clock registers\n", node);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Force the PLL-Audio-1x divider to 4 */
|
||||
val = readl(reg + SUNIV_PLL_AUDIO_REG);
|
||||
val &= ~GENMASK(19, 16);
|
||||
writel(val | (3 << 16), reg + SUNIV_PLL_AUDIO_REG);
|
||||
|
||||
sunxi_ccu_probe(node, reg, &suniv_ccu_desc);
|
||||
|
||||
/* Gate then ungate PLL CPU after any rate changes */
|
||||
ccu_pll_notifier_register(&suniv_pll_cpu_nb);
|
||||
|
||||
/* Reparent CPU during PLL CPU rate changes */
|
||||
ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
|
||||
&suniv_cpu_nb);
|
||||
}
|
||||
CLK_OF_DECLARE(suniv_f1c100s_ccu, "allwinner,suniv-f1c100s-ccu",
|
||||
suniv_f1c100s_ccu_setup);
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _CCU_SUNIV_F1C100S_H_
|
||||
#define _CCU_SUNIV_F1C100S_H_
|
||||
|
||||
#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
|
||||
#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
|
||||
|
||||
#define CLK_PLL_CPU 0
|
||||
#define CLK_PLL_AUDIO_BASE 1
|
||||
#define CLK_PLL_AUDIO 2
|
||||
#define CLK_PLL_AUDIO_2X 3
|
||||
#define CLK_PLL_AUDIO_4X 4
|
||||
#define CLK_PLL_AUDIO_8X 5
|
||||
#define CLK_PLL_VIDEO 6
|
||||
#define CLK_PLL_VIDEO_2X 7
|
||||
#define CLK_PLL_VE 8
|
||||
#define CLK_PLL_DDR0 9
|
||||
#define CLK_PLL_PERIPH 10
|
||||
|
||||
/* CPU clock is exported */
|
||||
|
||||
#define CLK_AHB 12
|
||||
#define CLK_APB 13
|
||||
|
||||
/* All bus gates, DRAM gates and mod clocks are exported */
|
||||
|
||||
#define CLK_NUMBER (CLK_AVS + 1)
|
||||
|
||||
#endif /* _CCU_SUNIV_F1C100S_H_ */
|
||||
|
|
@ -40,6 +40,61 @@ static void ccu_mp_find_best(unsigned long parent, unsigned long rate,
|
|||
*p = best_p;
|
||||
}
|
||||
|
||||
static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw,
|
||||
unsigned long *parent,
|
||||
unsigned long rate,
|
||||
unsigned int max_m,
|
||||
unsigned int max_p)
|
||||
{
|
||||
unsigned long parent_rate_saved;
|
||||
unsigned long parent_rate, now;
|
||||
unsigned long best_rate = 0;
|
||||
unsigned int _m, _p, div;
|
||||
unsigned long maxdiv;
|
||||
|
||||
parent_rate_saved = *parent;
|
||||
|
||||
/*
|
||||
* The maximum divider we can use without overflowing
|
||||
* unsigned long in rate * m * p below
|
||||
*/
|
||||
maxdiv = max_m * max_p;
|
||||
maxdiv = min(ULONG_MAX / rate, maxdiv);
|
||||
|
||||
for (_p = 1; _p <= max_p; _p <<= 1) {
|
||||
for (_m = 1; _m <= max_m; _m++) {
|
||||
div = _m * _p;
|
||||
|
||||
if (div > maxdiv)
|
||||
break;
|
||||
|
||||
if (rate * div == parent_rate_saved) {
|
||||
/*
|
||||
* It's the most ideal case if the requested
|
||||
* rate can be divided from parent clock without
|
||||
* needing to change parent rate, so return the
|
||||
* divider immediately.
|
||||
*/
|
||||
*parent = parent_rate_saved;
|
||||
return rate;
|
||||
}
|
||||
|
||||
parent_rate = clk_hw_round_rate(hw, rate * div);
|
||||
now = parent_rate / div;
|
||||
|
||||
if (now <= rate && now > best_rate) {
|
||||
best_rate = now;
|
||||
*parent = parent_rate;
|
||||
|
||||
if (now == rate)
|
||||
return rate;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return best_rate;
|
||||
}
|
||||
|
||||
static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux,
|
||||
struct clk_hw *hw,
|
||||
unsigned long *parent_rate,
|
||||
|
|
@ -56,8 +111,13 @@ static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux,
|
|||
max_m = cmp->m.max ?: 1 << cmp->m.width;
|
||||
max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
|
||||
|
||||
ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
|
||||
rate = *parent_rate / p / m;
|
||||
if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
|
||||
ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
|
||||
rate = *parent_rate / p / m;
|
||||
} else {
|
||||
rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate,
|
||||
max_m, max_p);
|
||||
}
|
||||
|
||||
if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
|
||||
rate /= cmp->fixed_post_div;
|
||||
|
|
|
|||
|
|
@ -19,6 +19,17 @@ struct _ccu_nm {
|
|||
unsigned long m, min_m, max_m;
|
||||
};
|
||||
|
||||
static unsigned long ccu_nm_calc_rate(unsigned long parent,
|
||||
unsigned long n, unsigned long m)
|
||||
{
|
||||
u64 rate = parent;
|
||||
|
||||
rate *= n;
|
||||
do_div(rate, m);
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
static void ccu_nm_find_best(unsigned long parent, unsigned long rate,
|
||||
struct _ccu_nm *nm)
|
||||
{
|
||||
|
|
@ -28,7 +39,8 @@ static void ccu_nm_find_best(unsigned long parent, unsigned long rate,
|
|||
|
||||
for (_n = nm->min_n; _n <= nm->max_n; _n++) {
|
||||
for (_m = nm->min_m; _m <= nm->max_m; _m++) {
|
||||
unsigned long tmp_rate = parent * _n / _m;
|
||||
unsigned long tmp_rate = ccu_nm_calc_rate(parent,
|
||||
_n, _m);
|
||||
|
||||
if (tmp_rate > rate)
|
||||
continue;
|
||||
|
|
@ -100,7 +112,7 @@ static unsigned long ccu_nm_recalc_rate(struct clk_hw *hw,
|
|||
if (ccu_sdm_helper_is_enabled(&nm->common, &nm->sdm))
|
||||
rate = ccu_sdm_helper_read_rate(&nm->common, &nm->sdm, m, n);
|
||||
else
|
||||
rate = parent_rate * n / m;
|
||||
rate = ccu_nm_calc_rate(parent_rate, n, m);
|
||||
|
||||
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
|
||||
rate /= nm->fixed_post_div;
|
||||
|
|
@ -149,7 +161,7 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
_nm.max_m = nm->m.max ?: 1 << nm->m.width;
|
||||
|
||||
ccu_nm_find_best(*parent_rate, rate, &_nm);
|
||||
rate = *parent_rate * _nm.n / _nm.m;
|
||||
rate = ccu_nm_calc_rate(*parent_rate, _nm.n, _nm.m);
|
||||
|
||||
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
|
||||
rate /= nm->fixed_post_div;
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@ const struct clk_ops tegra_clk_sync_source_ops = {
|
|||
};
|
||||
|
||||
struct clk *tegra_clk_register_sync_source(const char *name,
|
||||
unsigned long rate, unsigned long max_rate)
|
||||
unsigned long max_rate)
|
||||
{
|
||||
struct tegra_clk_sync_source *sync;
|
||||
struct clk_init_data init;
|
||||
|
|
@ -67,7 +67,6 @@ struct clk *tegra_clk_register_sync_source(const char *name,
|
|||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
sync->rate = rate;
|
||||
sync->max_rate = max_rate;
|
||||
|
||||
init.ops = &tegra_clk_sync_source_ops;
|
||||
|
|
|
|||
|
|
@ -590,12 +590,13 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
|
|||
cfg->n = cfg->output_rate / cfreq;
|
||||
cfg->cpcon = OUT_OF_TABLE_CPCON;
|
||||
|
||||
if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
|
||||
(1 << p_div) > divp_max(pll)
|
||||
|| cfg->output_rate > pll->params->vco_max) {
|
||||
if (cfg->m == 0 || cfg->m > divm_max(pll) ||
|
||||
cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) ||
|
||||
cfg->output_rate > pll->params->vco_max) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m);
|
||||
cfg->output_rate >>= p_div;
|
||||
|
||||
if (pll->params->pdiv_tohw) {
|
||||
|
|
|
|||
|
|
@ -49,8 +49,6 @@ struct tegra_sync_source_initdata {
|
|||
#define SYNC(_name) \
|
||||
{\
|
||||
.name = #_name,\
|
||||
.rate = 24000000,\
|
||||
.max_rate = 24000000,\
|
||||
.clk_id = tegra_clk_ ## _name,\
|
||||
}
|
||||
|
||||
|
|
@ -176,7 +174,7 @@ static void __init tegra_audio_sync_clk_init(void __iomem *clk_base,
|
|||
void __init tegra_audio_clk_init(void __iomem *clk_base,
|
||||
void __iomem *pmc_base, struct tegra_clk *tegra_clks,
|
||||
struct tegra_audio_clk_info *audio_info,
|
||||
unsigned int num_plls)
|
||||
unsigned int num_plls, unsigned long sync_max_rate)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk **dt_clk;
|
||||
|
|
@ -221,8 +219,7 @@ void __init tegra_audio_clk_init(void __iomem *clk_base,
|
|||
if (!dt_clk)
|
||||
continue;
|
||||
|
||||
clk = tegra_clk_register_sync_source(data->name,
|
||||
data->rate, data->max_rate);
|
||||
clk = tegra_clk_register_sync_source(data->name, sync_max_rate);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -79,7 +79,6 @@
|
|||
#define CLK_SOURCE_3D 0x158
|
||||
#define CLK_SOURCE_2D 0x15c
|
||||
#define CLK_SOURCE_MPE 0x170
|
||||
#define CLK_SOURCE_UARTE 0x1c4
|
||||
#define CLK_SOURCE_VI_SENSOR 0x1a8
|
||||
#define CLK_SOURCE_VI 0x148
|
||||
#define CLK_SOURCE_EPP 0x16c
|
||||
|
|
@ -117,8 +116,6 @@
|
|||
#define CLK_SOURCE_ISP 0x144
|
||||
#define CLK_SOURCE_SOR0 0x414
|
||||
#define CLK_SOURCE_DPAUX 0x418
|
||||
#define CLK_SOURCE_SATA_OOB 0x420
|
||||
#define CLK_SOURCE_SATA 0x424
|
||||
#define CLK_SOURCE_ENTROPY 0x628
|
||||
#define CLK_SOURCE_VI_SENSOR2 0x658
|
||||
#define CLK_SOURCE_HDMI_AUDIO 0x668
|
||||
|
|
|
|||
|
|
@ -1190,6 +1190,13 @@ static struct tegra_clk_init_table init_table[] __initdata = {
|
|||
{ TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 },
|
||||
{ TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 },
|
||||
{ TEGRA114_CLK_VDE, TEGRA114_CLK_CLK_MAX, 600000000, 0 },
|
||||
{ TEGRA114_CLK_SPDIF_IN_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA114_CLK_I2S0_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA114_CLK_I2S1_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA114_CLK_I2S2_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA114_CLK_I2S3_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA114_CLK_I2S4_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA114_CLK_VIMCLK_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
|
||||
/* must be the last entry */
|
||||
{ TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 },
|
||||
};
|
||||
|
|
@ -1362,7 +1369,7 @@ static void __init tegra114_clock_init(struct device_node *np)
|
|||
tegra114_periph_clk_init(clk_base, pmc_base);
|
||||
tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
|
||||
tegra114_audio_plls,
|
||||
ARRAY_SIZE(tegra114_audio_plls));
|
||||
ARRAY_SIZE(tegra114_audio_plls), 24000000);
|
||||
tegra_pmc_clk_init(pmc_base, tegra114_clks);
|
||||
tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
|
||||
&pll_x_params);
|
||||
|
|
|
|||
|
|
@ -1291,6 +1291,13 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
|
|||
{ TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 },
|
||||
{ TEGRA124_CLK_VIC03, TEGRA124_CLK_PLL_C3, 0, 0 },
|
||||
{ TEGRA124_CLK_SPDIF_IN_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA124_CLK_I2S0_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA124_CLK_I2S1_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA124_CLK_I2S2_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA124_CLK_I2S3_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA124_CLK_I2S4_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA124_CLK_VIMCLK_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
|
||||
/* must be the last entry */
|
||||
{ TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
|
||||
};
|
||||
|
|
@ -1455,7 +1462,7 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
|
|||
tegra124_periph_clk_init(clk_base, pmc_base);
|
||||
tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks,
|
||||
tegra124_audio_plls,
|
||||
ARRAY_SIZE(tegra124_audio_plls));
|
||||
ARRAY_SIZE(tegra124_audio_plls), 24576000);
|
||||
tegra_pmc_clk_init(pmc_base, tegra124_clks);
|
||||
|
||||
/* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
|
||||
|
|
|
|||
|
|
@ -578,7 +578,6 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true },
|
||||
[tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true },
|
||||
[tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true },
|
||||
[tegra_clk_emc] = { .dt_id = TEGRA20_CLK_EMC, .present = true },
|
||||
};
|
||||
|
||||
static unsigned long tegra20_clk_measure_input_freq(void)
|
||||
|
|
@ -799,6 +798,41 @@ static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
|
|||
TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2),
|
||||
};
|
||||
|
||||
static void __init tegra20_emc_clk_init(void)
|
||||
{
|
||||
const u32 use_pllm_ud = BIT(29);
|
||||
struct clk *clk;
|
||||
u32 emc_reg;
|
||||
|
||||
clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
|
||||
ARRAY_SIZE(mux_pllmcp_clkm),
|
||||
CLK_SET_RATE_NO_REPARENT,
|
||||
clk_base + CLK_SOURCE_EMC,
|
||||
30, 2, 0, &emc_lock);
|
||||
|
||||
clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
|
||||
&emc_lock);
|
||||
clks[TEGRA20_CLK_MC] = clk;
|
||||
|
||||
/* un-divided pll_m_out0 is currently unsupported */
|
||||
emc_reg = readl_relaxed(clk_base + CLK_SOURCE_EMC);
|
||||
if (emc_reg & use_pllm_ud) {
|
||||
pr_err("%s: un-divided PllM_out0 used as clock source\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Note that 'emc_mux' source and 'emc' rate shouldn't be changed at
|
||||
* the same time due to a HW bug, this won't happen because we're
|
||||
* defining 'emc_mux' and 'emc' as distinct clocks.
|
||||
*/
|
||||
clk = tegra_clk_register_divider("emc", "emc_mux",
|
||||
clk_base + CLK_SOURCE_EMC, CLK_IS_CRITICAL,
|
||||
TEGRA_DIVIDER_INT, 0, 8, 1, &emc_lock);
|
||||
clks[TEGRA20_CLK_EMC] = clk;
|
||||
}
|
||||
|
||||
static void __init tegra20_periph_clk_init(void)
|
||||
{
|
||||
struct tegra_periph_init_data *data;
|
||||
|
|
@ -812,15 +846,7 @@ static void __init tegra20_periph_clk_init(void)
|
|||
clks[TEGRA20_CLK_AC97] = clk;
|
||||
|
||||
/* emc */
|
||||
clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
|
||||
ARRAY_SIZE(mux_pllmcp_clkm),
|
||||
CLK_SET_RATE_NO_REPARENT,
|
||||
clk_base + CLK_SOURCE_EMC,
|
||||
30, 2, 0, &emc_lock);
|
||||
|
||||
clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
|
||||
&emc_lock);
|
||||
clks[TEGRA20_CLK_MC] = clk;
|
||||
tegra20_emc_clk_init();
|
||||
|
||||
/* dsi */
|
||||
clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
|
||||
|
|
|
|||
|
|
@ -3370,6 +3370,13 @@ static struct tegra_clk_init_table init_table[] __initdata = {
|
|||
{ TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 },
|
||||
{ TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 },
|
||||
{ TEGRA210_CLK_SPDIF_IN_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA210_CLK_I2S0_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA210_CLK_I2S1_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA210_CLK_I2S2_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA210_CLK_I2S3_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA210_CLK_I2S4_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
|
||||
/* This MUST be the last entry. */
|
||||
{ TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
|
||||
};
|
||||
|
|
@ -3563,7 +3570,7 @@ static void __init tegra210_clock_init(struct device_node *np)
|
|||
tegra210_periph_clk_init(clk_base, pmc_base);
|
||||
tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,
|
||||
tegra210_audio_plls,
|
||||
ARRAY_SIZE(tegra210_audio_plls));
|
||||
ARRAY_SIZE(tegra210_audio_plls), 24576000);
|
||||
tegra_pmc_clk_init(pmc_base, tegra210_clks);
|
||||
|
||||
/* For Tegra210, PLLD is the only source for DSIA & DSIB */
|
||||
|
|
|
|||
|
|
@ -1148,9 +1148,9 @@ static bool tegra30_cpu_rail_off_ready(void)
|
|||
|
||||
cpu_rst_status = readl(clk_base +
|
||||
TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
|
||||
cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) ||
|
||||
tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) ||
|
||||
tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3);
|
||||
cpu_pwr_status = tegra_pmc_cpu_is_powered(1) ||
|
||||
tegra_pmc_cpu_is_powered(2) ||
|
||||
tegra_pmc_cpu_is_powered(3);
|
||||
|
||||
if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
|
||||
return false;
|
||||
|
|
@ -1267,6 +1267,13 @@ static struct tegra_clk_init_table init_table[] __initdata = {
|
|||
{ TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },
|
||||
{ TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 },
|
||||
{ TEGRA30_CLK_VDE, TEGRA30_CLK_CLK_MAX, 600000000, 0 },
|
||||
{ TEGRA30_CLK_SPDIF_IN_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA30_CLK_I2S0_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA30_CLK_I2S1_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA30_CLK_I2S2_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA30_CLK_I2S3_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA30_CLK_I2S4_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
|
||||
/* must be the last entry */
|
||||
{ TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
|
||||
};
|
||||
|
|
@ -1344,7 +1351,7 @@ static void __init tegra30_clock_init(struct device_node *np)
|
|||
tegra30_periph_clk_init();
|
||||
tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,
|
||||
tegra30_audio_plls,
|
||||
ARRAY_SIZE(tegra30_audio_plls));
|
||||
ARRAY_SIZE(tegra30_audio_plls), 24000000);
|
||||
tegra_pmc_clk_init(pmc_base, tegra30_clks);
|
||||
|
||||
tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ extern const struct clk_ops tegra_clk_sync_source_ops;
|
|||
extern int *periph_clk_enb_refcnt;
|
||||
|
||||
struct clk *tegra_clk_register_sync_source(const char *name,
|
||||
unsigned long fixed_rate, unsigned long max_rate);
|
||||
unsigned long max_rate);
|
||||
|
||||
/**
|
||||
* struct tegra_clk_frac_div - fractional divider clock
|
||||
|
|
@ -796,7 +796,7 @@ void tegra_register_devclks(struct tegra_devclk *dev_clks, int num);
|
|||
void tegra_audio_clk_init(void __iomem *clk_base,
|
||||
void __iomem *pmc_base, struct tegra_clk *tegra_clks,
|
||||
struct tegra_audio_clk_info *audio_info,
|
||||
unsigned int num_plls);
|
||||
unsigned int num_plls, unsigned long sync_max_rate);
|
||||
|
||||
void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
|
||||
struct tegra_clk *tegra_clks,
|
||||
|
|
|
|||
|
|
@ -600,7 +600,6 @@ int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
|
|||
}
|
||||
EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
/**
|
||||
* tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
|
||||
* @cpuid: CPU partition ID
|
||||
|
|
@ -660,7 +659,6 @@ int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
|
|||
|
||||
return tegra_powergate_remove_clamping(id);
|
||||
}
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
static int tegra_pmc_restart_notify(struct notifier_block *this,
|
||||
unsigned long action, void *data)
|
||||
|
|
|
|||
|
|
@ -128,5 +128,23 @@
|
|||
#define CLKID_VDEC_1 153
|
||||
#define CLKID_VDEC_HEVC 156
|
||||
#define CLKID_GEN_CLK 159
|
||||
#define CLKID_VID_PLL 166
|
||||
#define CLKID_VCLK 175
|
||||
#define CLKID_VCLK2 176
|
||||
#define CLKID_VCLK_DIV1 185
|
||||
#define CLKID_VCLK_DIV2 186
|
||||
#define CLKID_VCLK_DIV4 187
|
||||
#define CLKID_VCLK_DIV6 188
|
||||
#define CLKID_VCLK_DIV12 189
|
||||
#define CLKID_VCLK2_DIV1 190
|
||||
#define CLKID_VCLK2_DIV2 191
|
||||
#define CLKID_VCLK2_DIV4 192
|
||||
#define CLKID_VCLK2_DIV6 193
|
||||
#define CLKID_VCLK2_DIV12 194
|
||||
#define CLKID_CTS_ENCI 199
|
||||
#define CLKID_CTS_ENCP 200
|
||||
#define CLKID_CTS_VDAC 201
|
||||
#define CLKID_HDMI_TX 202
|
||||
#define CLKID_HDMI 205
|
||||
|
||||
#endif /* __GXBB_CLKC_H */
|
||||
|
|
|
|||
|
|
@ -103,5 +103,9 @@
|
|||
#define CLKID_MPLL1 94
|
||||
#define CLKID_MPLL2 95
|
||||
#define CLKID_NAND_CLK 112
|
||||
#define CLKID_ABP 124
|
||||
#define CLKID_PERIPH 126
|
||||
#define CLKID_AXI 128
|
||||
#define CLKID_L2_DRAM 130
|
||||
|
||||
#endif /* __MESON8B_CLKC_H */
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@
|
|||
#define R8A7795_CLK_CANFD 39
|
||||
#define R8A7795_CLK_HDMI 40
|
||||
#define R8A7795_CLK_CSI0 41
|
||||
#define R8A7795_CLK_CSIREF 42
|
||||
/* CLK_CSIREF was removed */
|
||||
#define R8A7795_CLK_CP 43
|
||||
#define R8A7795_CLK_CPEX 44
|
||||
#define R8A7795_CLK_R 45
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@
|
|||
#define R8A7796_CLK_CANFD 45
|
||||
#define R8A7796_CLK_HDMI 46
|
||||
#define R8A7796_CLK_CSI0 47
|
||||
#define R8A7796_CLK_CSIREF 48
|
||||
/* CLK_CSIREF was removed */
|
||||
#define R8A7796_CLK_CP 49
|
||||
#define R8A7796_CLK_CPEX 50
|
||||
#define R8A7796_CLK_R 51
|
||||
|
|
|
|||
|
|
@ -35,8 +35,8 @@
|
|||
#define R8A77995_CLK_CRD2 24
|
||||
#define R8A77995_CLK_SD0H 25
|
||||
#define R8A77995_CLK_SD0 26
|
||||
#define R8A77995_CLK_SSP2 27
|
||||
#define R8A77995_CLK_SSP1 28
|
||||
/* CLK_SSP2 was removed */
|
||||
/* CLK_SSP1 was removed */
|
||||
#define R8A77995_CLK_RPC 29
|
||||
#define R8A77995_CLK_RPCD2 30
|
||||
#define R8A77995_CLK_ZA2 31
|
||||
|
|
@ -49,5 +49,6 @@
|
|||
#define R8A77995_CLK_LV0 38
|
||||
#define R8A77995_CLK_LV1 39
|
||||
#define R8A77995_CLK_CP 40
|
||||
#define R8A77995_CLK_CPEX 41
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */
|
||||
|
|
|
|||
|
|
@ -172,13 +172,14 @@
|
|||
#define PCLK_HDCP 232
|
||||
#define PCLK_DCF 233
|
||||
#define PCLK_SARADC 234
|
||||
#define PCLK_ACODECPHY 235
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_PERI 308
|
||||
#define HCLK_TSP 309
|
||||
#define HCLK_GMAC 310
|
||||
#define HCLK_I2S0_8CH 311
|
||||
#define HCLK_I2S1_8CH 313
|
||||
#define HCLK_I2S1_8CH 312
|
||||
#define HCLK_I2S2_2CH 313
|
||||
#define HCLK_SPDIF_8CH 314
|
||||
#define HCLK_VOP 315
|
||||
|
|
|
|||
|
|
@ -15,4 +15,7 @@
|
|||
#define CLK_MIXER1 7
|
||||
#define CLK_WB 8
|
||||
|
||||
#define CLK_BUS_ROT 9
|
||||
#define CLK_ROT 10
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,70 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
*
|
||||
* Copyright (c) 2018 Icenowy Zheng <icenowy@aosc.xyz>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
|
||||
#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
|
||||
|
||||
#define CLK_CPU 11
|
||||
|
||||
#define CLK_BUS_DMA 14
|
||||
#define CLK_BUS_MMC0 15
|
||||
#define CLK_BUS_MMC1 16
|
||||
#define CLK_BUS_DRAM 17
|
||||
#define CLK_BUS_SPI0 18
|
||||
#define CLK_BUS_SPI1 19
|
||||
#define CLK_BUS_OTG 20
|
||||
#define CLK_BUS_VE 21
|
||||
#define CLK_BUS_LCD 22
|
||||
#define CLK_BUS_DEINTERLACE 23
|
||||
#define CLK_BUS_CSI 24
|
||||
#define CLK_BUS_TVD 25
|
||||
#define CLK_BUS_TVE 26
|
||||
#define CLK_BUS_DE_BE 27
|
||||
#define CLK_BUS_DE_FE 28
|
||||
#define CLK_BUS_CODEC 29
|
||||
#define CLK_BUS_SPDIF 30
|
||||
#define CLK_BUS_IR 31
|
||||
#define CLK_BUS_RSB 32
|
||||
#define CLK_BUS_I2S0 33
|
||||
#define CLK_BUS_I2C0 34
|
||||
#define CLK_BUS_I2C1 35
|
||||
#define CLK_BUS_I2C2 36
|
||||
#define CLK_BUS_PIO 37
|
||||
#define CLK_BUS_UART0 38
|
||||
#define CLK_BUS_UART1 39
|
||||
#define CLK_BUS_UART2 40
|
||||
|
||||
#define CLK_MMC0 41
|
||||
#define CLK_MMC0_SAMPLE 42
|
||||
#define CLK_MMC0_OUTPUT 43
|
||||
#define CLK_MMC1 44
|
||||
#define CLK_MMC1_SAMPLE 45
|
||||
#define CLK_MMC1_OUTPUT 46
|
||||
#define CLK_I2S 47
|
||||
#define CLK_SPDIF 48
|
||||
|
||||
#define CLK_USB_PHY0 49
|
||||
|
||||
#define CLK_DRAM_VE 50
|
||||
#define CLK_DRAM_CSI 51
|
||||
#define CLK_DRAM_DEINTERLACE 52
|
||||
#define CLK_DRAM_TVD 53
|
||||
#define CLK_DRAM_DE_FE 54
|
||||
#define CLK_DRAM_DE_BE 55
|
||||
|
||||
#define CLK_DE_BE 56
|
||||
#define CLK_DE_FE 57
|
||||
#define CLK_TCON 58
|
||||
#define CLK_DEINTERLACE 59
|
||||
#define CLK_TVE2_CLK 60
|
||||
#define CLK_TVE1_CLK 61
|
||||
#define CLK_TVD 62
|
||||
#define CLK_CSI 63
|
||||
#define CLK_VE 64
|
||||
#define CLK_CODEC 65
|
||||
#define CLK_AVS 66
|
||||
|
||||
#endif
|
||||
|
|
@ -10,5 +10,6 @@
|
|||
#define RST_MIXER0 0
|
||||
#define RST_MIXER1 1
|
||||
#define RST_WB 2
|
||||
#define RST_ROT 3
|
||||
|
||||
#endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,38 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
*
|
||||
* Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.xyz>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RST_SUNIV_F1C100S_H_
|
||||
#define _DT_BINDINGS_RST_SUNIV_F1C100S_H_
|
||||
|
||||
#define RST_USB_PHY0 0
|
||||
#define RST_BUS_DMA 1
|
||||
#define RST_BUS_MMC0 2
|
||||
#define RST_BUS_MMC1 3
|
||||
#define RST_BUS_DRAM 4
|
||||
#define RST_BUS_SPI0 5
|
||||
#define RST_BUS_SPI1 6
|
||||
#define RST_BUS_OTG 7
|
||||
#define RST_BUS_VE 8
|
||||
#define RST_BUS_LCD 9
|
||||
#define RST_BUS_DEINTERLACE 10
|
||||
#define RST_BUS_CSI 11
|
||||
#define RST_BUS_TVD 12
|
||||
#define RST_BUS_TVE 13
|
||||
#define RST_BUS_DE_BE 14
|
||||
#define RST_BUS_DE_FE 15
|
||||
#define RST_BUS_CODEC 16
|
||||
#define RST_BUS_SPDIF 17
|
||||
#define RST_BUS_IR 18
|
||||
#define RST_BUS_RSB 19
|
||||
#define RST_BUS_I2S0 20
|
||||
#define RST_BUS_I2C0 21
|
||||
#define RST_BUS_I2C1 22
|
||||
#define RST_BUS_I2C2 23
|
||||
#define RST_BUS_UART0 24
|
||||
#define RST_BUS_UART1 25
|
||||
#define RST_BUS_UART2 26
|
||||
|
||||
#endif /* _DT_BINDINGS_RST_SUNIV_F1C100S_H_ */
|
||||
|
|
@ -26,11 +26,9 @@
|
|||
struct clk;
|
||||
struct reset_control;
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
bool tegra_pmc_cpu_is_powered(unsigned int cpuid);
|
||||
int tegra_pmc_cpu_power_on(unsigned int cpuid);
|
||||
int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
/*
|
||||
* powergate and I/O rail APIs
|
||||
|
|
|
|||
Loading…
Reference in New Issue