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ARM: 6473/1: Small update to ux500 specific L2 cache code 

This change updates the ux500 specific outer cache code to use
the new *_relaxed() I/O accessors.

Signed-off-by: Per Fransson <per.xx.fransson@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Per Fransson 2010-11-15 14:31:17 +01:00 committed by Russell King
parent c0ba10b512
commit ffc43ef313
1 changed files with 3 additions and 3 deletions
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6
arch/arm/mach-ux500/cpu.c
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@ -75,14 +75,14 @@ void __init ux500_init_irq(void)
static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
{
/* wait for the operation to complete */
while (readl(reg) & mask)
while (readl_relaxed(reg) & mask)
;
}
static inline void ux500_cache_sync(void)
{
void __iomem *base = __io_address(UX500_L2CC_BASE);
writel(0, base + L2X0_CACHE_SYNC);
writel_relaxed(0, base + L2X0_CACHE_SYNC);
ux500_cache_wait(base + L2X0_CACHE_SYNC, 1);
}
@ -107,7 +107,7 @@ static void ux500_l2x0_inv_all(void)
uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */
/* invalidate all ways */
writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
ux500_cache_sync();
}