mailbox: add STMicroelectronics STM32 IPCC driver
The STMicroelectronics STM32 Inter-Processor Communication Controller (IPCC) is used for communicating data between two processors. It provides a non blocking signaling mechanism to post and retrieve communication data in an atomic way. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
This commit is contained in:
Fabien Dessenne
Jassi Brar
parent
8f51bb7cae
commit
ffbded7dee
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@ -177,4 +177,12 @@ config BCM_FLEXRM_MBOX
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Mailbox implementation of the Broadcom FlexRM ring manager,
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Mailbox implementation of the Broadcom FlexRM ring manager,
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which provides access to various offload engines on Broadcom
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which provides access to various offload engines on Broadcom
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SoCs. Say Y here if you want to use the Broadcom FlexRM.
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SoCs. Say Y here if you want to use the Broadcom FlexRM.
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config STM32_IPCC
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tristate "STM32 IPCC Mailbox"
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depends on MACH_STM32MP157
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help
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Mailbox implementation for STMicroelectonics STM32 family chips
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with hardware for Inter-Processor Communication Controller (IPCC)
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between processors. Say Y here if you want to have this support.
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endif
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endif
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@ -38,3 +38,5 @@ obj-$(CONFIG_BCM_FLEXRM_MBOX) += bcm-flexrm-mailbox.o
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obj-$(CONFIG_QCOM_APCS_IPC) += qcom-apcs-ipc-mailbox.o
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obj-$(CONFIG_QCOM_APCS_IPC) += qcom-apcs-ipc-mailbox.o
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obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
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obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
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obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
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@ -0,0 +1,402 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
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* Authors: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
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* Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/mailbox_controller.h>
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#include <linux/module.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/pm_wakeirq.h>
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#define IPCC_XCR 0x000
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#define XCR_RXOIE BIT(0)
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#define XCR_TXOIE BIT(16)
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#define IPCC_XMR 0x004
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#define IPCC_XSCR 0x008
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#define IPCC_XTOYSR 0x00c
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#define IPCC_PROC_OFFST 0x010
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#define IPCC_HWCFGR 0x3f0
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#define IPCFGR_CHAN_MASK GENMASK(7, 0)
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#define IPCC_VER 0x3f4
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#define VER_MINREV_MASK GENMASK(3, 0)
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#define VER_MAJREV_MASK GENMASK(7, 4)
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#define RX_BIT_MASK GENMASK(15, 0)
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#define RX_BIT_CHAN(chan) BIT(chan)
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#define TX_BIT_SHIFT 16
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#define TX_BIT_MASK GENMASK(31, 16)
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#define TX_BIT_CHAN(chan) BIT(TX_BIT_SHIFT + (chan))
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#define STM32_MAX_PROCS 2
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enum {
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IPCC_IRQ_RX,
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IPCC_IRQ_TX,
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IPCC_IRQ_NUM,
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};
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struct stm32_ipcc {
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struct mbox_controller controller;
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void __iomem *reg_base;
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void __iomem *reg_proc;
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struct clk *clk;
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int irqs[IPCC_IRQ_NUM];
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int wkp;
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u32 proc_id;
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u32 n_chans;
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u32 xcr;
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u32 xmr;
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};
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static inline void stm32_ipcc_set_bits(void __iomem *reg, u32 mask)
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{
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writel_relaxed(readl_relaxed(reg) | mask, reg);
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}
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static inline void stm32_ipcc_clr_bits(void __iomem *reg, u32 mask)
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{
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writel_relaxed(readl_relaxed(reg) & ~mask, reg);
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}
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static irqreturn_t stm32_ipcc_rx_irq(int irq, void *data)
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{
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struct stm32_ipcc *ipcc = data;
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struct device *dev = ipcc->controller.dev;
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u32 status, mr, tosr, chan;
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irqreturn_t ret = IRQ_NONE;
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int proc_offset;
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/* read 'channel occupied' status from other proc */
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proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
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tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);
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mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
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/* search for unmasked 'channel occupied' */
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status = tosr & FIELD_GET(RX_BIT_MASK, ~mr);
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for (chan = 0; chan < ipcc->n_chans; chan++) {
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if (!(status & (1 << chan)))
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continue;
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dev_dbg(dev, "%s: chan:%d rx\n", __func__, chan);
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mbox_chan_received_data(&ipcc->controller.chans[chan], NULL);
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stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XSCR,
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RX_BIT_CHAN(chan));
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ret = IRQ_HANDLED;
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}
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return ret;
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}
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static irqreturn_t stm32_ipcc_tx_irq(int irq, void *data)
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{
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struct stm32_ipcc *ipcc = data;
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struct device *dev = ipcc->controller.dev;
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u32 status, mr, tosr, chan;
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irqreturn_t ret = IRQ_NONE;
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tosr = readl_relaxed(ipcc->reg_proc + IPCC_XTOYSR);
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mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
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/* search for unmasked 'channel free' */
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status = ~tosr & FIELD_GET(TX_BIT_MASK, ~mr);
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for (chan = 0; chan < ipcc->n_chans ; chan++) {
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if (!(status & (1 << chan)))
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continue;
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dev_dbg(dev, "%s: chan:%d tx\n", __func__, chan);
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/* mask 'tx channel free' interrupt */
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stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
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TX_BIT_CHAN(chan));
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mbox_chan_txdone(&ipcc->controller.chans[chan], 0);
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ret = IRQ_HANDLED;
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}
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return ret;
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}
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static int stm32_ipcc_send_data(struct mbox_chan *link, void *data)
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{
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unsigned int chan = (unsigned int)link->con_priv;
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struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
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controller);
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dev_dbg(ipcc->controller.dev, "%s: chan:%d\n", __func__, chan);
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/* set channel n occupied */
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stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan));
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/* unmask 'tx channel free' interrupt */
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stm32_ipcc_clr_bits(ipcc->reg_proc + IPCC_XMR, TX_BIT_CHAN(chan));
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return 0;
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}
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static int stm32_ipcc_startup(struct mbox_chan *link)
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{
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unsigned int chan = (unsigned int)link->con_priv;
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struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
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controller);
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int ret;
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ret = clk_prepare_enable(ipcc->clk);
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if (ret) {
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dev_err(ipcc->controller.dev, "can not enable the clock\n");
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return ret;
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}
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/* unmask 'rx channel occupied' interrupt */
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stm32_ipcc_clr_bits(ipcc->reg_proc + IPCC_XMR, RX_BIT_CHAN(chan));
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return 0;
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}
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static void stm32_ipcc_shutdown(struct mbox_chan *link)
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{
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unsigned int chan = (unsigned int)link->con_priv;
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struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
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controller);
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/* mask rx/tx interrupt */
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stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
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RX_BIT_CHAN(chan) | TX_BIT_CHAN(chan));
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clk_disable_unprepare(ipcc->clk);
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}
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static const struct mbox_chan_ops stm32_ipcc_ops = {
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.send_data = stm32_ipcc_send_data,
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.startup = stm32_ipcc_startup,
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.shutdown = stm32_ipcc_shutdown,
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};
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static int stm32_ipcc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct stm32_ipcc *ipcc;
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struct resource *res;
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unsigned int i;
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int ret;
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u32 ip_ver;
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static const char * const irq_name[] = {"rx", "tx"};
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irq_handler_t irq_thread[] = {stm32_ipcc_rx_irq, stm32_ipcc_tx_irq};
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if (!np) {
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dev_err(dev, "No DT found\n");
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return -ENODEV;
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}
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ipcc = devm_kzalloc(dev, sizeof(*ipcc), GFP_KERNEL);
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if (!ipcc)
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return -ENOMEM;
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/* proc_id */
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if (of_property_read_u32(np, "st,proc-id", &ipcc->proc_id)) {
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dev_err(dev, "Missing st,proc-id\n");
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return -ENODEV;
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}
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if (ipcc->proc_id >= STM32_MAX_PROCS) {
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dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);
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return -EINVAL;
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}
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/* regs */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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ipcc->reg_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(ipcc->reg_base))
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return PTR_ERR(ipcc->reg_base);
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ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;
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/* clock */
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ipcc->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(ipcc->clk))
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return PTR_ERR(ipcc->clk);
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ret = clk_prepare_enable(ipcc->clk);
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if (ret) {
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dev_err(dev, "can not enable the clock\n");
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return ret;
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}
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/* irq */
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for (i = 0; i < IPCC_IRQ_NUM; i++) {
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ipcc->irqs[i] = of_irq_get_byname(dev->of_node, irq_name[i]);
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if (ipcc->irqs[i] < 0) {
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dev_err(dev, "no IRQ specified %s\n", irq_name[i]);
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ret = ipcc->irqs[i];
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goto err_clk;
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}
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ret = devm_request_threaded_irq(dev, ipcc->irqs[i], NULL,
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irq_thread[i], IRQF_ONESHOT,
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dev_name(dev), ipcc);
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if (ret) {
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dev_err(dev, "failed to request irq %d (%d)\n", i, ret);
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goto err_clk;
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}
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}
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/* mask and enable rx/tx irq */
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stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
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RX_BIT_MASK | TX_BIT_MASK);
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stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XCR, XCR_RXOIE | XCR_TXOIE);
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/* wakeup */
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if (of_property_read_bool(np, "wakeup-source")) {
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ipcc->wkp = of_irq_get_byname(dev->of_node, "wakeup");
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if (ipcc->wkp < 0) {
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dev_err(dev, "could not get wakeup IRQ\n");
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ret = ipcc->wkp;
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goto err_clk;
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}
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device_init_wakeup(dev, true);
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ret = dev_pm_set_dedicated_wake_irq(dev, ipcc->wkp);
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if (ret) {
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dev_err(dev, "Failed to set wake up irq\n");
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goto err_init_wkp;
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}
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} else {
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device_init_wakeup(dev, false);
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}
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/* mailbox controller */
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ipcc->n_chans = readl_relaxed(ipcc->reg_base + IPCC_HWCFGR);
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ipcc->n_chans &= IPCFGR_CHAN_MASK;
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ipcc->controller.dev = dev;
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ipcc->controller.txdone_irq = true;
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ipcc->controller.ops = &stm32_ipcc_ops;
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ipcc->controller.num_chans = ipcc->n_chans;
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ipcc->controller.chans = devm_kcalloc(dev, ipcc->controller.num_chans,
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sizeof(*ipcc->controller.chans),
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GFP_KERNEL);
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if (!ipcc->controller.chans) {
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ret = -ENOMEM;
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goto err_irq_wkp;
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}
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for (i = 0; i < ipcc->controller.num_chans; i++)
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ipcc->controller.chans[i].con_priv = (void *)i;
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ret = mbox_controller_register(&ipcc->controller);
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if (ret)
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goto err_irq_wkp;
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platform_set_drvdata(pdev, ipcc);
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ip_ver = readl_relaxed(ipcc->reg_base + IPCC_VER);
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dev_info(dev, "ipcc rev:%ld.%ld enabled, %d chans, proc %d\n",
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FIELD_GET(VER_MAJREV_MASK, ip_ver),
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FIELD_GET(VER_MINREV_MASK, ip_ver),
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ipcc->controller.num_chans, ipcc->proc_id);
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clk_disable_unprepare(ipcc->clk);
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return 0;
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err_irq_wkp:
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if (ipcc->wkp)
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dev_pm_clear_wake_irq(dev);
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err_init_wkp:
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device_init_wakeup(dev, false);
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err_clk:
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clk_disable_unprepare(ipcc->clk);
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return ret;
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}
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static int stm32_ipcc_remove(struct platform_device *pdev)
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{
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struct stm32_ipcc *ipcc = platform_get_drvdata(pdev);
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mbox_controller_unregister(&ipcc->controller);
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if (ipcc->wkp)
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dev_pm_clear_wake_irq(&pdev->dev);
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device_init_wakeup(&pdev->dev, false);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_PM_SLEEP
|
||||||
|
static void stm32_ipcc_set_irq_wake(struct device *dev, bool enable)
|
||||||
|
{
|
||||||
|
struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
|
||||||
|
unsigned int i;
|
||||||
|
|
||||||
|
if (device_may_wakeup(dev))
|
||||||
|
for (i = 0; i < IPCC_IRQ_NUM; i++)
|
||||||
|
irq_set_irq_wake(ipcc->irqs[i], enable);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int stm32_ipcc_suspend(struct device *dev)
|
||||||
|
{
|
||||||
|
struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
|
||||||
|
|
||||||
|
ipcc->xmr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
|
||||||
|
ipcc->xcr = readl_relaxed(ipcc->reg_proc + IPCC_XCR);
|
||||||
|
|
||||||
|
stm32_ipcc_set_irq_wake(dev, true);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int stm32_ipcc_resume(struct device *dev)
|
||||||
|
{
|
||||||
|
struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
|
||||||
|
|
||||||
|
stm32_ipcc_set_irq_wake(dev, false);
|
||||||
|
|
||||||
|
writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR);
|
||||||
|
writel_relaxed(ipcc->xcr, ipcc->reg_proc + IPCC_XCR);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static SIMPLE_DEV_PM_OPS(stm32_ipcc_pm_ops,
|
||||||
|
stm32_ipcc_suspend, stm32_ipcc_resume);
|
||||||
|
|
||||||
|
static const struct of_device_id stm32_ipcc_of_match[] = {
|
||||||
|
{ .compatible = "st,stm32mp1-ipcc" },
|
||||||
|
{},
|
||||||
|
};
|
||||||
|
MODULE_DEVICE_TABLE(of, stm32_ipcc_of_match);
|
||||||
|
|
||||||
|
static struct platform_driver stm32_ipcc_driver = {
|
||||||
|
.driver = {
|
||||||
|
.name = "stm32-ipcc",
|
||||||
|
.pm = &stm32_ipcc_pm_ops,
|
||||||
|
.of_match_table = stm32_ipcc_of_match,
|
||||||
|
},
|
||||||
|
.probe = stm32_ipcc_probe,
|
||||||
|
.remove = stm32_ipcc_remove,
|
||||||
|
};
|
||||||
|
|
||||||
|
module_platform_driver(stm32_ipcc_driver);
|
||||||
|
|
||||||
|
MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
|
||||||
|
MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
|
||||||
|
MODULE_DESCRIPTION("STM32 IPCC driver");
|
||||||
|
MODULE_LICENSE("GPL v2");
|
||||||
Loading…
Reference in New Issue