tg3: Eliminate nvram routine forward declarations
This patch moves all NVRAM routines earlier in the source file to eliminate forward declarations. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Benjamin Li <benli@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
David S. Miller
parent
844b3eed8a
commit
ffbcfed441
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@ -2050,8 +2050,6 @@ static int tg3_setup_phy(struct tg3 *, int);
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static void tg3_write_sig_post_reset(struct tg3 *, int);
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static int tg3_halt_cpu(struct tg3 *, u32);
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static int tg3_nvram_lock(struct tg3 *);
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static void tg3_nvram_unlock(struct tg3 *);
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static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
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{
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@ -2107,6 +2105,197 @@ static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
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tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
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}
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/* tp->lock is held. */
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static int tg3_nvram_lock(struct tg3 *tp)
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{
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if (tp->tg3_flags & TG3_FLAG_NVRAM) {
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int i;
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if (tp->nvram_lock_cnt == 0) {
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tw32(NVRAM_SWARB, SWARB_REQ_SET1);
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for (i = 0; i < 8000; i++) {
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if (tr32(NVRAM_SWARB) & SWARB_GNT1)
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break;
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udelay(20);
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}
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if (i == 8000) {
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tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
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return -ENODEV;
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}
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}
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tp->nvram_lock_cnt++;
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}
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return 0;
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}
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/* tp->lock is held. */
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static void tg3_nvram_unlock(struct tg3 *tp)
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{
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if (tp->tg3_flags & TG3_FLAG_NVRAM) {
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if (tp->nvram_lock_cnt > 0)
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tp->nvram_lock_cnt--;
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if (tp->nvram_lock_cnt == 0)
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tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
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}
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}
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/* tp->lock is held. */
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static void tg3_enable_nvram_access(struct tg3 *tp)
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{
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if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
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!(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
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u32 nvaccess = tr32(NVRAM_ACCESS);
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tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
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}
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}
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/* tp->lock is held. */
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static void tg3_disable_nvram_access(struct tg3 *tp)
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{
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if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
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!(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
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u32 nvaccess = tr32(NVRAM_ACCESS);
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tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
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}
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}
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static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
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u32 offset, u32 *val)
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{
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u32 tmp;
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int i;
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if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
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return -EINVAL;
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tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
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EEPROM_ADDR_DEVID_MASK |
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EEPROM_ADDR_READ);
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tw32(GRC_EEPROM_ADDR,
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tmp |
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(0 << EEPROM_ADDR_DEVID_SHIFT) |
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((offset << EEPROM_ADDR_ADDR_SHIFT) &
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EEPROM_ADDR_ADDR_MASK) |
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EEPROM_ADDR_READ | EEPROM_ADDR_START);
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for (i = 0; i < 1000; i++) {
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tmp = tr32(GRC_EEPROM_ADDR);
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if (tmp & EEPROM_ADDR_COMPLETE)
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break;
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msleep(1);
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}
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if (!(tmp & EEPROM_ADDR_COMPLETE))
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return -EBUSY;
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*val = tr32(GRC_EEPROM_DATA);
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return 0;
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}
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#define NVRAM_CMD_TIMEOUT 10000
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static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
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{
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int i;
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tw32(NVRAM_CMD, nvram_cmd);
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for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
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udelay(10);
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if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
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udelay(10);
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break;
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}
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}
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if (i == NVRAM_CMD_TIMEOUT)
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return -EBUSY;
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return 0;
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}
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static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
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{
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if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
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(tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
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(tp->tg3_flags2 & TG3_FLG2_FLASH) &&
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!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
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(tp->nvram_jedecnum == JEDEC_ATMEL))
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addr = ((addr / tp->nvram_pagesize) <<
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ATMEL_AT45DB0X1B_PAGE_POS) +
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(addr % tp->nvram_pagesize);
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return addr;
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}
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static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
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{
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if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
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(tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
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(tp->tg3_flags2 & TG3_FLG2_FLASH) &&
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!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
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(tp->nvram_jedecnum == JEDEC_ATMEL))
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addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
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tp->nvram_pagesize) +
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(addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
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return addr;
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}
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static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
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{
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int ret;
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if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
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return tg3_nvram_read_using_eeprom(tp, offset, val);
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offset = tg3_nvram_phys_addr(tp, offset);
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if (offset > NVRAM_ADDR_MSK)
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return -EINVAL;
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ret = tg3_nvram_lock(tp);
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if (ret)
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return ret;
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tg3_enable_nvram_access(tp);
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tw32(NVRAM_ADDR, offset);
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ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
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NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
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if (ret == 0)
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*val = swab32(tr32(NVRAM_RDDATA));
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tg3_disable_nvram_access(tp);
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tg3_nvram_unlock(tp);
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return ret;
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}
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static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
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{
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int err;
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u32 tmp;
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err = tg3_nvram_read(tp, offset, &tmp);
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*val = swab32(tmp);
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return err;
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}
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static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val)
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{
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u32 v;
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int res = tg3_nvram_read(tp, offset, &v);
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if (!res)
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*val = cpu_to_le32(v);
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return res;
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}
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/* tp->lock is held. */
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static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
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{
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@ -5638,62 +5827,6 @@ static int tg3_abort_hw(struct tg3 *tp, int silent)
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return err;
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}
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/* tp->lock is held. */
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static int tg3_nvram_lock(struct tg3 *tp)
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{
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if (tp->tg3_flags & TG3_FLAG_NVRAM) {
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int i;
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if (tp->nvram_lock_cnt == 0) {
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tw32(NVRAM_SWARB, SWARB_REQ_SET1);
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for (i = 0; i < 8000; i++) {
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if (tr32(NVRAM_SWARB) & SWARB_GNT1)
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break;
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udelay(20);
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}
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if (i == 8000) {
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tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
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return -ENODEV;
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}
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}
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tp->nvram_lock_cnt++;
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}
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return 0;
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}
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/* tp->lock is held. */
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static void tg3_nvram_unlock(struct tg3 *tp)
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{
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if (tp->tg3_flags & TG3_FLAG_NVRAM) {
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if (tp->nvram_lock_cnt > 0)
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tp->nvram_lock_cnt--;
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if (tp->nvram_lock_cnt == 0)
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tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
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}
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}
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/* tp->lock is held. */
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static void tg3_enable_nvram_access(struct tg3 *tp)
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{
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if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
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!(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
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u32 nvaccess = tr32(NVRAM_ACCESS);
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tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
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}
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}
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/* tp->lock is held. */
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static void tg3_disable_nvram_access(struct tg3 *tp)
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{
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if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
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!(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
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u32 nvaccess = tr32(NVRAM_ACCESS);
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tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
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}
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}
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static void tg3_ape_send_event(struct tg3 *tp, u32 event)
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{
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int i;
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@ -8394,10 +8527,6 @@ static int tg3_get_eeprom_len(struct net_device *dev)
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return tp->nvram_size;
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}
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static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
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static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val);
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static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
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static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
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{
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struct tg3 *tp = netdev_priv(dev);
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@ -10511,141 +10640,6 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
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}
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}
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static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
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u32 offset, u32 *val)
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{
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u32 tmp;
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int i;
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if (offset > EEPROM_ADDR_ADDR_MASK ||
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(offset % 4) != 0)
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return -EINVAL;
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tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
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EEPROM_ADDR_DEVID_MASK |
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EEPROM_ADDR_READ);
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tw32(GRC_EEPROM_ADDR,
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tmp |
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(0 << EEPROM_ADDR_DEVID_SHIFT) |
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((offset << EEPROM_ADDR_ADDR_SHIFT) &
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EEPROM_ADDR_ADDR_MASK) |
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EEPROM_ADDR_READ | EEPROM_ADDR_START);
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for (i = 0; i < 1000; i++) {
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tmp = tr32(GRC_EEPROM_ADDR);
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if (tmp & EEPROM_ADDR_COMPLETE)
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break;
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msleep(1);
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}
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if (!(tmp & EEPROM_ADDR_COMPLETE))
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return -EBUSY;
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*val = tr32(GRC_EEPROM_DATA);
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return 0;
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}
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#define NVRAM_CMD_TIMEOUT 10000
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static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
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{
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int i;
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tw32(NVRAM_CMD, nvram_cmd);
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for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
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udelay(10);
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if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
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udelay(10);
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break;
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}
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}
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if (i == NVRAM_CMD_TIMEOUT) {
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return -EBUSY;
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}
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return 0;
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}
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static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
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{
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if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
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(tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
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(tp->tg3_flags2 & TG3_FLG2_FLASH) &&
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!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
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(tp->nvram_jedecnum == JEDEC_ATMEL))
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addr = ((addr / tp->nvram_pagesize) <<
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ATMEL_AT45DB0X1B_PAGE_POS) +
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(addr % tp->nvram_pagesize);
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return addr;
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}
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static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
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{
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if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
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(tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
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(tp->tg3_flags2 & TG3_FLG2_FLASH) &&
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!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
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(tp->nvram_jedecnum == JEDEC_ATMEL))
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addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
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tp->nvram_pagesize) +
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(addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
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return addr;
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}
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static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
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{
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int ret;
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if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
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return tg3_nvram_read_using_eeprom(tp, offset, val);
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offset = tg3_nvram_phys_addr(tp, offset);
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if (offset > NVRAM_ADDR_MSK)
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return -EINVAL;
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ret = tg3_nvram_lock(tp);
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if (ret)
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return ret;
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tg3_enable_nvram_access(tp);
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tw32(NVRAM_ADDR, offset);
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ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
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NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
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if (ret == 0)
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*val = swab32(tr32(NVRAM_RDDATA));
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tg3_disable_nvram_access(tp);
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tg3_nvram_unlock(tp);
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return ret;
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}
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static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val)
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{
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u32 v;
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int res = tg3_nvram_read(tp, offset, &v);
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if (!res)
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*val = cpu_to_le32(v);
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return res;
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}
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static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
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{
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int err;
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u32 tmp;
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err = tg3_nvram_read(tp, offset, &tmp);
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*val = swab32(tmp);
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return err;
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}
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static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
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u32 offset, u32 len, u8 *buf)
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{
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