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arm64: dts: allwinner: a64: Add A64 CSI controller 

Add dts node details for Allwinner A64 CSI controller.

A64 CSI has similar features as like in H3, but the CSI_SCLK
need to update it to 300MHz than default clock rate.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This commit is contained in:
Jagan Teki 2019-01-28 14:28:45 +05:30 committed by Maxime Ripard
parent 52d9bcb3d0
commit ff29f13e93
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GPG Key ID: E3EF0D6F671851C5
1 changed files with 20 additions and 0 deletions
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@ -559,6 +559,12 @@
interrupt-controller; interrupt-controller;
#interrupt-cells = <3>; #interrupt-cells = <3>;
csi_pins: csi-pins {
pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
"PE7", "PE8", "PE9", "PE10", "PE11";
function = "csi";
};
i2c0_pins: i2c0_pins { i2c0_pins: i2c0_pins {
pins = "PH0", "PH1"; pins = "PH0", "PH1";
function = "i2c0"; function = "i2c0";
@ -926,6 +932,20 @@
status = "disabled"; status = "disabled";
}; };
csi: csi@1cb0000 {
compatible = "allwinner,sun50i-a64-csi";
reg = <0x01cb0000 0x1000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CSI>,
<&ccu CLK_CSI_SCLK>,
<&ccu CLK_DRAM_CSI>;
clock-names = "bus", "mod", "ram";
resets = <&ccu RST_BUS_CSI>;
pinctrl-names = "default";
pinctrl-0 = <&csi_pins>;
status = "disabled";
};
hdmi: hdmi@1ee0000 { hdmi: hdmi@1ee0000 {
compatible = "allwinner,sun50i-a64-dw-hdmi", compatible = "allwinner,sun50i-a64-dw-hdmi",
"allwinner,sun8i-a83t-dw-hdmi"; "allwinner,sun8i-a83t-dw-hdmi";