spi: tegra: use reset framework
Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org> Reviewed-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Stephen Warren
parent
c0df5bf536
commit
ff2251e3de
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@ -448,6 +448,7 @@ config SPI_MXS
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config SPI_TEGRA114
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tristate "NVIDIA Tegra114 SPI Controller"
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depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
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depends on RESET_CONTROLLER
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help
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SPI driver for NVIDIA Tegra114 SPI Controller interface. This controller
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is different than the older SoCs SPI controller and also register interface
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@ -456,6 +457,7 @@ config SPI_TEGRA114
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config SPI_TEGRA20_SFLASH
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tristate "Nvidia Tegra20 Serial flash Controller"
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depends on ARCH_TEGRA || COMPILE_TEST
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depends on RESET_CONTROLLER
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help
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SPI driver for Nvidia Tegra20 Serial flash Controller interface.
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The main usecase of this controller is to use spi flash as boot
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@ -464,6 +466,7 @@ config SPI_TEGRA20_SFLASH
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config SPI_TEGRA20_SLINK
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tristate "Nvidia Tegra20/Tegra30 SLINK Controller"
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depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
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depends on RESET_CONTROLLER
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help
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SPI driver for Nvidia Tegra20/Tegra30 SLINK Controller interface.
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@ -17,7 +17,6 @@
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*/
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#include <linux/clk.h>
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#include <linux/clk/tegra.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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@ -34,6 +33,7 @@
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/reset.h>
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#include <linux/spi/spi.h>
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#define SPI_COMMAND1 0x000
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@ -174,6 +174,7 @@ struct tegra_spi_data {
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spinlock_t lock;
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struct clk *clk;
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struct reset_control *rst;
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void __iomem *base;
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phys_addr_t phys;
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unsigned irq;
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@ -918,9 +919,9 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
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tspi->status_reg);
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dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
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tspi->command1_reg, tspi->dma_control_reg);
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tegra_periph_reset_assert(tspi->clk);
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reset_control_assert(tspi->rst);
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udelay(2);
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tegra_periph_reset_deassert(tspi->clk);
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reset_control_deassert(tspi->rst);
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complete(&tspi->xfer_completion);
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goto exit;
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}
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@ -990,9 +991,9 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
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tspi->status_reg);
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dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
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tspi->command1_reg, tspi->dma_control_reg);
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tegra_periph_reset_assert(tspi->clk);
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reset_control_assert(tspi->rst);
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udelay(2);
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tegra_periph_reset_deassert(tspi->clk);
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reset_control_deassert(tspi->rst);
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complete(&tspi->xfer_completion);
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spin_unlock_irqrestore(&tspi->lock, flags);
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return IRQ_HANDLED;
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@ -1127,6 +1128,13 @@ static int tegra_spi_probe(struct platform_device *pdev)
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goto exit_free_irq;
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}
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tspi->rst = devm_reset_control_get(&pdev->dev, "spi");
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if (IS_ERR(tspi->rst)) {
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dev_err(&pdev->dev, "can not get reset\n");
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ret = PTR_ERR(tspi->rst);
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goto exit_free_irq;
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}
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tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
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tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
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@ -32,8 +32,8 @@
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/reset.h>
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#include <linux/spi/spi.h>
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#include <linux/clk/tegra.h>
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#define SPI_COMMAND 0x000
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#define SPI_GO BIT(30)
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@ -118,6 +118,7 @@ struct tegra_sflash_data {
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spinlock_t lock;
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struct clk *clk;
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struct reset_control *rst;
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void __iomem *base;
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unsigned irq;
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u32 spi_max_frequency;
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@ -389,9 +390,9 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_sflash_data *tsd)
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dev_err(tsd->dev,
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"CpuXfer 0x%08x:0x%08x\n", tsd->command_reg,
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tsd->dma_control_reg);
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tegra_periph_reset_assert(tsd->clk);
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reset_control_assert(tsd->rst);
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udelay(2);
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tegra_periph_reset_deassert(tsd->clk);
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reset_control_deassert(tsd->rst);
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complete(&tsd->xfer_completion);
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goto exit;
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}
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@ -505,6 +506,13 @@ static int tegra_sflash_probe(struct platform_device *pdev)
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goto exit_free_irq;
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}
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tsd->rst = devm_reset_control_get(&pdev->dev, "spi");
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if (IS_ERR(tsd->rst)) {
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dev_err(&pdev->dev, "can not get reset\n");
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ret = PTR_ERR(tsd->rst);
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goto exit_free_irq;
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}
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init_completion(&tsd->xfer_completion);
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pm_runtime_enable(&pdev->dev);
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if (!pm_runtime_enabled(&pdev->dev)) {
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@ -520,9 +528,9 @@ static int tegra_sflash_probe(struct platform_device *pdev)
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}
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/* Reset controller */
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tegra_periph_reset_assert(tsd->clk);
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reset_control_assert(tsd->rst);
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udelay(2);
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tegra_periph_reset_deassert(tsd->clk);
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reset_control_deassert(tsd->rst);
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tsd->def_command_reg = SPI_M_S | SPI_CS_SW;
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tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);
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@ -33,8 +33,8 @@
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/reset.h>
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#include <linux/spi/spi.h>
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#include <linux/clk/tegra.h>
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#define SLINK_COMMAND 0x000
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#define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
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@ -167,6 +167,7 @@ struct tegra_slink_data {
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spinlock_t lock;
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struct clk *clk;
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struct reset_control *rst;
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void __iomem *base;
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phys_addr_t phys;
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unsigned irq;
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@ -884,9 +885,9 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi)
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dev_err(tspi->dev,
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"CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
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tspi->command2_reg, tspi->dma_control_reg);
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tegra_periph_reset_assert(tspi->clk);
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reset_control_assert(tspi->rst);
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udelay(2);
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tegra_periph_reset_deassert(tspi->clk);
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reset_control_deassert(tspi->rst);
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complete(&tspi->xfer_completion);
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goto exit;
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}
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@ -957,9 +958,9 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi)
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dev_err(tspi->dev,
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"DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
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tspi->command2_reg, tspi->dma_control_reg);
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tegra_periph_reset_assert(tspi->clk);
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reset_control_assert(tspi->rst);
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udelay(2);
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tegra_periph_reset_deassert(tspi->clk);
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reset_control_assert(tspi->rst);
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complete(&tspi->xfer_completion);
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spin_unlock_irqrestore(&tspi->lock, flags);
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return IRQ_HANDLED;
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@ -1118,6 +1119,13 @@ static int tegra_slink_probe(struct platform_device *pdev)
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goto exit_free_irq;
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}
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tspi->rst = devm_reset_control_get(&pdev->dev, "spi");
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if (IS_ERR(tspi->rst)) {
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dev_err(&pdev->dev, "can not get reset\n");
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ret = PTR_ERR(tspi->rst);
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goto exit_free_irq;
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}
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tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
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tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
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