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mtd: nand: davinci: fix the binding documentation 

Since the aemif driver conversion to DT along with
its movement to drivers/ folder is not yet done,
fix NAND binding documentation to have NAND specific
DT details only.

Signed-off-by: Kumar, Anil <anilkumar.v@ti.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
Kumar, Anil 2012-12-07 14:39:34 +05:30 committed by Grant Likely
parent 0c955b392a
commit fed16bba87
1 changed files with 12 additions and 25 deletions
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37
Documentation/devicetree/bindings/arm/davinci/nand.txt
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@ -23,29 +23,16 @@ Recommended properties :
- ti,davinci-nand-buswidth: buswidth 8 or 16 - ti,davinci-nand-buswidth: buswidth 8 or 16
- ti,davinci-nand-use-bbt: use flash based bad block table support. - ti,davinci-nand-use-bbt: use flash based bad block table support.
Example (enbw_cmc board): Example(da850 EVM ):
aemif@60000000 { nand_cs3@62000000 {
compatible = "ti,davinci-aemif"; compatible = "ti,davinci-nand";
#address-cells = <2>; reg = <0x62000000 0x807ff
#size-cells = <1>; 0x68000000 0x8000>;
reg = <0x68000000 0x80000>; ti,davinci-chipselect = <1>;
ranges = <2 0 0x60000000 0x02000000 ti,davinci-mask-ale = <0>;
3 0 0x62000000 0x02000000 ti,davinci-mask-cle = <0>;
4 0 0x64000000 0x02000000 ti,davinci-mask-chipsel = <0>;
5 0 0x66000000 0x02000000 ti,davinci-ecc-mode = "hw";
6 0 0x68000000 0x02000000>; ti,davinci-ecc-bits = <4>;
nand@3,0 { ti,davinci-nand-use-bbt;
compatible = "ti,davinci-nand";
reg = <3 0x0 0x807ff
6 0x0 0x8000>;
#address-cells = <1>;
#size-cells = <1>;
ti,davinci-chipselect = <1>;
ti,davinci-mask-ale = <0>;
ti,davinci-mask-cle = <0>;
ti,davinci-mask-chipsel = <0>;
ti,davinci-ecc-mode = "hw";
ti,davinci-ecc-bits = <4>;
ti,davinci-nand-use-bbt;
};
}; };