From 2d7945100b1ade1de73ddc397c17d0c40b278fb4 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sun, 10 Mar 2013 15:56:30 +0100 Subject: [PATCH 1/3] ARM: sunxi: Add the Allwinner A31 compatible to the machine definition The Allwinner A31 is a quad-Cortex-A7 based SoC, which shares a lot of IPs with the previous SoCs from Allwinner, like the PIO, I2C, UARTs, timers, watchdog IPs, but also differs by dropping the WEMAC ethernet controller and most notably dropping the in-house IRQ controller in favor of a ARM GIC one. Signed-off-by: Maxime Ripard --- arch/arm/mach-sunxi/Kconfig | 2 ++ arch/arm/mach-sunxi/sunxi.c | 1 + 2 files changed, 3 insertions(+) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 5b045e302b43..3ab2f65f8a50 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -10,3 +10,5 @@ config ARCH_SUNXI select SPARSE_IRQ select SUN4I_TIMER select PINCTRL_SUNXI + select ARM_GIC + select HAVE_SMP diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index 38a3c55527c8..11326d9f13da 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -96,6 +96,7 @@ static const char * const sunxi_board_dt_compat[] = { "allwinner,sun4i-a10", "allwinner,sun5i-a10s", "allwinner,sun5i-a13", + "allwinner,sun6i-a31", NULL, }; From 06d71bcfee91b2be105f43c85fcd3960e179818b Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 11 Mar 2013 20:21:11 +0100 Subject: [PATCH 2/3] ARM: sun6i: Add restart code for the A31 The Allwinner A31 has a different watchdog, with a slightly different register layout, that requires a different restart code. Signed-off-by: Maxime Ripard --- .../watchdog/{sun4i-wdt.txt => sunxi-wdt.txt} | 5 ++- arch/arm/mach-sunxi/sunxi.c | 43 +++++++++++++++++-- 2 files changed, 43 insertions(+), 5 deletions(-) rename Documentation/devicetree/bindings/watchdog/{sun4i-wdt.txt => sunxi-wdt.txt} (56%) diff --git a/Documentation/devicetree/bindings/watchdog/sun4i-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt similarity index 56% rename from Documentation/devicetree/bindings/watchdog/sun4i-wdt.txt rename to Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt index ecd650adff31..e39cb266c8f4 100644 --- a/Documentation/devicetree/bindings/watchdog/sun4i-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt @@ -1,8 +1,9 @@ -Allwinner sun4i Watchdog timer +Allwinner SoCs Watchdog timer Required properties: -- compatible : should be "allwinner,sun4i-wdt" +- compatible : should be "allwinner,-wdt", the currently supported + SoC families being sun4i and sun6i - reg : Specifies base physical address and size of the registers. Example: diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index 11326d9f13da..223995e0481f 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -27,10 +27,19 @@ #include #define SUN4I_WATCHDOG_CTRL_REG 0x00 -#define SUN4I_WATCHDOG_CTRL_RESTART (1 << 0) +#define SUN4I_WATCHDOG_CTRL_RESTART BIT(0) #define SUN4I_WATCHDOG_MODE_REG 0x04 -#define SUN4I_WATCHDOG_MODE_ENABLE (1 << 0) -#define SUN4I_WATCHDOG_MODE_RESET_ENABLE (1 << 1) +#define SUN4I_WATCHDOG_MODE_ENABLE BIT(0) +#define SUN4I_WATCHDOG_MODE_RESET_ENABLE BIT(1) + +#define SUN6I_WATCHDOG1_IRQ_REG 0x00 +#define SUN6I_WATCHDOG1_CTRL_REG 0x10 +#define SUN6I_WATCHDOG1_CTRL_RESTART BIT(0) +#define SUN6I_WATCHDOG1_CONFIG_REG 0x14 +#define SUN6I_WATCHDOG1_CONFIG_RESTART BIT(0) +#define SUN6I_WATCHDOG1_CONFIG_IRQ BIT(1) +#define SUN6I_WATCHDOG1_MODE_REG 0x18 +#define SUN6I_WATCHDOG1_MODE_ENABLE BIT(0) static void __iomem *wdt_base; @@ -56,8 +65,36 @@ static void sun4i_restart(enum reboot_mode mode, const char *cmd) } } +static void sun6i_restart(enum reboot_mode mode, const char *cmd) +{ + if (!wdt_base) + return; + + /* Disable interrupts */ + writel(0, wdt_base + SUN6I_WATCHDOG1_IRQ_REG); + + /* We want to disable the IRQ and just reset the whole system */ + writel(SUN6I_WATCHDOG1_CONFIG_RESTART, + wdt_base + SUN6I_WATCHDOG1_CONFIG_REG); + + /* Enable timer. The default and lowest interval value is 0.5s */ + writel(SUN6I_WATCHDOG1_MODE_ENABLE, + wdt_base + SUN6I_WATCHDOG1_MODE_REG); + + /* Restart the watchdog. */ + writel(SUN6I_WATCHDOG1_CTRL_RESTART, + wdt_base + SUN6I_WATCHDOG1_CTRL_REG); + + while (1) { + mdelay(5); + writel(SUN6I_WATCHDOG1_MODE_ENABLE, + wdt_base + SUN6I_WATCHDOG1_MODE_REG); + } +} + static struct of_device_id sunxi_restart_ids[] = { { .compatible = "allwinner,sun4i-wdt", .data = sun4i_restart }, + { .compatible = "allwinner,sun6i-wdt", .data = sun6i_restart }, { /*sentinel*/ } }; From d18fd9445b18c4adf56cfc58c378c702c8edd0da Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 17 Jul 2013 09:47:18 +0200 Subject: [PATCH 3/3] ARM: sunxi: Introduce Allwinner A20 support The Allwinner A20 is a dual-core Cortex-A7-based SoC. It is pin-compatible with the A10, and re-uses most of the IPs found in it, plus some additional ones like a Gigabit Ethernet controller. Signed-off-by: Maxime Ripard --- arch/arm/mach-sunxi/sunxi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index 223995e0481f..e79fb3469341 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -134,6 +134,7 @@ static const char * const sunxi_board_dt_compat[] = { "allwinner,sun5i-a10s", "allwinner,sun5i-a13", "allwinner,sun6i-a31", + "allwinner,sun7i-a20", NULL, };