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linux-sg2042
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Merge branch 'for-linus/i2c-2638' of git://git.fluff.org/bjdooks/linux 

* 'for-linus/i2c-2638' of git://git.fluff.org/bjdooks/linux:
  i2c-bfin-twi: move setup to the earlier subsys initcall
  i2c-bfin-twi: handle faulty slave devices better
  i2c-mv64xxx: send repeated START between messages in xfer
  i2c-nomadik: fix regression on adapter name
  i2c-omap: Set latency requirements only once for several messages
  i2c-eg20t: add driver for Intel EG20T
  i2c-ocores: add some device tree documentation
  i2c-ocores: Use devres for resource allocation
  i2c-ocores: Adapt for device tree
  i2c-iop3xx: add iomem annotation
This commit is contained in:
Linus Torvalds 2011-01-13 10:40:57 -08:00
parent d20056032e dad92924ea
commit fe3c560b8a
10 changed files with 1086 additions and 61 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/i2c/busses/Kconfig
View File

@ -638,6 +638,14 @@ config I2C_XILINX
This driver can also be built as a module. If so, the module
will be called xilinx_i2c.
config I2C_EG20T
tristate "PCH I2C of Intel EG20T"
depends on PCI
help
This driver is for PCH(Platform controller Hub) I2C of EG20T which
is an IOH(Input/Output Hub) for x86 embedded processor.
This driver can access PCH I2C bus device.
comment "External I2C/SMBus adapter drivers"
config I2C_PARPORT

1
drivers/i2c/busses/Makefile
View File

@ -61,6 +61,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o

24
drivers/i2c/busses/i2c-bfin-twi.c
View File

@ -20,6 +20,7 @@
#include <linux/completion.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <asm/blackfin.h>
#include <asm/portmux.h>
@ -159,6 +160,27 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
if (mast_stat & BUFWRERR)
dev_dbg(&iface->adap.dev, "Buffer Write Error\n");
/* Faulty slave devices, may drive SDA low after a transfer
* finishes. To release the bus this code generates up to 9
* extra clocks until SDA is released.
*/
if (read_MASTER_STAT(iface) & SDASEN) {
int cnt = 9;
do {
write_MASTER_CTL(iface, SCLOVR);
udelay(6);
write_MASTER_CTL(iface, 0);
udelay(6);
} while ((read_MASTER_STAT(iface) & SDASEN) && cnt--);
write_MASTER_CTL(iface, SDAOVR | SCLOVR);
udelay(6);
write_MASTER_CTL(iface, SDAOVR);
udelay(6);
write_MASTER_CTL(iface, 0);
}
/* If it is a quick transfer, only address without data,
* not an err, return 1.
*/
@ -760,7 +782,7 @@ static void __exit i2c_bfin_twi_exit(void)
platform_driver_unregister(&i2c_bfin_twi_driver);
}
module_init(i2c_bfin_twi_init);
subsys_initcall(i2c_bfin_twi_init);
module_exit(i2c_bfin_twi_exit);
MODULE_AUTHOR("Bryan Wu, Sonic Zhang");

900
drivers/i2c/busses/i2c-eg20t.c Normal file
View File

@ -0,0 +1,900 @@
/*
* Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/i2c.h>
#include <linux/fs.h>
#include <linux/io.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/jiffies.h>
#include <linux/pci.h>
#include <linux/mutex.h>
#include <linux/ktime.h>
#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
#define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
#define PCH_I2CSADR 0x00 /* I2C slave address register */
#define PCH_I2CCTL 0x04 /* I2C control register */
#define PCH_I2CSR 0x08 /* I2C status register */
#define PCH_I2CDR 0x0C /* I2C data register */
#define PCH_I2CMON 0x10 /* I2C bus monitor register */
#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
#define PCH_I2CMOD 0x18 /* I2C mode register */
#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
#define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
#define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
#define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
#define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
#define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
#define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
#define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
#define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
#define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
#define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
#define PCH_I2CTMR 0x48 /* I2C timer register */
#define PCH_I2CSRST 0xFC /* I2C reset register */
#define PCH_I2CNF 0xF8 /* I2C noise filter register */
#define BUS_IDLE_TIMEOUT 20
#define PCH_I2CCTL_I2CMEN 0x0080
#define TEN_BIT_ADDR_DEFAULT 0xF000
#define TEN_BIT_ADDR_MASK 0xF0
#define PCH_START 0x0020
#define PCH_ESR_START 0x0001
#define PCH_BUFF_START 0x1
#define PCH_REPSTART 0x0004
#define PCH_ACK 0x0008
#define PCH_GETACK 0x0001
#define CLR_REG 0x0
#define I2C_RD 0x1
#define I2CMCF_BIT 0x0080
#define I2CMIF_BIT 0x0002
#define I2CMAL_BIT 0x0010
#define I2CBMFI_BIT 0x0001
#define I2CBMAL_BIT 0x0002
#define I2CBMNA_BIT 0x0004
#define I2CBMTO_BIT 0x0008
#define I2CBMIS_BIT 0x0010
#define I2CESRFI_BIT 0X0001
#define I2CESRTO_BIT 0x0002
#define I2CESRFIIE_BIT 0x1
#define I2CESRTOIE_BIT 0x2
#define I2CBMDZ_BIT 0x0040
#define I2CBMAG_BIT 0x0020
#define I2CMBB_BIT 0x0020
#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
I2CBMTO_BIT | I2CBMIS_BIT)
#define I2C_ADDR_MSK 0xFF
#define I2C_MSB_2B_MSK 0x300
#define FAST_MODE_CLK 400
#define FAST_MODE_EN 0x0001
#define SUB_ADDR_LEN_MAX 4
#define BUF_LEN_MAX 32
#define PCH_BUFFER_MODE 0x1
#define EEPROM_SW_RST_MODE 0x0002
#define NORMAL_INTR_ENBL 0x0300
#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
#define EEPROM_RST_INTR_DISBL 0x0
#define BUFFER_MODE_INTR_ENBL 0x001F
#define BUFFER_MODE_INTR_DISBL 0x0
#define NORMAL_MODE 0x0
#define BUFFER_MODE 0x1
#define EEPROM_SR_MODE 0x2
#define I2C_TX_MODE 0x0010
#define PCH_BUF_TX 0xFFF7
#define PCH_BUF_RD 0x0008
#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
#define I2CMAL_EVENT 0x0001
#define I2CMCF_EVENT 0x0002
#define I2CBMFI_EVENT 0x0004
#define I2CBMAL_EVENT 0x0008
#define I2CBMNA_EVENT 0x0010
#define I2CBMTO_EVENT 0x0020
#define I2CBMIS_EVENT 0x0040
#define I2CESRFI_EVENT 0x0080
#define I2CESRTO_EVENT 0x0100
#define PCI_DEVICE_ID_PCH_I2C 0x8817
#define pch_dbg(adap, fmt, arg...) \
dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
#define pch_err(adap, fmt, arg...) \
dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
#define pch_pci_err(pdev, fmt, arg...) \
dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
#define pch_pci_dbg(pdev, fmt, arg...) \
dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
/**
* struct i2c_algo_pch_data - for I2C driver functionalities
* @pch_adapter: stores the reference to i2c_adapter structure
* @p_adapter_info: stores the reference to adapter_info structure
* @pch_base_address: specifies the remapped base address
* @pch_buff_mode_en: specifies if buffer mode is enabled
* @pch_event_flag: specifies occurrence of interrupt events
* @pch_i2c_xfer_in_progress: specifies whether the transfer is completed
*/
struct i2c_algo_pch_data {
struct i2c_adapter pch_adapter;
struct adapter_info *p_adapter_info;
void __iomem *pch_base_address;
int pch_buff_mode_en;
u32 pch_event_flag;
bool pch_i2c_xfer_in_progress;
};
/**
* struct adapter_info - This structure holds the adapter information for the
PCH i2c controller
* @pch_data: stores a list of i2c_algo_pch_data
* @pch_i2c_suspended: specifies whether the system is suspended or not
* perhaps with more lines and words.
*
* pch_data has as many elements as maximum I2C channels
*/
struct adapter_info {
struct i2c_algo_pch_data pch_data;
bool pch_i2c_suspended;
};
static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
static wait_queue_head_t pch_event;
static DEFINE_MUTEX(pch_mutex);
static struct pci_device_id __devinitdata pch_pcidev_id[] = {
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)},
{0,}
};
static irqreturn_t pch_i2c_handler(int irq, void *pData);
static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
{
u32 val;
val = ioread32(addr + offset);
val |= bitmask;
iowrite32(val, addr + offset);
}
static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
{
u32 val;
val = ioread32(addr + offset);
val &= (~bitmask);
iowrite32(val, addr + offset);
}
/**
* pch_i2c_init() - hardware initialization of I2C module
* @adap: Pointer to struct i2c_algo_pch_data.
*/
static void pch_i2c_init(struct i2c_algo_pch_data *adap)
{
void __iomem *p = adap->pch_base_address;
u32 pch_i2cbc;
u32 pch_i2ctmr;
u32 reg_value;
/* reset I2C controller */
iowrite32(0x01, p + PCH_I2CSRST);
msleep(20);
iowrite32(0x0, p + PCH_I2CSRST);
/* Initialize I2C registers */
iowrite32(0x21, p + PCH_I2CNF);
pch_setbit(adap->pch_base_address, PCH_I2CCTL,
PCH_I2CCTL_I2CMEN);
if (pch_i2c_speed != 400)
pch_i2c_speed = 100;
reg_value = PCH_I2CCTL_I2CMEN;
if (pch_i2c_speed == FAST_MODE_CLK) {
reg_value |= FAST_MODE_EN;
pch_dbg(adap, "Fast mode enabled\n");
}
if (pch_clk > PCH_MAX_CLK)
pch_clk = 62500;
pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / pch_i2c_speed * 8;
/* Set transfer speed in I2CBC */
iowrite32(pch_i2cbc, p + PCH_I2CBC);
pch_i2ctmr = (pch_clk) / 8;
iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
iowrite32(reg_value, p + PCH_I2CCTL);
pch_dbg(adap,
"I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
init_waitqueue_head(&pch_event);
}
static inline bool ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
{
return cmp1.tv64 < cmp2.tv64;
}
/**
* pch_i2c_wait_for_bus_idle() - check the status of bus.
* @adap: Pointer to struct i2c_algo_pch_data.
* @timeout: waiting time counter (us).
*/
static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
s32 timeout)
{
void __iomem *p = adap->pch_base_address;
/* MAX timeout value is timeout*1000*1000nsec */
ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
do {
if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
break;
msleep(20);
} while (ktime_lt(ktime_get(), ns_val));
pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
if (timeout == 0) {
pch_err(adap, "%s: Timeout Error.return%d\n", __func__, -ETIME);
return -ETIME;
}
return 0;
}
/**
* pch_i2c_start() - Generate I2C start condition in normal mode.
* @adap: Pointer to struct i2c_algo_pch_data.
*
* Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
*/
static void pch_i2c_start(struct i2c_algo_pch_data *adap)
{
void __iomem *p = adap->pch_base_address;
pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
}
/**
* pch_i2c_wait_for_xfer_complete() - initiates a wait for the tx complete event
* @adap: Pointer to struct i2c_algo_pch_data.
*/
static s32 pch_i2c_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
{
s32 ret;
ret = wait_event_timeout(pch_event,
(adap->pch_event_flag != 0), msecs_to_jiffies(50));
if (ret < 0) {
pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
return ret;
}
if (ret == 0) {
pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
return -ETIMEDOUT;
}
if (adap->pch_event_flag & I2C_ERROR_MASK) {
pch_err(adap, "error bits set: %x\n", adap->pch_event_flag);
return -EIO;
}
adap->pch_event_flag = 0;
return 0;
}
/**
* pch_i2c_getack() - to confirm ACK/NACK
* @adap: Pointer to struct i2c_algo_pch_data.
*/
static s32 pch_i2c_getack(struct i2c_algo_pch_data *adap)
{
u32 reg_val;
void __iomem *p = adap->pch_base_address;
reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
if (reg_val != 0) {
pch_err(adap, "return%d\n", -EPROTO);
return -EPROTO;
}
return 0;
}
/**
* pch_i2c_stop() - generate stop condition in normal mode.
* @adap: Pointer to struct i2c_algo_pch_data.
*/
static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
{
void __iomem *p = adap->pch_base_address;
pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
/* clear the start bit */
pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
}
/**
* pch_i2c_repstart() - generate repeated start condition in normal mode
* @adap: Pointer to struct i2c_algo_pch_data.
*/
static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
{
void __iomem *p = adap->pch_base_address;
pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
}
/**
* pch_i2c_writebytes() - write data to I2C bus in normal mode
* @i2c_adap: Pointer to the struct i2c_adapter.
* @last: specifies whether last message or not.
* In the case of compound mode it will be 1 for last message,
* otherwise 0.
* @first: specifies whether first message or not.
* 1 for first message otherwise 0.
*/
static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
struct i2c_msg *msgs, u32 last, u32 first)
{
struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
u8 *buf;
u32 length;
u32 addr;
u32 addr_2_msb;
u32 addr_8_lsb;
s32 wrcount;
void __iomem *p = adap->pch_base_address;
length = msgs->len;
buf = msgs->buf;
addr = msgs->addr;
/* enable master tx */
pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
length);
if (first) {
if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
return -ETIME;
}
if (msgs->flags & I2C_M_TEN) {
addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
if (first)
pch_i2c_start(adap);
if (pch_i2c_wait_for_xfer_complete(adap) == 0 &&
pch_i2c_getack(adap) == 0) {
addr_8_lsb = (addr & I2C_ADDR_MSK);
iowrite32(addr_8_lsb, p + PCH_I2CDR);
} else {
pch_i2c_stop(adap);
return -ETIME;
}
} else {
/* set 7 bit slave address and R/W bit as 0 */
iowrite32(addr << 1, p + PCH_I2CDR);
if (first)
pch_i2c_start(adap);
}
if ((pch_i2c_wait_for_xfer_complete(adap) == 0) &&
(pch_i2c_getack(adap) == 0)) {
for (wrcount = 0; wrcount < length; ++wrcount) {
/* write buffer value to I2C data register */
iowrite32(buf[wrcount], p + PCH_I2CDR);
pch_dbg(adap, "writing %x to Data register\n",
buf[wrcount]);
if (pch_i2c_wait_for_xfer_complete(adap) != 0)
return -ETIME;
if (pch_i2c_getack(adap))
return -EIO;
}
/* check if this is the last message */
if (last)
pch_i2c_stop(adap);
else
pch_i2c_repstart(adap);
} else {
pch_i2c_stop(adap);
return -EIO;
}
pch_dbg(adap, "return=%d\n", wrcount);
return wrcount;
}
/**
* pch_i2c_sendack() - send ACK
* @adap: Pointer to struct i2c_algo_pch_data.
*/
static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
{
void __iomem *p = adap->pch_base_address;
pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
}
/**
* pch_i2c_sendnack() - send NACK
* @adap: Pointer to struct i2c_algo_pch_data.
*/
static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
{
void __iomem *p = adap->pch_base_address;
pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
}
/**
* pch_i2c_readbytes() - read data from I2C bus in normal mode.
* @i2c_adap: Pointer to the struct i2c_adapter.
* @msgs: Pointer to i2c_msg structure.
* @last: specifies whether last message or not.
* @first: specifies whether first message or not.
*/
s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
u32 last, u32 first)
{
struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
u8 *buf;
u32 count;
u32 length;
u32 addr;
u32 addr_2_msb;
void __iomem *p = adap->pch_base_address;
length = msgs->len;
buf = msgs->buf;
addr = msgs->addr;
/* enable master reception */
pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
if (first) {
if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
return -ETIME;
}
if (msgs->flags & I2C_M_TEN) {
addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
} else {
/* 7 address bits + R/W bit */
addr = (((addr) << 1) | (I2C_RD));
iowrite32(addr, p + PCH_I2CDR);
}
/* check if it is the first message */
if (first)
pch_i2c_start(adap);
if ((pch_i2c_wait_for_xfer_complete(adap) == 0) &&
(pch_i2c_getack(adap) == 0)) {
pch_dbg(adap, "return %d\n", 0);
if (length == 0) {
pch_i2c_stop(adap);
ioread32(p + PCH_I2CDR); /* Dummy read needs */
count = length;
} else {
int read_index;
int loop;
pch_i2c_sendack(adap);
/* Dummy read */
for (loop = 1, read_index = 0; loop < length; loop++) {
buf[read_index] = ioread32(p + PCH_I2CDR);
if (loop != 1)
read_index++;
if (pch_i2c_wait_for_xfer_complete(adap) != 0) {
pch_i2c_stop(adap);
return -ETIME;
}
} /* end for */
pch_i2c_sendnack(adap);
buf[read_index] = ioread32(p + PCH_I2CDR);
if (length != 1)
read_index++;
if (pch_i2c_wait_for_xfer_complete(adap) == 0) {
if (last)
pch_i2c_stop(adap);
else
pch_i2c_repstart(adap);
buf[read_index++] = ioread32(p + PCH_I2CDR);
count = read_index;
} else {
count = -ETIME;
}
}
} else {
count = -ETIME;
pch_i2c_stop(adap);
}
return count;
}
/**
* pch_i2c_cb_ch0() - Interrupt handler Call back function
* @adap: Pointer to struct i2c_algo_pch_data.
*/
static void pch_i2c_cb_ch0(struct i2c_algo_pch_data *adap)
{
u32 sts;
void __iomem *p = adap->pch_base_address;
sts = ioread32(p + PCH_I2CSR);
sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
if (sts & I2CMAL_BIT)
adap->pch_event_flag |= I2CMAL_EVENT;
if (sts & I2CMCF_BIT)
adap->pch_event_flag |= I2CMCF_EVENT;
/* clear the applicable bits */
pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
wake_up(&pch_event);
}
/**
* pch_i2c_handler() - interrupt handler for the PCH I2C controller
* @irq: irq number.
* @pData: cookie passed back to the handler function.
*/
static irqreturn_t pch_i2c_handler(int irq, void *pData)
{
s32 reg_val;
struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
void __iomem *p = adap_data->pch_base_address;
u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
if (mode != NORMAL_MODE) {
pch_err(adap_data, "I2C mode is not supported\n");
return IRQ_NONE;
}
reg_val = ioread32(p + PCH_I2CSR);
if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
pch_i2c_cb_ch0(adap_data);
else
return IRQ_NONE;
return IRQ_HANDLED;
}
/**
* pch_i2c_xfer() - Reading adnd writing data through I2C bus
* @i2c_adap: Pointer to the struct i2c_adapter.
* @msgs: Pointer to i2c_msg structure.
* @num: number of messages.
*/
static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
struct i2c_msg *msgs, s32 num)
{
struct i2c_msg *pmsg;
u32 i = 0;
u32 status;
u32 msglen;
u32 subaddrlen;
s32 ret;
struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
ret = mutex_lock_interruptible(&pch_mutex);
if (ret)
return -ERESTARTSYS;
if (adap->p_adapter_info->pch_i2c_suspended) {
mutex_unlock(&pch_mutex);
return -EBUSY;
}
pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
adap->p_adapter_info->pch_i2c_suspended);
/* transfer not completed */
adap->pch_i2c_xfer_in_progress = true;
pmsg = &msgs[0];
pmsg->flags |= adap->pch_buff_mode_en;
status = pmsg->flags;
pch_dbg(adap,
"After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
/* calculate sub address length and message length */
/* these are applicable only for buffer mode */
subaddrlen = pmsg->buf[0];
/* calculate actual message length excluding
* the sub address fields */
msglen = (pmsg->len) - (subaddrlen + 1);
if (status & (I2C_M_RD)) {
pch_dbg(adap, "invoking pch_i2c_readbytes\n");
ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
(i == 0));
} else {
pch_dbg(adap, "invoking pch_i2c_writebytes\n");
ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
(i == 0));
}
adap->pch_i2c_xfer_in_progress = false; /* transfer completed */
mutex_unlock(&pch_mutex);
return ret;
}
/**
* pch_i2c_func() - return the functionality of the I2C driver
* @adap: Pointer to struct i2c_algo_pch_data.
*/
static u32 pch_i2c_func(struct i2c_adapter *adap)
{
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
}
static struct i2c_algorithm pch_algorithm = {
.master_xfer = pch_i2c_xfer,
.functionality = pch_i2c_func
};
/**
* pch_i2c_disbl_int() - Disable PCH I2C interrupts
* @adap: Pointer to struct i2c_algo_pch_data.
*/
static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
{
void __iomem *p = adap->pch_base_address;
pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
}
static int __devinit pch_i2c_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
void __iomem *base_addr;
s32 ret;
struct adapter_info *adap_info;
pch_pci_dbg(pdev, "Entered.\n");
adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
if (adap_info == NULL) {
pch_pci_err(pdev, "Memory allocation FAILED\n");
return -ENOMEM;
}
ret = pci_enable_device(pdev);
if (ret) {
pch_pci_err(pdev, "pci_enable_device FAILED\n");
goto err_pci_enable;
}
ret = pci_request_regions(pdev, KBUILD_MODNAME);
if (ret) {
pch_pci_err(pdev, "pci_request_regions FAILED\n");
goto err_pci_req;
}
base_addr = pci_iomap(pdev, 1, 0);
if (base_addr == NULL) {
pch_pci_err(pdev, "pci_iomap FAILED\n");
ret = -ENOMEM;
goto err_pci_iomap;
}
adap_info->pch_i2c_suspended = false;
adap_info->pch_data.p_adapter_info = adap_info;
adap_info->pch_data.pch_adapter.owner = THIS_MODULE;
adap_info->pch_data.pch_adapter.class = I2C_CLASS_HWMON;
strcpy(adap_info->pch_data.pch_adapter.name, KBUILD_MODNAME);
adap_info->pch_data.pch_adapter.algo = &pch_algorithm;
adap_info->pch_data.pch_adapter.algo_data =
&adap_info->pch_data;
/* (i * 0x80) + base_addr; */
adap_info->pch_data.pch_base_address = base_addr;
adap_info->pch_data.pch_adapter.dev.parent = &pdev->dev;
ret = i2c_add_adapter(&(adap_info->pch_data.pch_adapter));
if (ret) {
pch_pci_err(pdev, "i2c_add_adapter FAILED\n");
goto err_i2c_add_adapter;
}
pch_i2c_init(&adap_info->pch_data);
ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
KBUILD_MODNAME, &adap_info->pch_data);
if (ret) {
pch_pci_err(pdev, "request_irq FAILED\n");
goto err_request_irq;
}
pci_set_drvdata(pdev, adap_info);
pch_pci_dbg(pdev, "returns %d.\n", ret);
return 0;
err_request_irq:
i2c_del_adapter(&(adap_info->pch_data.pch_adapter));
err_i2c_add_adapter:
pci_iounmap(pdev, base_addr);
err_pci_iomap:
pci_release_regions(pdev);
err_pci_req:
pci_disable_device(pdev);
err_pci_enable:
kfree(adap_info);
return ret;
}
static void __devexit pch_i2c_remove(struct pci_dev *pdev)
{
struct adapter_info *adap_info = pci_get_drvdata(pdev);
pch_i2c_disbl_int(&adap_info->pch_data);
free_irq(pdev->irq, &adap_info->pch_data);
i2c_del_adapter(&(adap_info->pch_data.pch_adapter));
if (adap_info->pch_data.pch_base_address) {
pci_iounmap(pdev, adap_info->pch_data.pch_base_address);
adap_info->pch_data.pch_base_address = 0;
}
pci_set_drvdata(pdev, NULL);
pci_release_regions(pdev);
pci_disable_device(pdev);
kfree(adap_info);
}
#ifdef CONFIG_PM
static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state)
{
int ret;
struct adapter_info *adap_info = pci_get_drvdata(pdev);
void __iomem *p = adap_info->pch_data.pch_base_address;
adap_info->pch_i2c_suspended = true;
while ((adap_info->pch_data.pch_i2c_xfer_in_progress)) {
/* Wait until all channel transfers are completed */
msleep(20);
}
/* Disable the i2c interrupts */
pch_i2c_disbl_int(&adap_info->pch_data);
pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
"invoked function pch_i2c_disbl_int successfully\n",
ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
ioread32(p + PCH_I2CESRSTA));
ret = pci_save_state(pdev);
if (ret) {
pch_pci_err(pdev, "pci_save_state\n");
return ret;
}
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_disable_device(pdev);
pci_set_power_state(pdev, pci_choose_state(pdev, state));
return 0;
}
static int pch_i2c_resume(struct pci_dev *pdev)
{
struct adapter_info *adap_info = pci_get_drvdata(pdev);
pci_set_power_state(pdev, PCI_D0);
pci_restore_state(pdev);
if (pci_enable_device(pdev) < 0) {
pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n");
return -EIO;
}
pci_enable_wake(pdev, PCI_D3hot, 0);
pch_i2c_init(&adap_info->pch_data);
adap_info->pch_i2c_suspended = false;
return 0;
}
#else
#define pch_i2c_suspend NULL
#define pch_i2c_resume NULL
#endif
static struct pci_driver pch_pcidriver = {
.name = KBUILD_MODNAME,
.id_table = pch_pcidev_id,
.probe = pch_i2c_probe,
.remove = __devexit_p(pch_i2c_remove),
.suspend = pch_i2c_suspend,
.resume = pch_i2c_resume
};
static int __init pch_pci_init(void)
{
return pci_register_driver(&pch_pcidriver);
}
module_init(pch_pci_init);
static void __exit pch_pci_exit(void)
{
pci_unregister_driver(&pch_pcidriver);
}
module_exit(pch_pci_exit);
MODULE_DESCRIPTION("PCH I2C PCI Driver");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Tomoya MORINAGA. <tomoya-linux@dsn.okisemi.com>");
module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
module_param(pch_clk, int, (S_IRUSR | S_IWUSR));

6
drivers/i2c/busses/i2c-iop3xx.c
View File

@ -409,7 +409,7 @@ iop3xx_i2c_remove(struct platform_device *pdev)
IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE);
__raw_writel(cr, adapter_data->ioaddr + CR_OFFSET);
iounmap((void __iomem*)adapter_data->ioaddr);
iounmap(adapter_data->ioaddr);
release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
kfree(adapter_data);
kfree(padapter);
@ -453,7 +453,7 @@ iop3xx_i2c_probe(struct platform_device *pdev)
/* set the adapter enumeration # */
adapter_data->id = i2c_id++;
adapter_data->ioaddr = (u32)ioremap(res->start, IOP3XX_I2C_IO_SIZE);
adapter_data->ioaddr = ioremap(res->start, IOP3XX_I2C_IO_SIZE);
if (!adapter_data->ioaddr) {
ret = -ENOMEM;
goto release_region;
@ -498,7 +498,7 @@ iop3xx_i2c_probe(struct platform_device *pdev)
return 0;
unmap:
iounmap((void __iomem*)adapter_data->ioaddr);
iounmap(adapter_data->ioaddr);
release_region:
release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);

2
drivers/i2c/busses/i2c-iop3xx.h
View File

@ -97,7 +97,7 @@
#define IOP3XX_I2C_IO_SIZE 0x18
struct i2c_algo_iop3xx_data {
u32 ioaddr;
void __iomem *ioaddr;
wait_queue_head_t waitq;
spinlock_t lock;
u32 SR_enabled, SR_received;

45
drivers/i2c/busses/i2c-mv64xxx.c
View File

@ -59,6 +59,7 @@ enum {
MV64XXX_I2C_STATE_INVALID,
MV64XXX_I2C_STATE_IDLE,
MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
MV64XXX_I2C_STATE_WAITING_FOR_RESTART,
MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
@ -70,6 +71,7 @@ enum {
MV64XXX_I2C_ACTION_INVALID,
MV64XXX_I2C_ACTION_CONTINUE,
MV64XXX_I2C_ACTION_SEND_START,
MV64XXX_I2C_ACTION_SEND_RESTART,
MV64XXX_I2C_ACTION_SEND_ADDR_1,
MV64XXX_I2C_ACTION_SEND_ADDR_2,
MV64XXX_I2C_ACTION_SEND_DATA,
@ -91,6 +93,7 @@ struct mv64xxx_i2c_data {
u32 addr2;
u32 bytes_left;
u32 byte_posn;
u32 send_stop;
u32 block;
int rc;
u32 freq_m;
@ -159,8 +162,15 @@ mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
if ((drv_data->bytes_left == 0)
|| (drv_data->aborting
&& (drv_data->byte_posn != 0))) {
drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
drv_data->state = MV64XXX_I2C_STATE_IDLE;
if (drv_data->send_stop) {
drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
drv_data->state = MV64XXX_I2C_STATE_IDLE;
} else {
drv_data->action =
MV64XXX_I2C_ACTION_SEND_RESTART;
drv_data->state =
MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
}
} else {
drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
drv_data->state =
@ -228,6 +238,15 @@ static void
mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
{
switch(drv_data->action) {
case MV64XXX_I2C_ACTION_SEND_RESTART:
drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_START;
drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
writel(drv_data->cntl_bits,
drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
drv_data->block = 0;
wake_up_interruptible(&drv_data->waitq);
break;
case MV64XXX_I2C_ACTION_CONTINUE:
writel(drv_data->cntl_bits,
drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
@ -386,7 +405,8 @@ mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
}
static int
mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg)
mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
int is_first, int is_last)
{
unsigned long flags;
@ -406,10 +426,18 @@ mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg)
drv_data->bytes_left--;
}
} else {
drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
if (is_first) {
drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
drv_data->state =
MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
} else {
drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
drv_data->state =
MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
}
}
drv_data->send_stop = is_last;
drv_data->block = 1;
mv64xxx_i2c_do_action(drv_data);
spin_unlock_irqrestore(&drv_data->lock, flags);
@ -437,9 +465,12 @@ mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
int i, rc;
for (i=0; i<num; i++)
if ((rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i])) < 0)
for (i = 0; i < num; i++) {
rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i],
i == 0, i + 1 == num);
if (rc < 0)
return rc;
}
return num;
}

6
drivers/i2c/busses/i2c-nomadik.c
View File

@ -872,6 +872,8 @@ static int __devinit nmk_i2c_probe(struct platform_device *pdev)
adap->owner = THIS_MODULE;
adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
adap->algo = &nmk_i2c_algo;
snprintf(adap->name, sizeof(adap->name),
"Nomadik I2C%d at %lx", pdev->id, (unsigned long)res->start);
/* fetch the controller id */
adap->nr = pdev->id;
@ -891,8 +893,8 @@ static int __devinit nmk_i2c_probe(struct platform_device *pdev)
goto err_init_hw;
}
dev_dbg(&pdev->dev, "initialize I2C%d bus on virtual "
"base %p\n", pdev->id, dev->virtbase);
dev_info(&pdev->dev, "initialize %s on virtual "
"base %p\n", adap->name, dev->virtbase);
ret = i2c_add_numbered_adapter(adap);
if (ret) {

145
drivers/i2c/busses/i2c-ocores.c
View File

@ -9,6 +9,41 @@
* kind, whether express or implied.
*/
/*
* Device tree configuration:
*
* Required properties:
* - compatible : "opencores,i2c-ocores"
* - reg : bus address start and address range size of device
* - interrupts : interrupt number
* - regstep : size of device registers in bytes
* - clock-frequency : frequency of bus clock in Hz
*
* Example:
*
* i2c0: ocores@a0000000 {
* compatible = "opencores,i2c-ocores";
* reg = <0xa0000000 0x8>;
* interrupts = <10>;
*
* regstep = <1>;
* clock-frequency = <20000000>;
*
* -- Devices connected on this I2C bus get
* -- defined here; address- and size-cells
* -- apply to these child devices
*
* #address-cells = <1>;
* #size-cells = <0>;
*
* dummy@60 {
* compatible = "dummy";
* reg = <60>;
* };
* };
*
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
@ -210,6 +245,32 @@ static struct i2c_adapter ocores_adapter = {
.algo = &ocores_algorithm,
};
#ifdef CONFIG_OF
static int ocores_i2c_of_probe(struct platform_device* pdev,
struct ocores_i2c* i2c)
{
__be32* val;
val = of_get_property(pdev->dev.of_node, "regstep", NULL);
if (!val) {
dev_err(&pdev->dev, "Missing required parameter 'regstep'");
return -ENODEV;
}
i2c->regstep = be32_to_cpup(val);
val = of_get_property(pdev->dev.of_node, "clock-frequency", NULL);
if (!val) {
dev_err(&pdev->dev,
"Missing required parameter 'clock-frequency'");
return -ENODEV;
}
i2c->clock_khz = be32_to_cpup(val) / 1000;
return 0;
}
#else
#define ocores_i2c_of_probe(pdev,i2c) -ENODEV
#endif
static int __devinit ocores_i2c_probe(struct platform_device *pdev)
{
@ -227,37 +288,41 @@ static int __devinit ocores_i2c_probe(struct platform_device *pdev)
if (!res2)
return -ENODEV;
pdata = (struct ocores_i2c_platform_data*) pdev->dev.platform_data;
if (!pdata)
return -ENODEV;
i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
if (!i2c)
return -ENOMEM;
if (!request_mem_region(res->start, resource_size(res),
pdev->name)) {
if (!devm_request_mem_region(&pdev->dev, res->start,
resource_size(res), pdev->name)) {
dev_err(&pdev->dev, "Memory region busy\n");
ret = -EBUSY;
goto request_mem_failed;
return -EBUSY;
}
i2c->base = ioremap(res->start, resource_size(res));
i2c->base = devm_ioremap_nocache(&pdev->dev, res->start,
resource_size(res));
if (!i2c->base) {
dev_err(&pdev->dev, "Unable to map registers\n");
ret = -EIO;
goto map_failed;
return -EIO;
}
pdata = pdev->dev.platform_data;
if (pdata) {
i2c->regstep = pdata->regstep;
i2c->clock_khz = pdata->clock_khz;
} else {
ret = ocores_i2c_of_probe(pdev, i2c);
if (ret)
return ret;
}
i2c->regstep = pdata->regstep;
i2c->clock_khz = pdata->clock_khz;
ocores_init(i2c);
init_waitqueue_head(&i2c->wait);
ret = request_irq(res2->start, ocores_isr, 0, pdev->name, i2c);
ret = devm_request_irq(&pdev->dev, res2->start, ocores_isr, 0,
pdev->name, i2c);
if (ret) {
dev_err(&pdev->dev, "Cannot claim IRQ\n");
goto request_irq_failed;
return ret;
}
/* hook up driver to tree */
@ -265,36 +330,29 @@ static int __devinit ocores_i2c_probe(struct platform_device *pdev)
i2c->adap = ocores_adapter;
i2c_set_adapdata(&i2c->adap, i2c);
i2c->adap.dev.parent = &pdev->dev;
#ifdef CONFIG_OF
i2c->adap.dev.of_node = pdev->dev.of_node;
#endif
/* add i2c adapter to i2c tree */
ret = i2c_add_adapter(&i2c->adap);
if (ret) {
dev_err(&pdev->dev, "Failed to add adapter\n");
goto add_adapter_failed;
return ret;
}
/* add in known devices to the bus */
for (i = 0; i < pdata->num_devices; i++)
i2c_new_device(&i2c->adap, pdata->devices + i);
if (pdata) {
for (i = 0; i < pdata->num_devices; i++)
i2c_new_device(&i2c->adap, pdata->devices + i);
}
return 0;
add_adapter_failed:
free_irq(res2->start, i2c);
request_irq_failed:
iounmap(i2c->base);
map_failed:
release_mem_region(res->start, resource_size(res));
request_mem_failed:
kfree(i2c);
return ret;
}
static int __devexit ocores_i2c_remove(struct platform_device* pdev)
{
struct ocores_i2c *i2c = platform_get_drvdata(pdev);
struct resource *res;
/* disable i2c logic */
oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
@ -304,18 +362,6 @@ static int __devexit ocores_i2c_remove(struct platform_device* pdev)
i2c_del_adapter(&i2c->adap);
platform_set_drvdata(pdev, NULL);
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (res)
free_irq(res->start, i2c);
iounmap(i2c->base);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res)
release_mem_region(res->start, resource_size(res));
kfree(i2c);
return 0;
}
@ -344,6 +390,16 @@ static int ocores_i2c_resume(struct platform_device *pdev)
#define ocores_i2c_resume NULL
#endif
#ifdef CONFIG_OF
static struct of_device_id ocores_i2c_match[] = {
{
.compatible = "opencores,i2c-ocores",
},
{},
};
MODULE_DEVICE_TABLE(of, ocores_i2c_match);
#endif
/* work with hotplug and coldplug */
MODULE_ALIAS("platform:ocores-i2c");
@ -355,6 +411,9 @@ static struct platform_driver ocores_i2c_driver = {
.driver = {
.owner = THIS_MODULE,
.name = "ocores-i2c",
#ifdef CONFIG_OF
.of_match_table = ocores_i2c_match,
#endif
},
};

10
drivers/i2c/busses/i2c-omap.c
View File

@ -598,12 +598,8 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
* REVISIT: We should abort the transfer on signals, but the bus goes
* into arbitration and we're currently unable to recover from it.
*/
if (dev->set_mpu_wkup_lat != NULL)
dev->set_mpu_wkup_lat(dev->dev, dev->latency);
r = wait_for_completion_timeout(&dev->cmd_complete,
OMAP_I2C_TIMEOUT);
if (dev->set_mpu_wkup_lat != NULL)
dev->set_mpu_wkup_lat(dev->dev, -1);
dev->buf_len = 0;
if (r < 0)
return r;
@ -654,12 +650,18 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
if (r < 0)
goto out;
if (dev->set_mpu_wkup_lat != NULL)
dev->set_mpu_wkup_lat(dev->dev, dev->latency);
for (i = 0; i < num; i++) {
r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
if (r != 0)
break;
}
if (dev->set_mpu_wkup_lat != NULL)
dev->set_mpu_wkup_lat(dev->dev, -1);
if (r == 0)
r = num;