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i2c: rcar: fix some trivial typos in comments 

Nothing big, but they get annoying after a while ;)

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Wolfram Sang 2018-01-21 15:45:11 +01:00 committed by Wolfram Sang
parent 19cfcafd7f
commit fe34fbf93f
1 changed files with 3 additions and 3 deletions
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6
drivers/i2c/busses/i2c-rcar.c
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@ -62,7 +62,7 @@
#define MIE (1 << 3) /* master if enable */
#define TSBE (1 << 2)
#define FSB (1 << 1) /* force stop bit */
#define ESG (1 << 0) /* en startbit gen */
#define ESG (1 << 0) /* enable start bit gen */
/* ICSSR (also for ICSIER) */
#define GCAR (1 << 6) /* general call received */
@ -331,7 +331,7 @@ static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read);
/*
* We don't have a testcase but the HW engineers say that the write order
* We don't have a test case but the HW engineers say that the write order
* of ICMSR and ICMCR depends on whether we issue START or REP_START. Since
* it didn't cause a drawback for me, let's rather be safe than sorry.
*/
@ -489,7 +489,7 @@ static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
/*
* Try to use DMA to transmit the rest of the data if
* address transfer pashe just finished.
* address transfer phase just finished.
*/
if (msr & MAT)
rcar_i2c_dma(priv);