net: phy: meson-gxl: add read and write helpers for banked registers
Add read and write helpers to manipulate banked registers on this PHY This helps clarify the settings applied to these registers and what the driver actually does Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jerome Brunet
David S. Miller
parent
00fd73eb29
commit
fdaa84c371
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@ -50,69 +50,100 @@
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#define FR_PLL_DIV0 0x1c
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#define FR_PLL_DIV1 0x1d
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static int meson_gxl_open_banks(struct phy_device *phydev)
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{
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int ret;
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/* Enable Analog and DSP register Bank access by
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* toggling TSTCNTL_TEST_MODE bit in the TSTCNTL register
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*/
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ret = phy_write(phydev, TSTCNTL, 0);
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if (ret)
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return ret;
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ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
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if (ret)
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return ret;
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ret = phy_write(phydev, TSTCNTL, 0);
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if (ret)
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return ret;
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return phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
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}
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static void meson_gxl_close_banks(struct phy_device *phydev)
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{
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phy_write(phydev, TSTCNTL, 0);
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}
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static int meson_gxl_read_reg(struct phy_device *phydev,
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unsigned int bank, unsigned int reg)
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{
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int ret;
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ret = meson_gxl_open_banks(phydev);
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if (ret)
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goto out;
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ret = phy_write(phydev, TSTCNTL, TSTCNTL_READ |
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FIELD_PREP(TSTCNTL_REG_BANK_SEL, bank) |
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TSTCNTL_TEST_MODE |
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FIELD_PREP(TSTCNTL_READ_ADDRESS, reg));
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if (ret)
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goto out;
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ret = phy_read(phydev, TSTREAD1);
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out:
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/* Close the bank access on our way out */
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meson_gxl_close_banks(phydev);
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return ret;
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}
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static int meson_gxl_write_reg(struct phy_device *phydev,
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unsigned int bank, unsigned int reg,
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uint16_t value)
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{
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int ret;
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ret = meson_gxl_open_banks(phydev);
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if (ret)
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goto out;
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ret = phy_write(phydev, TSTWRITE, value);
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if (ret)
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goto out;
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ret = phy_write(phydev, TSTCNTL, TSTCNTL_WRITE |
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FIELD_PREP(TSTCNTL_REG_BANK_SEL, bank) |
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TSTCNTL_TEST_MODE |
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FIELD_PREP(TSTCNTL_WRITE_ADDRESS, reg));
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out:
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/* Close the bank access on our way out */
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meson_gxl_close_banks(phydev);
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return ret;
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}
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static int meson_gxl_config_init(struct phy_device *phydev)
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{
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int ret;
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/* Enable Analog and DSP register Bank access by */
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ret = phy_write(phydev, TSTCNTL, 0);
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if (ret)
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return ret;
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ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
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if (ret)
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return ret;
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ret = phy_write(phydev, TSTCNTL, 0);
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if (ret)
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return ret;
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ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
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if (ret)
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return ret;
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/* Write CONFIG_A6*/
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ret = phy_write(phydev, TSTWRITE, 0x8e0d);
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if (ret)
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return ret;
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ret = phy_write(phydev, TSTCNTL,
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TSTCNTL_WRITE
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| FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_ANALOG_DSP)
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| TSTCNTL_TEST_MODE
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| FIELD_PREP(TSTCNTL_WRITE_ADDRESS, A6_CONFIG_REG));
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ret = meson_gxl_write_reg(phydev, BANK_ANALOG_DSP, A6_CONFIG_REG,
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0x8e0d);
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if (ret)
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return ret;
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/* Enable fractional PLL */
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ret = phy_write(phydev, TSTWRITE, 0x0005);
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if (ret)
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return ret;
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ret = phy_write(phydev, TSTCNTL,
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TSTCNTL_WRITE
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| FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_BIST)
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| TSTCNTL_TEST_MODE
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| FIELD_PREP(TSTCNTL_WRITE_ADDRESS, FR_PLL_CONTROL));
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ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_CONTROL, 0x5);
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if (ret)
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return ret;
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/* Program fraction FR_PLL_DIV1 */
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ret = phy_write(phydev, TSTWRITE, 0x029a);
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if (ret)
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return ret;
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ret = phy_write(phydev, TSTCNTL,
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TSTCNTL_WRITE
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| FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_BIST)
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| TSTCNTL_TEST_MODE
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| FIELD_PREP(TSTCNTL_WRITE_ADDRESS, FR_PLL_DIV1));
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ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_DIV1, 0x029a);
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if (ret)
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return ret;
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/* Program fraction FR_PLL_DIV1 */
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ret = phy_write(phydev, TSTWRITE, 0xaaaa);
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if (ret)
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return ret;
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ret = phy_write(phydev, TSTCNTL,
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TSTCNTL_WRITE
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| FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_BIST)
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| TSTCNTL_TEST_MODE
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| FIELD_PREP(TSTCNTL_WRITE_ADDRESS, FR_PLL_DIV0));
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ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_DIV0, 0xaaaa);
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if (ret)
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return ret;
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@ -146,31 +177,8 @@ static int meson_gxl_read_status(struct phy_device *phydev)
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else if (!ret)
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goto read_status_continue;
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/* Need to access WOL bank, make sure the access is open */
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ret = phy_write(phydev, TSTCNTL, 0);
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if (ret)
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return ret;
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ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
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if (ret)
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return ret;
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ret = phy_write(phydev, TSTCNTL, 0);
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if (ret)
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return ret;
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ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
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if (ret)
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return ret;
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/* Request LPI_STATUS WOL register */
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ret = phy_write(phydev, TSTCNTL,
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TSTCNTL_READ
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| FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_WOL)
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| TSTCNTL_TEST_MODE
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| FIELD_PREP(TSTCNTL_READ_ADDRESS, LPI_STATUS));
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if (ret)
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return ret;
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/* Read LPI_STATUS value */
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wol = phy_read(phydev, TSTREAD1);
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/* Aneg is done, let's check everything is fine */
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wol = meson_gxl_read_reg(phydev, BANK_WOL, LPI_STATUS);
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if (wol < 0)
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return wol;
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