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typo fixes: disadvantadge -> disadvantage 

Signed-off-by: Adrian Bunk <bunk@stusta.de>
This commit is contained in:
Adrian Bunk 2006-06-30 18:23:39 +02:00
parent 0418726bb5
commit fd245f0069
2 changed files with 2 additions and 2 deletions
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2
Documentation/arm/IXP4xx
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@ -85,7 +85,7 @@ IXP4xx provides two methods of accessing PCI memory space:
2) If > 64MB of memory space is required, the IXP4xx can be 2) If > 64MB of memory space is required, the IXP4xx can be
configured to use indirect registers to access PCI This allows configured to use indirect registers to access PCI This allows
for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus. for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus.
The disadvantadge of this is that every PCI access requires The disadvantage of this is that every PCI access requires
three local register accesses plus a spinlock, but in some three local register accesses plus a spinlock, but in some
cases the performance hit is acceptable. In addition, you cannot cases the performance hit is acceptable. In addition, you cannot
mmap() PCI devices in this case due to the indirect nature mmap() PCI devices in this case due to the indirect nature

2
include/asm-arm/arch-ixp4xx/io.h
View File

@ -38,7 +38,7 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
* 2) If > 64MB of memory space is required, the IXP4xx can be configured * 2) If > 64MB of memory space is required, the IXP4xx can be configured
* to use indirect registers to access PCI (as we do below for I/O * to use indirect registers to access PCI (as we do below for I/O
* transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff) * transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff)
* of memory on the bus. The disadvantadge of this is that every * of memory on the bus. The disadvantage of this is that every
* PCI access requires three local register accesses plus a spinlock, * PCI access requires three local register accesses plus a spinlock,
* but in some cases the performance hit is acceptable. In addition, * but in some cases the performance hit is acceptable. In addition,
* you cannot mmap() PCI devices in this case. * you cannot mmap() PCI devices in this case.