powerpc/476: add machine check handler for 47x core
The 47x core's MCSR varies from 44x, so it needs it's own machine check handler. Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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@ -72,6 +72,7 @@ extern int machine_check_4xx(struct pt_regs *regs);
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extern int machine_check_440A(struct pt_regs *regs);
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extern int machine_check_e500(struct pt_regs *regs);
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extern int machine_check_e200(struct pt_regs *regs);
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extern int machine_check_47x(struct pt_regs *regs);
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/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
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struct cpu_spec {
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@ -1712,6 +1712,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
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.icache_bsize = 32,
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.dcache_bsize = 128,
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.machine_check = machine_check_47x,
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.platform = "ppc470",
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},
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{ /* default match */
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@ -380,6 +380,46 @@ int machine_check_440A(struct pt_regs *regs)
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}
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return 0;
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}
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int machine_check_47x(struct pt_regs *regs)
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{
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unsigned long reason = get_mc_reason(regs);
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u32 mcsr;
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printk(KERN_ERR "Machine check in kernel mode.\n");
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if (reason & ESR_IMCP) {
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printk(KERN_ERR
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"Instruction Synchronous Machine Check exception\n");
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mtspr(SPRN_ESR, reason & ~ESR_IMCP);
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return 0;
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}
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mcsr = mfspr(SPRN_MCSR);
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if (mcsr & MCSR_IB)
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printk(KERN_ERR "Instruction Read PLB Error\n");
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if (mcsr & MCSR_DRB)
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printk(KERN_ERR "Data Read PLB Error\n");
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if (mcsr & MCSR_DWB)
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printk(KERN_ERR "Data Write PLB Error\n");
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if (mcsr & MCSR_TLBP)
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printk(KERN_ERR "TLB Parity Error\n");
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if (mcsr & MCSR_ICP) {
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flush_instruction_cache();
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printk(KERN_ERR "I-Cache Parity Error\n");
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}
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if (mcsr & MCSR_DCSP)
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printk(KERN_ERR "D-Cache Search Parity Error\n");
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if (mcsr & PPC47x_MCSR_GPR)
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printk(KERN_ERR "GPR Parity Error\n");
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if (mcsr & PPC47x_MCSR_FPR)
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printk(KERN_ERR "FPR Parity Error\n");
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if (mcsr & PPC47x_MCSR_IPR)
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printk(KERN_ERR "Machine Check exception is imprecise\n");
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/* Clear MCSR */
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mtspr(SPRN_MCSR, mcsr);
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return 0;
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}
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#elif defined(CONFIG_E500)
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int machine_check_e500(struct pt_regs *regs)
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{
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