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[MIPS] Use the proper technical term for naming some of the cache macros. 

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle 2006-07-06 13:04:01 +01:00
parent 879ba8c88a
commit fc5d2d279f
12 changed files with 18 additions and 18 deletions
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8
arch/mips/mm/c-r4k.c
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@ -578,7 +578,7 @@ static inline void local_r4k_flush_icache_page(void *args)
* secondary cache will result in any entries in the primary caches * secondary cache will result in any entries in the primary caches
* also getting invalidated which hopefully is a bit more economical. * also getting invalidated which hopefully is a bit more economical.
*/ */
if (cpu_has_subset_pcaches) { if (cpu_has_inclusive_pcaches) {
unsigned long addr = (unsigned long) page_address(page); unsigned long addr = (unsigned long) page_address(page);
r4k_blast_scache_page(addr); r4k_blast_scache_page(addr);
@ -634,7 +634,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
/* Catch bad driver code */ /* Catch bad driver code */
BUG_ON(size == 0); BUG_ON(size == 0);
if (cpu_has_subset_pcaches) { if (cpu_has_inclusive_pcaches) {
if (size >= scache_size) if (size >= scache_size)
r4k_blast_scache(); r4k_blast_scache();
else else
@ -662,7 +662,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
/* Catch bad driver code */ /* Catch bad driver code */
BUG_ON(size == 0); BUG_ON(size == 0);
if (cpu_has_subset_pcaches) { if (cpu_has_inclusive_pcaches) {
if (size >= scache_size) if (size >= scache_size)
r4k_blast_scache(); r4k_blast_scache();
else else
@ -1192,7 +1192,7 @@ static void __init setup_scache(void)
printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
c->options |= MIPS_CPU_SUBSET_CACHES; c->options |= MIPS_CPU_INCLUSIVE_CACHES;
} }
void au1x00_fixup_config_od(void) void au1x00_fixup_config_od(void)

4
include/asm-mips/cpu-features.h
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@ -195,8 +195,8 @@
# define cpu_has_veic 0 # define cpu_has_veic 0
#endif #endif
#ifndef cpu_has_subset_pcaches #ifndef cpu_has_inclusive_pcaches
#define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES) #define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
#endif #endif
#ifndef cpu_dcache_line_size #ifndef cpu_dcache_line_size

2
include/asm-mips/cpu.h
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@ -242,7 +242,7 @@
#define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */ #define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */
#define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */ #define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */
#define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */ #define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */
#define MIPS_CPU_SUBSET_CACHES 0x00040000 /* P-cache subset enforced */ #define MIPS_CPU_INCLUSIVE_CACHES 0x00040000 /* P-cache subset enforced */
#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ #define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */
#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ #define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */
#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ #define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */

2
include/asm-mips/mach-cobalt/cpu-feature-overrides.h
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@ -27,7 +27,7 @@
#define cpu_has_mcheck 0 #define cpu_has_mcheck 0
#define cpu_has_ejtag 0 #define cpu_has_ejtag 0
#define cpu_has_subset_pcaches 0 #define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 32 #define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32 #define cpu_icache_line_size() 32
#define cpu_scache_line_size() 0 #define cpu_scache_line_size() 0

2
include/asm-mips/mach-excite/cpu-feature-overrides.h
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@ -31,7 +31,7 @@
#define cpu_has_nofpuex 0 #define cpu_has_nofpuex 0
#define cpu_has_64bits 1 #define cpu_has_64bits 1
#define cpu_has_subset_pcaches 0 #define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 32 #define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32 #define cpu_icache_line_size() 32

2
include/asm-mips/mach-ip27/cpu-feature-overrides.h
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@ -34,7 +34,7 @@
#define cpu_has_4kex 1 #define cpu_has_4kex 1
#define cpu_has_4k_cache 1 #define cpu_has_4k_cache 1
#define cpu_has_subset_pcaches 1 #define cpu_has_inclusive_pcaches 1
#define cpu_dcache_line_size() 32 #define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 64 #define cpu_icache_line_size() 64

2
include/asm-mips/mach-ja/cpu-feature-overrides.h
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@ -31,7 +31,7 @@
#define cpu_has_nofpuex 0 #define cpu_has_nofpuex 0
#define cpu_has_64bits 1 #define cpu_has_64bits 1
#define cpu_has_subset_pcaches 0 #define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 32 #define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32 #define cpu_icache_line_size() 32

4
include/asm-mips/mach-mips/cpu-feature-overrides.h
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@ -39,7 +39,7 @@
#define cpu_has_nofpuex 0 #define cpu_has_nofpuex 0
/* #define cpu_has_64bits ? */ /* #define cpu_has_64bits ? */
/* #define cpu_has_64bit_zero_reg ? */ /* #define cpu_has_64bit_zero_reg ? */
/* #define cpu_has_subset_pcaches ? */ /* #define cpu_has_inclusive_pcaches ? */
#define cpu_icache_snoops_remote_store 1 #define cpu_icache_snoops_remote_store 1
#endif #endif
@ -65,7 +65,7 @@
#define cpu_has_nofpuex 0 #define cpu_has_nofpuex 0
/* #define cpu_has_64bits ? */ /* #define cpu_has_64bits ? */
/* #define cpu_has_64bit_zero_reg ? */ /* #define cpu_has_64bit_zero_reg ? */
/* #define cpu_has_subset_pcaches ? */ /* #define cpu_has_inclusive_pcaches ? */
#define cpu_icache_snoops_remote_store 1 #define cpu_icache_snoops_remote_store 1
#endif #endif

2
include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
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@ -34,7 +34,7 @@
#define cpu_has_nofpuex 0 #define cpu_has_nofpuex 0
#define cpu_has_64bits 1 #define cpu_has_64bits 1
#define cpu_has_subset_pcaches 0 #define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 32 #define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32 #define cpu_icache_line_size() 32

2
include/asm-mips/mach-sibyte/cpu-feature-overrides.h
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@ -31,7 +31,7 @@
#define cpu_has_nofpuex 0 #define cpu_has_nofpuex 0
#define cpu_has_64bits 1 #define cpu_has_64bits 1
#define cpu_has_subset_pcaches 0 #define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 32 #define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32 #define cpu_icache_line_size() 32

4
include/asm-mips/mach-sim/cpu-feature-overrides.h
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@ -34,7 +34,7 @@
#define cpu_has_nofpuex 0 #define cpu_has_nofpuex 0
/* #define cpu_has_64bits ? */ /* #define cpu_has_64bits ? */
/* #define cpu_has_64bit_zero_reg ? */ /* #define cpu_has_64bit_zero_reg ? */
/* #define cpu_has_subset_pcaches ? */ /* #define cpu_has_inclusive_pcaches ? */
#endif #endif
#ifdef CONFIG_CPU_MIPS64 #ifdef CONFIG_CPU_MIPS64
@ -59,7 +59,7 @@
#define cpu_has_nofpuex 0 #define cpu_has_nofpuex 0
/* #define cpu_has_64bits ? */ /* #define cpu_has_64bits ? */
/* #define cpu_has_64bit_zero_reg ? */ /* #define cpu_has_64bit_zero_reg ? */
/* #define cpu_has_subset_pcaches ? */ /* #define cpu_has_inclusive_pcaches ? */
#endif #endif
#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ #endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */

2
include/asm-mips/mach-yosemite/cpu-feature-overrides.h
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@ -31,7 +31,7 @@
#define cpu_has_nofpuex 0 #define cpu_has_nofpuex 0
#define cpu_has_64bits 1 #define cpu_has_64bits 1
#define cpu_has_subset_pcaches 0 #define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 32 #define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32 #define cpu_icache_line_size() 32