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powerpc/64s/exception: Remove old INT_ENTRY macro 

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-7-npiggin@gmail.com
This commit is contained in:
Nicholas Piggin 2020-02-26 03:35:15 +10:00 committed by Michael Ellerman
parent 4f50541f67
commit fc589ee416
1 changed files with 30 additions and 38 deletions
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68
arch/powerpc/kernel/exceptions-64s.S
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@ -482,13 +482,13 @@ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948)
* - Fall through and continue executing in real, unrelocated mode. * - Fall through and continue executing in real, unrelocated mode.
* This is done if early=2. * This is done if early=2.
*/ */
.macro INT_HANDLER name, vec, ool=0, early=0, virt=0, hsrr=0, area=PACA_EXGEN, ri=1, dar=0, dsisr=0, bitmask=0, kvm=0 .macro GEN_INT_ENTRY name, virt, ool=0
SET_SCRATCH0(r13) /* save r13 */ SET_SCRATCH0(r13) /* save r13 */
GET_PACA(r13) GET_PACA(r13)
std r9,\area\()+EX_R9(r13) /* save r9 */ std r9,IAREA+EX_R9(r13) /* save r9 */
OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR) OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR)
HMT_MEDIUM HMT_MEDIUM
std r10,\area\()+EX_R10(r13) /* save r10 - r12 */ std r10,IAREA+EX_R10(r13) /* save r10 - r12 */
OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR) OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
.if \ool .if \ool
.if !\virt .if !\virt
@ -502,47 +502,47 @@ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948)
.endif .endif
.endif .endif
OPT_SAVE_REG_TO_PACA(\area\()+EX_PPR, r9, CPU_FTR_HAS_PPR) OPT_SAVE_REG_TO_PACA(IAREA+EX_PPR, r9, CPU_FTR_HAS_PPR)
OPT_SAVE_REG_TO_PACA(\area\()+EX_CFAR, r10, CPU_FTR_CFAR) OPT_SAVE_REG_TO_PACA(IAREA+EX_CFAR, r10, CPU_FTR_CFAR)
INTERRUPT_TO_KERNEL INTERRUPT_TO_KERNEL
SAVE_CTR(r10, \area\()) SAVE_CTR(r10, IAREA)
mfcr r9 mfcr r9
.if \kvm .if (!\virt && IKVM_REAL) || (\virt && IKVM_VIRT)
KVMTEST \name \hsrr \vec KVMTEST \name IHSRR IVEC
.endif .endif
.if \bitmask .if IMASK
lbz r10,PACAIRQSOFTMASK(r13) lbz r10,PACAIRQSOFTMASK(r13)
andi. r10,r10,\bitmask andi. r10,r10,IMASK
/* Associate vector numbers with bits in paca->irq_happened */ /* Associate vector numbers with bits in paca->irq_happened */
.if \vec == 0x500 || \vec == 0xea0 .if IVEC == 0x500 || IVEC == 0xea0
li r10,PACA_IRQ_EE li r10,PACA_IRQ_EE
.elseif \vec == 0x900 .elseif IVEC == 0x900
li r10,PACA_IRQ_DEC li r10,PACA_IRQ_DEC
.elseif \vec == 0xa00 || \vec == 0xe80 .elseif IVEC == 0xa00 || IVEC == 0xe80
li r10,PACA_IRQ_DBELL li r10,PACA_IRQ_DBELL
.elseif \vec == 0xe60 .elseif IVEC == 0xe60
li r10,PACA_IRQ_HMI li r10,PACA_IRQ_HMI
.elseif \vec == 0xf00 .elseif IVEC == 0xf00
li r10,PACA_IRQ_PMI li r10,PACA_IRQ_PMI
.else .else
.abort "Bad maskable vector" .abort "Bad maskable vector"
.endif .endif
.if \hsrr == EXC_HV_OR_STD .if IHSRR == EXC_HV_OR_STD
BEGIN_FTR_SECTION BEGIN_FTR_SECTION
bne masked_Hinterrupt bne masked_Hinterrupt
FTR_SECTION_ELSE FTR_SECTION_ELSE
bne masked_interrupt bne masked_interrupt
ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
.elseif \hsrr .elseif IHSRR
bne masked_Hinterrupt bne masked_Hinterrupt
.else .else
bne masked_interrupt bne masked_interrupt
.endif .endif
.endif .endif
std r11,\area\()+EX_R11(r13) std r11,IAREA+EX_R11(r13)
std r12,\area\()+EX_R12(r13) std r12,IAREA+EX_R12(r13)
/* /*
* DAR/DSISR, SCRATCH0 must be read before setting MSR[RI], * DAR/DSISR, SCRATCH0 must be read before setting MSR[RI],
@ -550,47 +550,39 @@ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948)
* not recoverable if they are live. * not recoverable if they are live.
*/ */
GET_SCRATCH0(r10) GET_SCRATCH0(r10)
std r10,\area\()+EX_R13(r13) std r10,IAREA+EX_R13(r13)
.if \dar == 1 .if IDAR == 1
.if \hsrr .if IHSRR
mfspr r10,SPRN_HDAR mfspr r10,SPRN_HDAR
.else .else
mfspr r10,SPRN_DAR mfspr r10,SPRN_DAR
.endif .endif
std r10,\area\()+EX_DAR(r13) std r10,IAREA+EX_DAR(r13)
.endif .endif
.if \dsisr == 1 .if IDSISR == 1
.if \hsrr .if IHSRR
mfspr r10,SPRN_HDSISR mfspr r10,SPRN_HDSISR
.else .else
mfspr r10,SPRN_DSISR mfspr r10,SPRN_DSISR
.endif .endif
stw r10,\area\()+EX_DSISR(r13) stw r10,IAREA+EX_DSISR(r13)
.endif .endif
.if \early == 2 .if IEARLY == 2
/* nothing more */ /* nothing more */
.elseif \early .elseif IEARLY
mfctr r10 /* save ctr, even for !RELOCATABLE */ mfctr r10 /* save ctr, even for !RELOCATABLE */
BRANCH_TO_C000(r11, \name\()_common) BRANCH_TO_C000(r11, \name\()_common)
.elseif !\virt .elseif !\virt
INT_SAVE_SRR_AND_JUMP \name\()_common, \hsrr, \ri INT_SAVE_SRR_AND_JUMP \name\()_common, IHSRR, ISET_RI
.else .else
INT_VIRT_SAVE_SRR_AND_JUMP \name\()_common, \hsrr INT_VIRT_SAVE_SRR_AND_JUMP \name\()_common, IHSRR
.endif .endif
.if \ool .if \ool
.popsection .popsection
.endif .endif
.endm .endm
.macro GEN_INT_ENTRY name, virt, ool=0
.if ! \virt
INT_HANDLER \name, IVEC, \ool, IEARLY, \virt, IHSRR, IAREA, ISET_RI, IDAR, IDSISR, IMASK, IKVM_REAL
.else
INT_HANDLER \name, IVEC, \ool, IEARLY, \virt, IHSRR, IAREA, ISET_RI, IDAR, IDSISR, IMASK, IKVM_VIRT
.endif
.endm
/* /*
* On entry r13 points to the paca, r9-r13 are saved in the paca, * On entry r13 points to the paca, r9-r13 are saved in the paca,
* r9 contains the saved CR, r11 and r12 contain the saved SRR0 and * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and