arm64: dts: ti: am654: Add DSS node
Add DSS node to k3-am65-main.dtsi with labels for board specific support and syscon node for oldi-io-ctrl. Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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@ -287,6 +287,11 @@
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mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
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<0x4090 0x3>; /* SERDES1 lane select */
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};
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dss_oldi_io_ctrl: dss_oldi_io_ctrl@41E0 {
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compatible = "syscon";
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reg = <0x0000041E0 0x14>;
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};
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};
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dwc3_0: dwc3@4000000 {
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@ -746,4 +751,43 @@
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};
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};
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};
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dss: dss@04a00000 {
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compatible = "ti,am65x-dss";
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reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
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<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
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<0x0 0x04a06000 0x0 0x1000>, /* vid */
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<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
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<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
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<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
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<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
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reg-names = "common", "vidl1", "vid",
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"ovr1", "ovr2", "vp1", "vp2";
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ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
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power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 67 1>,
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<&k3_clks 216 1>,
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<&k3_clks 67 2>;
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clock-names = "fck", "vp1", "vp2";
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/*
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* Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
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* DIV1. See "Figure 12-3365. DSS Integration"
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* in AM65x TRM for details.
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*/
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assigned-clocks = <&k3_clks 67 2>;
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assigned-clock-parents = <&k3_clks 67 5>;
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interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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dss_ports: ports {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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