net: bcmgenet: cleanup ring interrupt masking and unmasking
Since the NAPI interrupts are basically ignored when NAPI is disabled we don't need to mask them within the functions bcmgenet_disable_tx_napi() and bcmgenet_disable_rx_napi(). So wait until all NAPI instances are disabled and mask all of the bcmgenet driver interrupts together in bcmgenet_netif_stop(). The interrupts can still be enabled in the functions bcmgenet_enable_tx_napi() and bcmgenet_enable_rx_napi(), but use the ring context int_enable() method to keep the functionality consistent and the code cleaner. Signed-off-by: Doug Berger <opendmb@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -2147,33 +2147,24 @@ static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
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static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
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{
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unsigned int i;
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u32 int0_enable = UMAC_IRQ_TXDMA_DONE;
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u32 int1_enable = 0;
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struct bcmgenet_tx_ring *ring;
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for (i = 0; i < priv->hw_params->tx_queues; ++i) {
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ring = &priv->tx_rings[i];
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napi_enable(&ring->napi);
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int1_enable |= (1 << i);
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ring->int_enable(ring);
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}
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ring = &priv->tx_rings[DESC_INDEX];
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napi_enable(&ring->napi);
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bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
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bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
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ring->int_enable(ring);
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}
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static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
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{
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unsigned int i;
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u32 int0_disable = UMAC_IRQ_TXDMA_DONE;
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u32 int1_disable = 0xffff;
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struct bcmgenet_tx_ring *ring;
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bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET);
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bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET);
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for (i = 0; i < priv->hw_params->tx_queues; ++i) {
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ring = &priv->tx_rings[i];
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napi_disable(&ring->napi);
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@ -2269,33 +2260,24 @@ static void bcmgenet_init_tx_queues(struct net_device *dev)
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static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
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{
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unsigned int i;
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u32 int0_enable = UMAC_IRQ_RXDMA_DONE;
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u32 int1_enable = 0;
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struct bcmgenet_rx_ring *ring;
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for (i = 0; i < priv->hw_params->rx_queues; ++i) {
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ring = &priv->rx_rings[i];
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napi_enable(&ring->napi);
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int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i));
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ring->int_enable(ring);
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}
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ring = &priv->rx_rings[DESC_INDEX];
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napi_enable(&ring->napi);
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bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
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bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
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ring->int_enable(ring);
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}
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static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
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{
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unsigned int i;
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u32 int0_disable = UMAC_IRQ_RXDMA_DONE;
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u32 int1_disable = 0xffff << UMAC_IRQ1_RX_INTR_SHIFT;
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struct bcmgenet_rx_ring *ring;
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bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET);
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bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET);
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for (i = 0; i < priv->hw_params->rx_queues; ++i) {
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ring = &priv->rx_rings[i];
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napi_disable(&ring->napi);
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@ -2888,9 +2870,9 @@ static void bcmgenet_netif_stop(struct net_device *dev)
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netif_tx_stop_all_queues(dev);
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phy_stop(priv->phydev);
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bcmgenet_intr_disable(priv);
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bcmgenet_disable_rx_napi(priv);
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bcmgenet_disable_tx_napi(priv);
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bcmgenet_intr_disable(priv);
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/* Wait for pending work items to complete. Since interrupts are
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* disabled no new work will be scheduled.
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