drm/radeon: KV has three PPLLs (v2)
Enable all three in the driver. Early documentation indicated the 3rd one was used for something else, but that is not the case. v2: handle disable as well Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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@ -1851,10 +1851,9 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
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return pll;
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return pll;
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}
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}
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/* otherwise, pick one of the plls */
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/* otherwise, pick one of the plls */
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if ((rdev->family == CHIP_KAVERI) ||
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if ((rdev->family == CHIP_KABINI) ||
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(rdev->family == CHIP_KABINI) ||
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(rdev->family == CHIP_MULLINS)) {
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(rdev->family == CHIP_MULLINS)) {
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/* KB/KV/ML has PPLL1 and PPLL2 */
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/* KB/ML has PPLL1 and PPLL2 */
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pll_in_use = radeon_get_pll_use_mask(crtc);
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pll_in_use = radeon_get_pll_use_mask(crtc);
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if (!(pll_in_use & (1 << ATOM_PPLL2)))
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if (!(pll_in_use & (1 << ATOM_PPLL2)))
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return ATOM_PPLL2;
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return ATOM_PPLL2;
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@ -1863,7 +1862,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
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DRM_ERROR("unable to allocate a PPLL\n");
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DRM_ERROR("unable to allocate a PPLL\n");
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return ATOM_PPLL_INVALID;
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return ATOM_PPLL_INVALID;
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} else {
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} else {
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/* CI has PPLL0, PPLL1, and PPLL2 */
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/* CI/KV has PPLL0, PPLL1, and PPLL2 */
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pll_in_use = radeon_get_pll_use_mask(crtc);
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pll_in_use = radeon_get_pll_use_mask(crtc);
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if (!(pll_in_use & (1 << ATOM_PPLL2)))
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if (!(pll_in_use & (1 << ATOM_PPLL2)))
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return ATOM_PPLL2;
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return ATOM_PPLL2;
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@ -2155,6 +2154,7 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
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case ATOM_PPLL0:
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case ATOM_PPLL0:
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/* disable the ppll */
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/* disable the ppll */
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if ((rdev->family == CHIP_ARUBA) ||
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if ((rdev->family == CHIP_ARUBA) ||
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(rdev->family == CHIP_KAVERI) ||
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(rdev->family == CHIP_BONAIRE) ||
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(rdev->family == CHIP_BONAIRE) ||
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(rdev->family == CHIP_HAWAII))
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(rdev->family == CHIP_HAWAII))
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atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
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atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
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