ASoC: Update regmap access for WM5100 DSP control registers
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Mark Brown
parent
c97f3bdd26
commit
fbe5c580a6
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@ -32,6 +32,17 @@ bool wm5100_volatile_register(struct device *dev, unsigned int reg)
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case WM5100_MIC_DETECT_3:
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return 1;
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default:
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if ((reg >= WM5100_DSP1_PM_0 && reg <= WM5100_DSP1_PM_1535) ||
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(reg >= WM5100_DSP1_ZM_0 && reg <= WM5100_DSP1_ZM_2047) ||
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(reg >= WM5100_DSP1_DM_0 && reg <= WM5100_DSP1_DM_511) ||
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(reg >= WM5100_DSP2_PM_0 && reg <= WM5100_DSP2_PM_1535) ||
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(reg >= WM5100_DSP2_ZM_0 && reg <= WM5100_DSP2_ZM_2047) ||
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(reg >= WM5100_DSP2_DM_0 && reg <= WM5100_DSP2_DM_511) ||
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(reg >= WM5100_DSP3_PM_0 && reg <= WM5100_DSP3_PM_1535) ||
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(reg >= WM5100_DSP3_ZM_0 && reg <= WM5100_DSP3_ZM_2047) ||
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(reg >= WM5100_DSP3_DM_0 && reg <= WM5100_DSP3_DM_511))
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return 1;
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else
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return 0;
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}
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}
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@ -697,8 +708,109 @@ bool wm5100_readable_register(struct device *dev, unsigned int reg)
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case WM5100_HPLPF3_2:
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case WM5100_HPLPF4_1:
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case WM5100_HPLPF4_2:
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case WM5100_DSP1_CONTROL_1:
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case WM5100_DSP1_CONTROL_2:
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case WM5100_DSP1_CONTROL_3:
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case WM5100_DSP1_CONTROL_4:
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case WM5100_DSP1_CONTROL_5:
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case WM5100_DSP1_CONTROL_6:
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case WM5100_DSP1_CONTROL_7:
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case WM5100_DSP1_CONTROL_8:
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case WM5100_DSP1_CONTROL_9:
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case WM5100_DSP1_CONTROL_10:
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case WM5100_DSP1_CONTROL_11:
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case WM5100_DSP1_CONTROL_12:
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case WM5100_DSP1_CONTROL_13:
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case WM5100_DSP1_CONTROL_14:
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case WM5100_DSP1_CONTROL_15:
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case WM5100_DSP1_CONTROL_16:
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case WM5100_DSP1_CONTROL_17:
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case WM5100_DSP1_CONTROL_18:
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case WM5100_DSP1_CONTROL_19:
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case WM5100_DSP1_CONTROL_20:
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case WM5100_DSP1_CONTROL_21:
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case WM5100_DSP1_CONTROL_22:
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case WM5100_DSP1_CONTROL_23:
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case WM5100_DSP1_CONTROL_24:
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case WM5100_DSP1_CONTROL_25:
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case WM5100_DSP1_CONTROL_26:
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case WM5100_DSP1_CONTROL_27:
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case WM5100_DSP1_CONTROL_28:
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case WM5100_DSP1_CONTROL_29:
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case WM5100_DSP1_CONTROL_30:
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case WM5100_DSP2_CONTROL_1:
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case WM5100_DSP2_CONTROL_2:
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case WM5100_DSP2_CONTROL_3:
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case WM5100_DSP2_CONTROL_4:
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case WM5100_DSP2_CONTROL_5:
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case WM5100_DSP2_CONTROL_6:
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case WM5100_DSP2_CONTROL_7:
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case WM5100_DSP2_CONTROL_8:
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case WM5100_DSP2_CONTROL_9:
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case WM5100_DSP2_CONTROL_10:
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case WM5100_DSP2_CONTROL_11:
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case WM5100_DSP2_CONTROL_12:
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case WM5100_DSP2_CONTROL_13:
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case WM5100_DSP2_CONTROL_14:
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case WM5100_DSP2_CONTROL_15:
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case WM5100_DSP2_CONTROL_16:
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case WM5100_DSP2_CONTROL_17:
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case WM5100_DSP2_CONTROL_18:
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case WM5100_DSP2_CONTROL_19:
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case WM5100_DSP2_CONTROL_20:
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case WM5100_DSP2_CONTROL_21:
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case WM5100_DSP2_CONTROL_22:
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case WM5100_DSP2_CONTROL_23:
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case WM5100_DSP2_CONTROL_24:
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case WM5100_DSP2_CONTROL_25:
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case WM5100_DSP2_CONTROL_26:
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case WM5100_DSP2_CONTROL_27:
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case WM5100_DSP2_CONTROL_28:
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case WM5100_DSP2_CONTROL_29:
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case WM5100_DSP2_CONTROL_30:
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case WM5100_DSP3_CONTROL_1:
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case WM5100_DSP3_CONTROL_2:
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case WM5100_DSP3_CONTROL_3:
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case WM5100_DSP3_CONTROL_4:
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case WM5100_DSP3_CONTROL_5:
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case WM5100_DSP3_CONTROL_6:
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case WM5100_DSP3_CONTROL_7:
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case WM5100_DSP3_CONTROL_8:
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case WM5100_DSP3_CONTROL_9:
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case WM5100_DSP3_CONTROL_10:
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case WM5100_DSP3_CONTROL_11:
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case WM5100_DSP3_CONTROL_12:
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case WM5100_DSP3_CONTROL_13:
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case WM5100_DSP3_CONTROL_14:
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case WM5100_DSP3_CONTROL_15:
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case WM5100_DSP3_CONTROL_16:
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case WM5100_DSP3_CONTROL_17:
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case WM5100_DSP3_CONTROL_18:
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case WM5100_DSP3_CONTROL_19:
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case WM5100_DSP3_CONTROL_20:
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case WM5100_DSP3_CONTROL_21:
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case WM5100_DSP3_CONTROL_22:
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case WM5100_DSP3_CONTROL_23:
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case WM5100_DSP3_CONTROL_24:
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case WM5100_DSP3_CONTROL_25:
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case WM5100_DSP3_CONTROL_26:
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case WM5100_DSP3_CONTROL_27:
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case WM5100_DSP3_CONTROL_28:
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case WM5100_DSP3_CONTROL_29:
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case WM5100_DSP3_CONTROL_30:
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return 1;
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default:
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if ((reg >= WM5100_DSP1_PM_0 && reg <= WM5100_DSP1_PM_1535) ||
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(reg >= WM5100_DSP1_ZM_0 && reg <= WM5100_DSP1_ZM_2047) ||
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(reg >= WM5100_DSP1_DM_0 && reg <= WM5100_DSP1_DM_511) ||
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(reg >= WM5100_DSP2_PM_0 && reg <= WM5100_DSP2_PM_1535) ||
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(reg >= WM5100_DSP2_ZM_0 && reg <= WM5100_DSP2_ZM_2047) ||
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(reg >= WM5100_DSP2_DM_0 && reg <= WM5100_DSP2_DM_511) ||
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(reg >= WM5100_DSP3_PM_0 && reg <= WM5100_DSP3_PM_1535) ||
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(reg >= WM5100_DSP3_ZM_0 && reg <= WM5100_DSP3_ZM_2047) ||
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(reg >= WM5100_DSP3_DM_0 && reg <= WM5100_DSP3_DM_511))
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return 1;
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else
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return 0;
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}
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}
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@ -1361,4 +1473,13 @@ struct reg_default wm5100_reg_defaults[WM5100_REGISTER_COUNT] = {
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{ 0x0EC9, 0x0000 }, /* R3785 - HPLPF3_2 */
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{ 0x0ECC, 0x0000 }, /* R3788 - HPLPF4_1 */
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{ 0x0ECD, 0x0000 }, /* R3789 - HPLPF4_2 */
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{ 0x0F02, 0x0000 }, /* R3842 - DSP1 Control 2 */
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{ 0x0F03, 0x0000 }, /* R3843 - DSP1 Control 3 */
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{ 0x0F04, 0x0000 }, /* R3844 - DSP1 Control 4 */
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{ 0x1002, 0x0000 }, /* R4098 - DSP2 Control 2 */
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{ 0x1003, 0x0000 }, /* R4099 - DSP2 Control 3 */
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{ 0x1004, 0x0000 }, /* R4100 - DSP2 Control 4 */
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{ 0x1102, 0x0000 }, /* R4354 - DSP3 Control 2 */
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{ 0x1103, 0x0000 }, /* R4355 - DSP3 Control 3 */
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{ 0x1104, 0x0000 }, /* R4356 - DSP3 Control 4 */
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};
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@ -709,6 +709,96 @@ int wm5100_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
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#define WM5100_HPLPF3_2 0xEC9
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#define WM5100_HPLPF4_1 0xECC
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#define WM5100_HPLPF4_2 0xECD
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#define WM5100_DSP1_CONTROL_1 0xF00
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#define WM5100_DSP1_CONTROL_2 0xF02
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#define WM5100_DSP1_CONTROL_3 0xF03
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#define WM5100_DSP1_CONTROL_4 0xF04
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#define WM5100_DSP1_CONTROL_5 0xF06
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#define WM5100_DSP1_CONTROL_6 0xF07
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#define WM5100_DSP1_CONTROL_7 0xF08
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#define WM5100_DSP1_CONTROL_8 0xF09
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#define WM5100_DSP1_CONTROL_9 0xF0A
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#define WM5100_DSP1_CONTROL_10 0xF0B
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#define WM5100_DSP1_CONTROL_11 0xF0C
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#define WM5100_DSP1_CONTROL_12 0xF0D
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#define WM5100_DSP1_CONTROL_13 0xF0F
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#define WM5100_DSP1_CONTROL_14 0xF10
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#define WM5100_DSP1_CONTROL_15 0xF11
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#define WM5100_DSP1_CONTROL_16 0xF12
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#define WM5100_DSP1_CONTROL_17 0xF13
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#define WM5100_DSP1_CONTROL_18 0xF14
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#define WM5100_DSP1_CONTROL_19 0xF16
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#define WM5100_DSP1_CONTROL_20 0xF17
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#define WM5100_DSP1_CONTROL_21 0xF18
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#define WM5100_DSP1_CONTROL_22 0xF1A
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#define WM5100_DSP1_CONTROL_23 0xF1B
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#define WM5100_DSP1_CONTROL_24 0xF1C
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#define WM5100_DSP1_CONTROL_25 0xF1E
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#define WM5100_DSP1_CONTROL_26 0xF20
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#define WM5100_DSP1_CONTROL_27 0xF21
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#define WM5100_DSP1_CONTROL_28 0xF22
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#define WM5100_DSP1_CONTROL_29 0xF23
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#define WM5100_DSP1_CONTROL_30 0xF24
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#define WM5100_DSP2_CONTROL_1 0x1000
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#define WM5100_DSP2_CONTROL_2 0x1002
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#define WM5100_DSP2_CONTROL_3 0x1003
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#define WM5100_DSP2_CONTROL_4 0x1004
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#define WM5100_DSP2_CONTROL_5 0x1006
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#define WM5100_DSP2_CONTROL_6 0x1007
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#define WM5100_DSP2_CONTROL_7 0x1008
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#define WM5100_DSP2_CONTROL_8 0x1009
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#define WM5100_DSP2_CONTROL_9 0x100A
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#define WM5100_DSP2_CONTROL_10 0x100B
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#define WM5100_DSP2_CONTROL_11 0x100C
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#define WM5100_DSP2_CONTROL_12 0x100D
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#define WM5100_DSP2_CONTROL_13 0x100F
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#define WM5100_DSP2_CONTROL_14 0x1010
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#define WM5100_DSP2_CONTROL_15 0x1011
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#define WM5100_DSP2_CONTROL_16 0x1012
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#define WM5100_DSP2_CONTROL_17 0x1013
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#define WM5100_DSP2_CONTROL_18 0x1014
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#define WM5100_DSP2_CONTROL_19 0x1016
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#define WM5100_DSP2_CONTROL_20 0x1017
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#define WM5100_DSP2_CONTROL_21 0x1018
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#define WM5100_DSP2_CONTROL_22 0x101A
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#define WM5100_DSP2_CONTROL_23 0x101B
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#define WM5100_DSP2_CONTROL_24 0x101C
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#define WM5100_DSP2_CONTROL_25 0x101E
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#define WM5100_DSP2_CONTROL_26 0x1020
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#define WM5100_DSP2_CONTROL_27 0x1021
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#define WM5100_DSP2_CONTROL_28 0x1022
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#define WM5100_DSP2_CONTROL_29 0x1023
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#define WM5100_DSP2_CONTROL_30 0x1024
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#define WM5100_DSP3_CONTROL_1 0x1100
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#define WM5100_DSP3_CONTROL_2 0x1102
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#define WM5100_DSP3_CONTROL_3 0x1103
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#define WM5100_DSP3_CONTROL_4 0x1104
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#define WM5100_DSP3_CONTROL_5 0x1106
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#define WM5100_DSP3_CONTROL_6 0x1107
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#define WM5100_DSP3_CONTROL_7 0x1108
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#define WM5100_DSP3_CONTROL_8 0x1109
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#define WM5100_DSP3_CONTROL_9 0x110A
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#define WM5100_DSP3_CONTROL_10 0x110B
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#define WM5100_DSP3_CONTROL_11 0x110C
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#define WM5100_DSP3_CONTROL_12 0x110D
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#define WM5100_DSP3_CONTROL_13 0x110F
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#define WM5100_DSP3_CONTROL_14 0x1110
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#define WM5100_DSP3_CONTROL_15 0x1111
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#define WM5100_DSP3_CONTROL_16 0x1112
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#define WM5100_DSP3_CONTROL_17 0x1113
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#define WM5100_DSP3_CONTROL_18 0x1114
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#define WM5100_DSP3_CONTROL_19 0x1116
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#define WM5100_DSP3_CONTROL_20 0x1117
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#define WM5100_DSP3_CONTROL_21 0x1118
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#define WM5100_DSP3_CONTROL_22 0x111A
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#define WM5100_DSP3_CONTROL_23 0x111B
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#define WM5100_DSP3_CONTROL_24 0x111C
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#define WM5100_DSP3_CONTROL_25 0x111E
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#define WM5100_DSP3_CONTROL_26 0x1120
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#define WM5100_DSP3_CONTROL_27 0x1121
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#define WM5100_DSP3_CONTROL_28 0x1122
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#define WM5100_DSP3_CONTROL_29 0x1123
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#define WM5100_DSP3_CONTROL_30 0x1124
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#define WM5100_DSP1_DM_0 0x4000
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#define WM5100_DSP1_DM_1 0x4001
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#define WM5100_DSP1_DM_2 0x4002
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@ -4560,6 +4650,75 @@ int wm5100_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
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#define WM5100_LHPF4_COEFF_SHIFT 0 /* LHPF4_COEFF - [15:0] */
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#define WM5100_LHPF4_COEFF_WIDTH 16 /* LHPF4_COEFF - [15:0] */
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/*
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* R4132 (0x1024) - DSP2 Control 30
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*/
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#define WM5100_DSP2_RATE_MASK 0xC000 /* DSP2_RATE - [15:14] */
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#define WM5100_DSP2_RATE_SHIFT 14 /* DSP2_RATE - [15:14] */
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#define WM5100_DSP2_RATE_WIDTH 2 /* DSP2_RATE - [15:14] */
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#define WM5100_DSP2_DBG_CLK_ENA 0x0008 /* DSP2_DBG_CLK_ENA */
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#define WM5100_DSP2_DBG_CLK_ENA_MASK 0x0008 /* DSP2_DBG_CLK_ENA */
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#define WM5100_DSP2_DBG_CLK_ENA_SHIFT 3 /* DSP2_DBG_CLK_ENA */
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#define WM5100_DSP2_DBG_CLK_ENA_WIDTH 1 /* DSP2_DBG_CLK_ENA */
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#define WM5100_DSP2_SYS_ENA 0x0004 /* DSP2_SYS_ENA */
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#define WM5100_DSP2_SYS_ENA_MASK 0x0004 /* DSP2_SYS_ENA */
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#define WM5100_DSP2_SYS_ENA_SHIFT 2 /* DSP2_SYS_ENA */
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#define WM5100_DSP2_SYS_ENA_WIDTH 1 /* DSP2_SYS_ENA */
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#define WM5100_DSP2_CORE_ENA 0x0002 /* DSP2_CORE_ENA */
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#define WM5100_DSP2_CORE_ENA_MASK 0x0002 /* DSP2_CORE_ENA */
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#define WM5100_DSP2_CORE_ENA_SHIFT 1 /* DSP2_CORE_ENA */
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#define WM5100_DSP2_CORE_ENA_WIDTH 1 /* DSP2_CORE_ENA */
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#define WM5100_DSP2_START 0x0001 /* DSP2_START */
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#define WM5100_DSP2_START_MASK 0x0001 /* DSP2_START */
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#define WM5100_DSP2_START_SHIFT 0 /* DSP2_START */
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#define WM5100_DSP2_START_WIDTH 1 /* DSP2_START */
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/*
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* R3876 (0xF24) - DSP1 Control 30
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*/
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#define WM5100_DSP1_RATE_MASK 0xC000 /* DSP1_RATE - [15:14] */
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#define WM5100_DSP1_RATE_SHIFT 14 /* DSP1_RATE - [15:14] */
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#define WM5100_DSP1_RATE_WIDTH 2 /* DSP1_RATE - [15:14] */
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#define WM5100_DSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
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#define WM5100_DSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
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#define WM5100_DSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
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#define WM5100_DSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
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#define WM5100_DSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
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#define WM5100_DSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
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#define WM5100_DSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
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#define WM5100_DSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
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#define WM5100_DSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
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#define WM5100_DSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
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#define WM5100_DSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
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#define WM5100_DSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
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#define WM5100_DSP1_START 0x0001 /* DSP1_START */
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#define WM5100_DSP1_START_MASK 0x0001 /* DSP1_START */
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#define WM5100_DSP1_START_SHIFT 0 /* DSP1_START */
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#define WM5100_DSP1_START_WIDTH 1 /* DSP1_START */
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/*
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* R4388 (0x1124) - DSP3 Control 30
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*/
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#define WM5100_DSP3_RATE_MASK 0xC000 /* DSP3_RATE - [15:14] */
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#define WM5100_DSP3_RATE_SHIFT 14 /* DSP3_RATE - [15:14] */
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#define WM5100_DSP3_RATE_WIDTH 2 /* DSP3_RATE - [15:14] */
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#define WM5100_DSP3_DBG_CLK_ENA 0x0008 /* DSP3_DBG_CLK_ENA */
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#define WM5100_DSP3_DBG_CLK_ENA_MASK 0x0008 /* DSP3_DBG_CLK_ENA */
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#define WM5100_DSP3_DBG_CLK_ENA_SHIFT 3 /* DSP3_DBG_CLK_ENA */
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#define WM5100_DSP3_DBG_CLK_ENA_WIDTH 1 /* DSP3_DBG_CLK_ENA */
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#define WM5100_DSP3_SYS_ENA 0x0004 /* DSP3_SYS_ENA */
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#define WM5100_DSP3_SYS_ENA_MASK 0x0004 /* DSP3_SYS_ENA */
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#define WM5100_DSP3_SYS_ENA_SHIFT 2 /* DSP3_SYS_ENA */
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#define WM5100_DSP3_SYS_ENA_WIDTH 1 /* DSP3_SYS_ENA */
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#define WM5100_DSP3_CORE_ENA 0x0002 /* DSP3_CORE_ENA */
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#define WM5100_DSP3_CORE_ENA_MASK 0x0002 /* DSP3_CORE_ENA */
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#define WM5100_DSP3_CORE_ENA_SHIFT 1 /* DSP3_CORE_ENA */
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#define WM5100_DSP3_CORE_ENA_WIDTH 1 /* DSP3_CORE_ENA */
|
||||
#define WM5100_DSP3_START 0x0001 /* DSP3_START */
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||||
#define WM5100_DSP3_START_MASK 0x0001 /* DSP3_START */
|
||||
#define WM5100_DSP3_START_SHIFT 0 /* DSP3_START */
|
||||
#define WM5100_DSP3_START_WIDTH 1 /* DSP3_START */
|
||||
|
||||
/*
|
||||
* R16384 (0x4000) - DSP1 DM 0
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue