uio: uio_fsl_elbc_gpcm: new driver
This driver provides UIO access to memory of a peripheral connected to the Freescale enhanced local bus controller (eLBC) interface using the general purpose chip-select mode (GPCM). Signed-off-by: John Ogness <john.ogness@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
John Ogness
Greg Kroah-Hartman
parent
02b03846bb
commit
fbc4a8a857
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@ -16,20 +16,28 @@ Example:
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"fsl,pq2-localbus";
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#address-cells = <2>;
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#size-cells = <1>;
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reg = <f0010100 40>;
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reg = <0xf0010100 0x40>;
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ranges = <0 0 fe000000 02000000
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1 0 f4500000 00008000>;
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ranges = <0x0 0x0 0xfe000000 0x02000000
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0x1 0x0 0xf4500000 0x00008000
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0x2 0x0 0xfd810000 0x00010000>;
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flash@0,0 {
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compatible = "jedec-flash";
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reg = <0 0 2000000>;
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reg = <0x0 0x0 0x2000000>;
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bank-width = <4>;
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device-width = <1>;
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};
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board-control@1,0 {
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reg = <1 0 20>;
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reg = <0x1 0x0 0x20>;
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compatible = "fsl,mpc8272ads-bcsr";
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};
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simple-periph@2,0 {
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compatible = "fsl,elbc-gpcm-uio";
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reg = <0x2 0x0 0x10000>;
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elbc-gpcm-br = <0xfd810800>;
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elbc-gpcm-or = <0xffff09f7>;
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};
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};
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@ -95,6 +95,9 @@ struct fsl_lbc_bank {
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#define OR_FCM_TRLX_SHIFT 2
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#define OR_FCM_EHTR 0x00000002
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#define OR_FCM_EHTR_SHIFT 1
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#define OR_GPCM_AM 0xFFFF8000
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#define OR_GPCM_AM_SHIFT 15
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};
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struct fsl_lbc_regs {
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@ -104,6 +104,26 @@ config UIO_NETX
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To compile this driver as a module, choose M here; the module
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will be called uio_netx.
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config UIO_FSL_ELBC_GPCM
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tristate "eLBC/GPCM driver"
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depends on FSL_LBC
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help
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Generic driver for accessing a peripheral connected to an eLBC port
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that is running in GPCM mode. GPCM is an interface for simple lower
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performance memories and memory-mapped devices. For devices using
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FCM or UPM eLBC modes, other device-specific drivers are available.
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config UIO_FSL_ELBC_GPCM_NETX5152
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bool "eLBC/GPCM netX 51/52 support"
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depends on UIO_FSL_ELBC_GPCM
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help
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This will add support for netX 51/52 devices connected via eLBC/GPCM.
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In particular, it implements interrupt handling. This can be used
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together with the userspace netX stack from Hilscher.
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Information about this hardware can be found at:
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http://www.hilscher.com/netx
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config UIO_PRUSS
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tristate "Texas Instruments PRUSS driver"
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depends on ARCH_DAVINCI_DA850
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@ -8,3 +8,4 @@ obj-$(CONFIG_UIO_PCI_GENERIC) += uio_pci_generic.o
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obj-$(CONFIG_UIO_NETX) += uio_netx.o
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obj-$(CONFIG_UIO_PRUSS) += uio_pruss.o
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obj-$(CONFIG_UIO_MF624) += uio_mf624.o
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obj-$(CONFIG_UIO_FSL_ELBC_GPCM) += uio_fsl_elbc_gpcm.o
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@ -0,0 +1,499 @@
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/* uio_fsl_elbc_gpcm: UIO driver for eLBC/GPCM peripherals
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Copyright (C) 2014 Linutronix GmbH
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Author: John Ogness <john.ogness@linutronix.de>
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This driver provides UIO access to memory of a peripheral connected
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to the Freescale enhanced local bus controller (eLBC) interface
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using the general purpose chip-select mode (GPCM).
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Here is an example of the device tree entries:
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localbus@ffe05000 {
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ranges = <0x2 0x0 0x0 0xff810000 0x10000>;
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dpm@2,0 {
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compatible = "fsl,elbc-gpcm-uio";
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reg = <0x2 0x0 0x10000>;
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elbc-gpcm-br = <0xff810800>;
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elbc-gpcm-or = <0xffff09f7>;
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interrupt-parent = <&mpic>;
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interrupts = <4 1>;
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device_type = "netx5152";
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uio_name = "netx_custom";
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netx5152,init-win0-offset = <0x0>;
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};
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};
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Only the entries reg (to identify bank) and elbc-gpcm-* (initial BR/OR
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values) are required. The entries interrupt*, device_type, and uio_name
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are optional (as well as any type-specific options such as
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netx5152,init-win0-offset). As long as no interrupt handler is needed,
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this driver can be used without any type-specific implementation.
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The netx5152 type has been tested to work with the netX 51/52 hardware
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from Hilscher using the Hilscher userspace netX stack.
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The netx5152 type should serve as a model to add new type-specific
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devices as needed.
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*/
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/uio_driver.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/fsl_lbc.h>
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#define MAX_BANKS 8
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struct fsl_elbc_gpcm {
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struct device *dev;
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struct fsl_lbc_regs __iomem *lbc;
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u32 bank;
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const char *name;
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void (*init)(struct uio_info *info);
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void (*shutdown)(struct uio_info *info, bool init_err);
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irqreturn_t (*irq_handler)(int irq, struct uio_info *info);
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};
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static ssize_t reg_show(struct device *dev, struct device_attribute *attr,
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char *buf);
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static ssize_t reg_store(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t count);
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DEVICE_ATTR(reg_br, S_IRUGO|S_IWUSR|S_IWGRP, reg_show, reg_store);
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DEVICE_ATTR(reg_or, S_IRUGO|S_IWUSR|S_IWGRP, reg_show, reg_store);
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static ssize_t reg_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct uio_info *info = platform_get_drvdata(pdev);
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struct fsl_elbc_gpcm *priv = info->priv;
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struct fsl_lbc_bank *bank = &priv->lbc->bank[priv->bank];
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if (attr == &dev_attr_reg_br) {
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return scnprintf(buf, PAGE_SIZE, "0x%08x\n",
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in_be32(&bank->br));
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} else if (attr == &dev_attr_reg_or) {
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return scnprintf(buf, PAGE_SIZE, "0x%08x\n",
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in_be32(&bank->or));
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}
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return 0;
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}
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static ssize_t reg_store(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct uio_info *info = platform_get_drvdata(pdev);
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struct fsl_elbc_gpcm *priv = info->priv;
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struct fsl_lbc_bank *bank = &priv->lbc->bank[priv->bank];
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unsigned long val;
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u32 reg_br_cur;
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u32 reg_or_cur;
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u32 reg_new;
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/* parse use input */
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if (kstrtoul(buf, 0, &val) != 0)
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return -EINVAL;
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reg_new = (u32)val;
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/* read current values */
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reg_br_cur = in_be32(&bank->br);
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reg_or_cur = in_be32(&bank->or);
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if (attr == &dev_attr_reg_br) {
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/* not allowed to change effective base address */
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if ((reg_br_cur & reg_or_cur & BR_BA) !=
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(reg_new & reg_or_cur & BR_BA)) {
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return -EINVAL;
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}
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/* not allowed to change mode */
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if ((reg_new & BR_MSEL) != BR_MS_GPCM)
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return -EINVAL;
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/* write new value (force valid) */
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out_be32(&bank->br, reg_new | BR_V);
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} else if (attr == &dev_attr_reg_or) {
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/* not allowed to change access mask */
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if ((reg_or_cur & OR_GPCM_AM) != (reg_new & OR_GPCM_AM))
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return -EINVAL;
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/* write new value */
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out_be32(&bank->or, reg_new);
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} else {
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return -EINVAL;
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}
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return count;
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}
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#ifdef CONFIG_UIO_FSL_ELBC_GPCM_NETX5152
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#define DPM_HOST_WIN0_OFFSET 0xff00
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#define DPM_HOST_INT_STAT0 0xe0
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#define DPM_HOST_INT_EN0 0xf0
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#define DPM_HOST_INT_MASK 0xe600ffff
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#define DPM_HOST_INT_GLOBAL_EN 0x80000000
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static irqreturn_t netx5152_irq_handler(int irq, struct uio_info *info)
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{
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void __iomem *reg_int_en = info->mem[0].internal_addr +
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DPM_HOST_WIN0_OFFSET +
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DPM_HOST_INT_EN0;
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void __iomem *reg_int_stat = info->mem[0].internal_addr +
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DPM_HOST_WIN0_OFFSET +
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DPM_HOST_INT_STAT0;
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/* check if an interrupt is enabled and active */
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if ((ioread32(reg_int_en) & ioread32(reg_int_stat) &
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DPM_HOST_INT_MASK) == 0) {
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return IRQ_NONE;
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}
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/* disable interrupts */
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iowrite32(ioread32(reg_int_en) & ~DPM_HOST_INT_GLOBAL_EN, reg_int_en);
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return IRQ_HANDLED;
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}
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static void netx5152_init(struct uio_info *info)
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{
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unsigned long win0_offset = DPM_HOST_WIN0_OFFSET;
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struct fsl_elbc_gpcm *priv = info->priv;
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const void *prop;
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/* get an optional initial win0 offset */
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prop = of_get_property(priv->dev->of_node,
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"netx5152,init-win0-offset", NULL);
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if (prop)
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win0_offset = of_read_ulong(prop, 1);
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/* disable interrupts */
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iowrite32(0, info->mem[0].internal_addr + win0_offset +
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DPM_HOST_INT_EN0);
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}
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static void netx5152_shutdown(struct uio_info *info, bool init_err)
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{
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if (init_err)
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return;
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/* disable interrupts */
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iowrite32(0, info->mem[0].internal_addr + DPM_HOST_WIN0_OFFSET +
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DPM_HOST_INT_EN0);
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}
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#endif
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static void setup_periph(struct fsl_elbc_gpcm *priv,
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const char *type)
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{
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#ifdef CONFIG_UIO_FSL_ELBC_GPCM_NETX5152
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if (strcmp(type, "netx5152") == 0) {
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priv->irq_handler = netx5152_irq_handler;
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priv->init = netx5152_init;
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priv->shutdown = netx5152_shutdown;
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priv->name = "netX 51/52";
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return;
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}
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#endif
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}
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static int check_of_data(struct fsl_elbc_gpcm *priv,
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struct resource *res,
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u32 reg_br, u32 reg_or)
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{
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/* check specified bank */
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if (priv->bank >= MAX_BANKS) {
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dev_err(priv->dev, "invalid bank\n");
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return -ENODEV;
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}
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/* check specified mode (BR_MS_GPCM is 0) */
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if ((reg_br & BR_MSEL) != BR_MS_GPCM) {
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dev_err(priv->dev, "unsupported mode\n");
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return -ENODEV;
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}
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/* check specified mask vs. resource size */
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if ((~(reg_or & OR_GPCM_AM) + 1) != resource_size(res)) {
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dev_err(priv->dev, "address mask / size mismatch\n");
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return -ENODEV;
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}
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/* check specified address */
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if ((reg_br & reg_or & BR_BA) != fsl_lbc_addr(res->start)) {
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dev_err(priv->dev, "base address mismatch\n");
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return -ENODEV;
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}
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return 0;
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}
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static int get_of_data(struct fsl_elbc_gpcm *priv, struct device_node *node,
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struct resource *res, u32 *reg_br,
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u32 *reg_or, unsigned int *irq, char **name)
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{
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const char *dt_name;
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const char *type;
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int ret;
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/* get the memory resource */
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ret = of_address_to_resource(node, 0, res);
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if (ret) {
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dev_err(priv->dev, "failed to get resource\n");
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return ret;
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}
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/* get the bank number */
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ret = of_property_read_u32(node, "reg", &priv->bank);
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if (ret) {
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dev_err(priv->dev, "failed to get bank number\n");
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return ret;
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}
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/* get BR value to set */
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ret = of_property_read_u32(node, "elbc-gpcm-br", reg_br);
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if (ret) {
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dev_err(priv->dev, "missing elbc-gpcm-br value\n");
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return ret;
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}
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/* get OR value to set */
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ret = of_property_read_u32(node, "elbc-gpcm-or", reg_or);
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if (ret) {
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dev_err(priv->dev, "missing elbc-gpcm-or value\n");
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return ret;
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}
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/* get optional peripheral type */
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priv->name = "generic";
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if (of_property_read_string(node, "device_type", &type) == 0)
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setup_periph(priv, type);
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/* get optional irq value */
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*irq = irq_of_parse_and_map(node, 0);
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/* sanity check device tree data */
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ret = check_of_data(priv, res, *reg_br, *reg_or);
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if (ret)
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return ret;
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/* get optional uio name */
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if (of_property_read_string(node, "uio_name", &dt_name) != 0)
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dt_name = "eLBC_GPCM";
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*name = kstrdup(dt_name, GFP_KERNEL);
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if (!*name)
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return -ENOMEM;
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return 0;
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}
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static int uio_fsl_elbc_gpcm_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct fsl_elbc_gpcm *priv;
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struct uio_info *info;
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char *uio_name = NULL;
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struct resource res;
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unsigned int irq;
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u32 reg_br_cur;
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u32 reg_or_cur;
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u32 reg_br_new;
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u32 reg_or_new;
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int ret;
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if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
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return -ENODEV;
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/* allocate private data */
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->dev = &pdev->dev;
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priv->lbc = fsl_lbc_ctrl_dev->regs;
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/* get device tree data */
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ret = get_of_data(priv, node, &res, ®_br_new, ®_or_new,
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&irq, &uio_name);
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if (ret)
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goto out_err0;
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/* allocate UIO structure */
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info = kzalloc(sizeof(*info), GFP_KERNEL);
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if (!info) {
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ret = -ENOMEM;
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goto out_err0;
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}
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/* get current BR/OR values */
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reg_br_cur = in_be32(&priv->lbc->bank[priv->bank].br);
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reg_or_cur = in_be32(&priv->lbc->bank[priv->bank].or);
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/* if bank already configured, make sure it matches */
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if ((reg_br_cur & BR_V)) {
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if ((reg_br_cur & BR_MSEL) != BR_MS_GPCM ||
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(reg_br_cur & reg_or_cur & BR_BA)
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!= fsl_lbc_addr(res.start)) {
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dev_err(priv->dev,
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"bank in use by another peripheral\n");
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ret = -ENODEV;
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goto out_err1;
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}
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/* warn if behavior settings changing */
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if ((reg_br_cur & ~(BR_BA | BR_V)) !=
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(reg_br_new & ~(BR_BA | BR_V))) {
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dev_warn(priv->dev,
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"modifying BR settings: 0x%08x -> 0x%08x",
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reg_br_cur, reg_br_new);
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}
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if ((reg_or_cur & ~OR_GPCM_AM) != (reg_or_new & ~OR_GPCM_AM)) {
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dev_warn(priv->dev,
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"modifying OR settings: 0x%08x -> 0x%08x",
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reg_or_cur, reg_or_new);
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}
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}
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/* configure the bank (force base address and GPCM) */
|
||||
reg_br_new &= ~(BR_BA | BR_MSEL);
|
||||
reg_br_new |= fsl_lbc_addr(res.start) | BR_MS_GPCM | BR_V;
|
||||
out_be32(&priv->lbc->bank[priv->bank].or, reg_or_new);
|
||||
out_be32(&priv->lbc->bank[priv->bank].br, reg_br_new);
|
||||
|
||||
/* map the memory resource */
|
||||
info->mem[0].internal_addr = ioremap(res.start, resource_size(&res));
|
||||
if (!info->mem[0].internal_addr) {
|
||||
dev_err(priv->dev, "failed to map chip region\n");
|
||||
ret = -ENODEV;
|
||||
goto out_err1;
|
||||
}
|
||||
|
||||
/* set all UIO data */
|
||||
if (node->name)
|
||||
info->mem[0].name = kstrdup(node->name, GFP_KERNEL);
|
||||
info->mem[0].addr = res.start;
|
||||
info->mem[0].size = resource_size(&res);
|
||||
info->mem[0].memtype = UIO_MEM_PHYS;
|
||||
info->priv = priv;
|
||||
info->name = uio_name;
|
||||
info->version = "0.0.1";
|
||||
if (irq != NO_IRQ) {
|
||||
if (priv->irq_handler) {
|
||||
info->irq = irq;
|
||||
info->irq_flags = IRQF_SHARED;
|
||||
info->handler = priv->irq_handler;
|
||||
} else {
|
||||
irq = NO_IRQ;
|
||||
dev_warn(priv->dev, "ignoring irq, no handler\n");
|
||||
}
|
||||
}
|
||||
|
||||
if (priv->init)
|
||||
priv->init(info);
|
||||
|
||||
/* register UIO device */
|
||||
if (uio_register_device(priv->dev, info) != 0) {
|
||||
dev_err(priv->dev, "UIO registration failed\n");
|
||||
ret = -ENODEV;
|
||||
goto out_err2;
|
||||
}
|
||||
|
||||
/* store private data */
|
||||
platform_set_drvdata(pdev, info);
|
||||
|
||||
/* create sysfs files */
|
||||
ret = device_create_file(priv->dev, &dev_attr_reg_br);
|
||||
if (ret)
|
||||
goto out_err3;
|
||||
ret = device_create_file(priv->dev, &dev_attr_reg_or);
|
||||
if (ret)
|
||||
goto out_err4;
|
||||
|
||||
dev_info(priv->dev,
|
||||
"eLBC/GPCM device (%s) at 0x%llx, bank %d, irq=%d\n",
|
||||
priv->name, (unsigned long long)res.start, priv->bank,
|
||||
irq != NO_IRQ ? irq : -1);
|
||||
|
||||
return 0;
|
||||
out_err4:
|
||||
device_remove_file(priv->dev, &dev_attr_reg_br);
|
||||
out_err3:
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
uio_unregister_device(info);
|
||||
out_err2:
|
||||
if (priv->shutdown)
|
||||
priv->shutdown(info, true);
|
||||
iounmap(info->mem[0].internal_addr);
|
||||
out_err1:
|
||||
kfree(info->mem[0].name);
|
||||
kfree(info);
|
||||
out_err0:
|
||||
kfree(uio_name);
|
||||
kfree(priv);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int uio_fsl_elbc_gpcm_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct uio_info *info = platform_get_drvdata(pdev);
|
||||
struct fsl_elbc_gpcm *priv = info->priv;
|
||||
|
||||
device_remove_file(priv->dev, &dev_attr_reg_or);
|
||||
device_remove_file(priv->dev, &dev_attr_reg_br);
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
uio_unregister_device(info);
|
||||
if (priv->shutdown)
|
||||
priv->shutdown(info, false);
|
||||
iounmap(info->mem[0].internal_addr);
|
||||
kfree(info->mem[0].name);
|
||||
kfree(info->name);
|
||||
kfree(info);
|
||||
kfree(priv);
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
static const struct of_device_id uio_fsl_elbc_gpcm_match[] = {
|
||||
{ .compatible = "fsl,elbc-gpcm-uio", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver uio_fsl_elbc_gpcm_driver = {
|
||||
.driver = {
|
||||
.name = "fsl,elbc-gpcm-uio",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = uio_fsl_elbc_gpcm_match,
|
||||
},
|
||||
.probe = uio_fsl_elbc_gpcm_probe,
|
||||
.remove = uio_fsl_elbc_gpcm_remove,
|
||||
};
|
||||
|
||||
static int __init uio_fsl_elbc_gpcm_init(void)
|
||||
{
|
||||
return platform_driver_register(&uio_fsl_elbc_gpcm_driver);
|
||||
}
|
||||
|
||||
static void __exit uio_fsl_elbc_gpcm_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&uio_fsl_elbc_gpcm_driver);
|
||||
}
|
||||
|
||||
module_init(uio_fsl_elbc_gpcm_init);
|
||||
module_exit(uio_fsl_elbc_gpcm_exit);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("John Ogness <john.ogness@linutronix.de>");
|
||||
MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller GPCM driver");
|
||||
Loading…
Reference in New Issue