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ARM: dts: sunxi: reference: Move the muxing back to the common DTSI 

Now that all the SoCs using the tablet reference design DTSI are using the
same pinctrl naming scheme, we can move back the pinctrl phandles to the
main DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
This commit is contained in:
Maxime Ripard 2018-11-21 12:05:00 +01:00
parent 9e41b5e966
commit fbb1f83c15
No known key found for this signature in database
GPG Key ID: E3EF0D6F671851C5
3 changed files with 3 additions and 20 deletions
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8
arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
View File

@ -76,8 +76,6 @@
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
axp209: pmic@34 {
reg = <0x34>;
interrupts = <0>;
@ -85,8 +83,6 @@
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
/*
* The gsl1680 is rated at 400KHz and it will not work reliable at
* 100KHz, this has been confirmed on multiple different q8 tablets.
@ -150,10 +146,6 @@
};
};
&pwm {
pinctrl-0 = <&pwm0_pin>;
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;

9
arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
View File

@ -62,7 +62,6 @@
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
/*
* The gsl1680 is rated at 400KHz and it will not work reliable at
* 100KHz, this has been confirmed on multiple different q8 tablets.
@ -80,10 +79,6 @@
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
@ -101,10 +96,6 @@
};
};
&pwm {
pinctrl-0 = <&pwm0_pin>;
};
&r_rsb {
status = "okay";

6
arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi
View File

@ -46,13 +46,13 @@
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
pinctrl-0 = <&i2c0_pins>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
@ -77,6 +77,6 @@
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pins>;
pinctrl-0 = <&pwm0_pin>;
status = "okay";
};