add null event check logic in riscv_pmu_sbi.c
Signed-off-by: lin peng <peng.lin@sophgo.com>
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7cb1cba6b2
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fbae4bce18
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@ -650,18 +650,20 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
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/* Reinitialize and start all the counter that overflowed */
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while (ctr_ovf_mask) {
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if (ctr_ovf_mask & 0x01) {
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event = cpu_hw_evt->events[idx];
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hwc = &event->hw;
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max_period = riscv_pmu_ctr_get_width_mask(event);
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init_val = local64_read(&hwc->prev_count) & max_period;
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if(event) {
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event = cpu_hw_evt->events[idx];
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hwc = &event->hw;
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max_period = riscv_pmu_ctr_get_width_mask(event);
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init_val = local64_read(&hwc->prev_count) & max_period;
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#if defined(CONFIG_32BIT)
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sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
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flag, init_val, init_val >> 32, 0);
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sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
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flag, init_val, init_val >> 32, 0);
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#else
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sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
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flag, init_val, 0, 0);
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sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
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flag, init_val, 0, 0);
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#endif
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perf_event_update_userpage(event);
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perf_event_update_userpage(event);
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}
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}
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ctr_ovf_mask = ctr_ovf_mask >> 1;
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idx++;
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