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sparc64: IO accessors fix 

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

I added a full memory clobber on all asm accessors except the _raw
ones.

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Benjamin Herrenschmidt 2008-05-30 02:01:28 -07:00 committed by David S. Miller
parent 551dec47bb
commit fbaa20f66a
1 changed files with 44 additions and 22 deletions
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66
include/asm-sparc64/io.h
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@ -24,7 +24,8 @@ static inline u8 _inb(unsigned long addr)
__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */" __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */"
: "=r" (ret) : "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
return ret; return ret;
} }
@ -35,7 +36,8 @@ static inline u16 _inw(unsigned long addr)
__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */" __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */"
: "=r" (ret) : "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
return ret; return ret;
} }
@ -46,7 +48,8 @@ static inline u32 _inl(unsigned long addr)
__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */" __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */"
: "=r" (ret) : "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
return ret; return ret;
} }
@ -55,21 +58,24 @@ static inline void _outb(u8 b, unsigned long addr)
{ {
__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */" __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */"
: /* no outputs */ : /* no outputs */
: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
} }
static inline void _outw(u16 w, unsigned long addr) static inline void _outw(u16 w, unsigned long addr)
{ {
__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */" __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */"
: /* no outputs */ : /* no outputs */
: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
} }
static inline void _outl(u32 l, unsigned long addr) static inline void _outl(u32 l, unsigned long addr)
{ {
__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */" __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */"
: /* no outputs */ : /* no outputs */
: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
} }
#define inb(__addr) (_inb((unsigned long)(__addr))) #define inb(__addr) (_inb((unsigned long)(__addr)))
@ -128,7 +134,8 @@ static inline u8 _readb(const volatile void __iomem *addr)
__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */" __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
: "=r" (ret) : "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
return ret; return ret;
} }
@ -137,7 +144,8 @@ static inline u16 _readw(const volatile void __iomem *addr)
__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */" __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
: "=r" (ret) : "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
return ret; return ret;
} }
@ -147,7 +155,8 @@ static inline u32 _readl(const volatile void __iomem *addr)
__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */" __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
: "=r" (ret) : "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
return ret; return ret;
} }
@ -157,7 +166,8 @@ static inline u64 _readq(const volatile void __iomem *addr)
__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */" __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
: "=r" (ret) : "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
return ret; return ret;
} }
@ -166,28 +176,32 @@ static inline void _writeb(u8 b, volatile void __iomem *addr)
{ {
__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */" __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
: /* no outputs */ : /* no outputs */
: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
} }
static inline void _writew(u16 w, volatile void __iomem *addr) static inline void _writew(u16 w, volatile void __iomem *addr)
{ {
__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */" __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
: /* no outputs */ : /* no outputs */
: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
} }
static inline void _writel(u32 l, volatile void __iomem *addr) static inline void _writel(u32 l, volatile void __iomem *addr)
{ {
__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */" __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
: /* no outputs */ : /* no outputs */
: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
} }
static inline void _writeq(u64 q, volatile void __iomem *addr) static inline void _writeq(u64 q, volatile void __iomem *addr)
{ {
__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */" __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
: /* no outputs */ : /* no outputs */
: "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
} }
#define readb(__addr) _readb(__addr) #define readb(__addr) _readb(__addr)
@ -299,7 +313,8 @@ static inline u8 _sbus_readb(const volatile void __iomem *addr)
__asm__ __volatile__("lduba\t[%1] %2, %0\t/* sbus_readb */" __asm__ __volatile__("lduba\t[%1] %2, %0\t/* sbus_readb */"
: "=r" (ret) : "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
: "memory");
return ret; return ret;
} }
@ -310,7 +325,8 @@ static inline u16 _sbus_readw(const volatile void __iomem *addr)
__asm__ __volatile__("lduha\t[%1] %2, %0\t/* sbus_readw */" __asm__ __volatile__("lduha\t[%1] %2, %0\t/* sbus_readw */"
: "=r" (ret) : "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
: "memory");
return ret; return ret;
} }
@ -321,7 +337,8 @@ static inline u32 _sbus_readl(const volatile void __iomem *addr)
__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* sbus_readl */" __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* sbus_readl */"
: "=r" (ret) : "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
: "memory");
return ret; return ret;
} }
@ -332,7 +349,8 @@ static inline u64 _sbus_readq(const volatile void __iomem *addr)
__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* sbus_readq */" __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* sbus_readq */"
: "=r" (ret) : "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
: "memory");
return ret; return ret;
} }
@ -341,28 +359,32 @@ static inline void _sbus_writeb(u8 b, volatile void __iomem *addr)
{ {
__asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */" __asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */"
: /* no outputs */ : /* no outputs */
: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
: "memory");
} }
static inline void _sbus_writew(u16 w, volatile void __iomem *addr) static inline void _sbus_writew(u16 w, volatile void __iomem *addr)
{ {
__asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */" __asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */"
: /* no outputs */ : /* no outputs */
: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
: "memory");
} }
static inline void _sbus_writel(u32 l, volatile void __iomem *addr) static inline void _sbus_writel(u32 l, volatile void __iomem *addr)
{ {
__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */" __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */"
: /* no outputs */ : /* no outputs */
: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
: "memory");
} }
static inline void _sbus_writeq(u64 l, volatile void __iomem *addr) static inline void _sbus_writeq(u64 l, volatile void __iomem *addr)
{ {
__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */" __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */"
: /* no outputs */ : /* no outputs */
: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
: "memory");
} }
#define sbus_readb(__addr) _sbus_readb(__addr) #define sbus_readb(__addr) _sbus_readb(__addr)