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[Blackfin] arch: Fix bug to Enable kernel to build for bf548 with PM. 

On BF548-EZKIT, build kernel faills with power management, video and audio enabled.
This patch fix this.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
This commit is contained in:
Sonic Zhang 2007-12-23 23:02:13 +08:00 committed by Bryan Wu
parent c50e19f498
commit fb5f00492a
7 changed files with 64 additions and 15 deletions
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2
arch/blackfin/Kconfig
View File

@ -951,6 +951,8 @@ config PM_WAKEUP_SIC_IWR
depends on PM_WAKEUP_GPIO_BY_SIC_IWR
default 0x80000000 if (BF537 || BF536 || BF534)
default 0x100000 if (BF533 || BF532 || BF531)
default 0x800000 if (BF549 || BF548 || BF547 || BF542)
default 0x800000 if (BF527 || BF524 || BF522)
config PM_WAKEUP_GPIO_NUMBER
int "Wakeup GPIO number"

8
arch/blackfin/mach-bf548/head.S
View File

@ -298,8 +298,8 @@ ENTRY(_start_dma_code)
w[p0] = r0.l;
ssync;
p0.h = hi(SIC_IWR);
p0.l = lo(SIC_IWR);
p0.h = hi(SIC_IWR0);
p0.l = lo(SIC_IWR0);
r0.l = 0x1;
r0.h = 0x0;
[p0] = r0;
@ -395,8 +395,8 @@ ENTRY(_start_dma_code)
[P2] = R1;
SSYNC;
p0.h = hi(SIC_IWR);
p0.l = lo(SIC_IWR);
p0.h = hi(SIC_IWR0);
p0.l = lo(SIC_IWR0);
r0.l = lo(IWR_ENABLE_ALL);
r0.h = hi(IWR_ENABLE_ALL);
[p0] = r0;

2
arch/blackfin/mach-bf548/ints-priority.c
View File

@ -58,7 +58,7 @@ void program_IAR(void)
((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) |
((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) |
((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) |
((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCHDOG_POS));
((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCH_POS));
bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) |
((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) |

46
arch/blackfin/mach-common/dpmc.S
View File

@ -38,6 +38,9 @@ ENTRY(_unmask_wdog_wakeup_evt)
#if defined(CONFIG_BF561)
P0.H = hi(SICA_IWR1);
P0.L = lo(SICA_IWR1);
#elif defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
P0.h = HI(SIC_IWR0);
P0.l = LO(SIC_IWR0);
#else
P0.h = HI(SIC_IWR);
P0.l = LO(SIC_IWR);
@ -236,7 +239,7 @@ ENTRY(_deep_sleep)
call _set_sic_iwr;
call _set_sdram_srfs;
call _set_dram_srfs;
/* Clear all the interrupts,bits sticky */
R0 = 0xFFFF (Z);
@ -253,7 +256,7 @@ ENTRY(_deep_sleep)
SSYNC;
IDLE;
call _unset_sdram_srfs;
call _unset_dram_srfs;
call _test_pll_locked;
@ -285,7 +288,7 @@ ENTRY(_sleep_deeper)
P3 = R0;
R0 = IWR_ENABLE(0);
call _set_sic_iwr;
call _set_sdram_srfs;
call _set_dram_srfs;
/* Clear all the interrupts,bits sticky */
R0 = 0xFFFF (Z);
@ -360,7 +363,7 @@ ENTRY(_sleep_deeper)
IDLE;
call _test_pll_locked;
call _unset_sdram_srfs;
call _unset_dram_srfs;
STI R4;
@ -368,25 +371,47 @@ ENTRY(_sleep_deeper)
( R7:0, P5:0 ) = [SP++];
RTS;
ENTRY(_set_sdram_srfs)
/* set the sdram to self refresh mode */
ENTRY(_set_dram_srfs)
/* set the dram to self refresh mode */
#if defined(CONFIG_BF54x)
P0.H = hi(EBIU_RSTCTL);
P0.L = lo(EBIU_RSTCTL);
R2 = [P0];
R3.H = hi(SRREQ);
R3.L = lo(SRREQ);
#else
P0.H = hi(EBIU_SDGCTL);
P0.L = lo(EBIU_SDGCTL);
R2 = [P0];
R3.H = hi(SRFS);
R3.L = lo(SRFS);
#endif
R2 = R2|R3;
[P0] = R2;
ssync;
#if defined(CONFIG_BF54x)
.LSRR_MODE:
R2 = [P0];
CC = BITTST(R2, 4);
if !CC JUMP .LSRR_MODE;
#endif
RTS;
ENTRY(_unset_sdram_srfs)
/* set the sdram out of self refresh mode */
ENTRY(_unset_dram_srfs)
/* set the dram out of self refresh mode */
#if defined(CONFIG_BF54x)
P0.H = hi(EBIU_RSTCTL);
P0.L = lo(EBIU_RSTCTL);
R2 = [P0];
R3.H = hi(SRREQ);
R3.L = lo(SRREQ);
#else
P0.H = hi(EBIU_SDGCTL);
P0.L = lo(EBIU_SDGCTL);
R2 = [P0];
R3.H = hi(SRFS);
R3.L = lo(SRFS);
#endif
R3 = ~R3;
R2 = R2&R3;
[P0] = R2;
@ -394,8 +419,13 @@ ENTRY(_unset_sdram_srfs)
RTS;
ENTRY(_set_sic_iwr)
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
P0.H = hi(SIC_IWR0);
P0.L = lo(SIC_IWR0);
#else
P0.H = hi(SIC_IWR);
P0.L = lo(SIC_IWR);
#endif
[P0] = R0;
SSYNC;
RTS;

16
arch/blackfin/mach-common/pm.c
View File

@ -77,7 +77,15 @@ void bfin_pm_suspend_standby_enter(void)
gpio_pm_restore();
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
# ifdef CONFIG_BF54x
bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
# endif
#else
bfin_write_SIC_IWR(IWR_ENABLE_ALL);
#endif
local_irq_restore(flags);
}
@ -85,7 +93,15 @@ void bfin_pm_suspend_standby_enter(void)
#if defined(CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR)
sleep_deeper(CONFIG_PM_WAKEUP_SIC_IWR);
# if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
# ifdef CONFIG_BF54x
bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
# endif
# else
bfin_write_SIC_IWR(IWR_ENABLE_ALL);
# endif
#endif /* CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR */
}

4
include/asm-blackfin/mach-bf548/irq.h
View File

@ -88,7 +88,7 @@ Events (highest priority) EMU 0
#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */
#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */
#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */
#define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */
#define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */
#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
@ -406,7 +406,7 @@ Events (highest priority) EMU 0
#define IRQ_PINT1_POS 16
#define IRQ_MDMAS0_POS 20
#define IRQ_MDMAS1_POS 24
#define IRQ_WATCHDOG_POS 28
#define IRQ_WATCH_POS 28
/* IAR3 BIT FIELDS */
#define IRQ_DMAC1_ERR_POS 0

1
include/asm-blackfin/mach-bf548/mem_init.h
View File

@ -30,6 +30,7 @@
*/
#if (CONFIG_MEM_MT46V32M16)
#endif
#if defined CONFIG_CLKIN_HALF
#define CLKIN_HALF 1