clk/samsung updates for v4.15
Overall clk/samsung clean up and fixes. Removed remaining unused code after removal of exynos4212 SoC support; dropped internal data structure fields and related code for registering clkdev lookup entry for each possible clock object, clkdev aliases could still be defined if needed in a separate table; other minor fixes of the clock tree definitions. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJZ4K7OAAoJEE1bIKeAnHqLlFUP/12Mnb3KIeO4WvNewZupUETd 2BWpPHMS/4Al216I+RAZIgBU5lxx9xv0lMUeSfOWXwPMh/xReCY3SQ3N11KTE6DW 6PwZpXtkYUyJ9sakVMNonczljfuWKFleRBscqPy3DH2S1vzG611lmmE8QvMmie2O shKrRQOwN7lWIGSQFdu1aSa/9OsHM9xsmgGGcAWMcpXTm26/nZ4EZxd7OU3nB39G fBzqjIP8hrvDKUi4b4+5uQxaXTYN8HKTmteWJzlXtXglVR55Wu7DmXXK4eFDLsmh iE3lkUnFK2cgkQjANJeeF/GK19ZvIVjlzEGX66IrAUG8qTDSgLDCWJRxW6qwm9jl KrSyC4d1D6GfymcVWUe8drixdeimVpOxyg/FCzyJXA8jkWUfwJJvi4eqJ3inPbh7 5fv84bTxm4xOhWYOLWu4r0Z9GvxDl/DyeW5tJhkGh7ZSWBWng9f2FDZp9aloJf4K DPopqAt5e+8NCe1jyKCNLdDrZxlHp7xyYu+n/xTAVOxS/BZJ+bKvuGIp6b39dzhB LMdTwwuwDCneEINROH09FqqH7y+HqyG2vR7cFaiShzP02OE0YGu20WlhRykzajFj XhXwfDiGzgTiLjuCS3BbtuYlgFxWAmjo81/3nuJ8MTZYDaXLWuaGCWHYvSc2+oFy AiNNDhap38/ed2cLdsgl =VHBX -----END PGP SIGNATURE----- Merge tag 'clk-v4.15-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next Pull Samsung clk driver updates from Sylwester Nawrocki: Overall clk/samsung clean up and fixes. Removed remaining unused code after removal of exynos4212 SoC support; dropped internal data structure fields and related code for registering clkdev lookup entry for each possible clock object, clkdev aliases could still be defined if needed in a separate table; other minor fixes of the clock tree definitions. * tag 'clk-v4.15-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: Remove obsolete clkdev alias support clk: samsung: Add explicit MPLL, EPLL clkdev aliases in S3C2443 driver clk: samsung: Rework clkdev alias handling in S3C2443 driver clk: samsung: Rework clkdev alias handling in Exynos5440 driver clk: samsung: Drop useless alias in Exynos5420 clk driver clk: samsung: Remove clkdev alias support in Exynos5250 clk driver clk: samsung: Remove double assignment of CLK_ARM_CLK in Exynos4 driver clk: samsung: Remove clkdev alias support in Exynos4 clk driver clk: samsung: Remove support for obsolete Exynos4212 CPU clock clk: samsung: Remove support for Exynos4212 SoCs in Exynos CLKOUT driver clk: samsung: Properly propagate flags in __PLL macro clk: samsung: Fix m2m scaler clock on Exynos542x clk: samsung: Delete a memory allocation error message in clk-cpu.c
This commit is contained in:
Stephen Boyd
commit
faa865f18c
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@ -457,8 +457,6 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
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cpuclk->cfg = kmemdup(cfg, sizeof(*cfg) * num_cfgs, GFP_KERNEL);
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if (!cpuclk->cfg) {
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pr_err("%s: could not allocate memory for cpuclk data\n",
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__func__);
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ret = -ENOMEM;
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goto unregister_clk_nb;
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}
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@ -144,8 +144,6 @@ static void __init exynos4_clkout_init(struct device_node *node)
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}
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CLK_OF_DECLARE_DRIVER(exynos4210_clkout, "samsung,exynos4210-pmu",
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exynos4_clkout_init);
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CLK_OF_DECLARE_DRIVER(exynos4212_clkout, "samsung,exynos4212-pmu",
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exynos4_clkout_init);
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CLK_OF_DECLARE_DRIVER(exynos4412_clkout, "samsung,exynos4412-pmu",
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exynos4_clkout_init);
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CLK_OF_DECLARE_DRIVER(exynos3250_clkout, "samsung,exynos3250-pmu",
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@ -550,9 +550,8 @@ static const struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __
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/* list of mux clocks supported in all exynos4 soc's */
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static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = {
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MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
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CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0,
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"mout_apll"),
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MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
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CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
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MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
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MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
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MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
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@ -737,7 +736,7 @@ static const struct samsung_div_clock exynos4_div_clks[] __initconst = {
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DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
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DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
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DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
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DIV(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3),
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DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
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DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
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DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
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DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
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@ -853,11 +852,6 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {
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/* list of gate clocks supported in all exynos4 soc's */
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static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = {
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/*
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* After all Exynos4 based platforms are migrated to use device tree,
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* the device name and clock alias names specified below for some
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* of the clocks can be removed.
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*/
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GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
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GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
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GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
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@ -1205,20 +1199,6 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {
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0),
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};
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static const struct samsung_clock_alias exynos4_aliases[] __initconst = {
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ALIAS(CLK_MOUT_CORE, NULL, "moutcore"),
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ALIAS(CLK_ARM_CLK, NULL, "armclk"),
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ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"),
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};
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static const struct samsung_clock_alias exynos4210_aliases[] __initconst = {
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ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"),
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};
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static const struct samsung_clock_alias exynos4x12_aliases[] __initconst = {
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ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"),
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};
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/*
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* The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
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* resides in chipid register space, outside of the clock controller memory
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@ -1355,14 +1335,14 @@ static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst =
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};
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static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
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[apll] = PLL_A(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
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APLL_LOCK, APLL_CON0, "fout_apll", NULL),
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[mpll] = PLL_A(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
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E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL),
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[epll] = PLL_A(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
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EPLL_LOCK, EPLL_CON0, "fout_epll", NULL),
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[vpll] = PLL_A(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
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VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL),
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[apll] = PLL(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
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APLL_LOCK, APLL_CON0, NULL),
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[mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
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E4210_MPLL_LOCK, E4210_MPLL_CON0, NULL),
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[epll] = PLL(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
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EPLL_LOCK, EPLL_CON0, NULL),
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[vpll] = PLL(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
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VPLL_LOCK, VPLL_CON0, NULL),
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};
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static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
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@ -1416,24 +1396,6 @@ static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
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{ 0 },
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};
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static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {
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{ 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
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{ 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
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{ 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
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{ 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
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{ 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },
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{ 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },
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{ 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
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{ 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
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{ 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
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{ 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
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{ 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
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{ 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
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{ 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
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{ 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },
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{ 0 },
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};
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#define E4412_CPU_DIV1(cores, hpm, copy) \
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(((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
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@ -1527,8 +1489,6 @@ static void __init exynos4_clk_init(struct device_node *np,
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ARRAY_SIZE(exynos4210_div_clks));
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samsung_clk_register_gate(ctx, exynos4210_gate_clks,
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ARRAY_SIZE(exynos4210_gate_clks));
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samsung_clk_register_alias(ctx, exynos4210_aliases,
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ARRAY_SIZE(exynos4210_aliases));
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samsung_clk_register_fixed_factor(ctx,
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exynos4210_fixed_factor_clks,
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ARRAY_SIZE(exynos4210_fixed_factor_clks));
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@ -1543,27 +1503,15 @@ static void __init exynos4_clk_init(struct device_node *np,
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ARRAY_SIZE(exynos4x12_div_clks));
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samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
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ARRAY_SIZE(exynos4x12_gate_clks));
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samsung_clk_register_alias(ctx, exynos4x12_aliases,
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ARRAY_SIZE(exynos4x12_aliases));
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samsung_clk_register_fixed_factor(ctx,
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exynos4x12_fixed_factor_clks,
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ARRAY_SIZE(exynos4x12_fixed_factor_clks));
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if (of_machine_is_compatible("samsung,exynos4412")) {
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exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
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mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
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e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
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CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
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} else {
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exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
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mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
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e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d),
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CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
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}
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exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
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mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
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e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
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CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
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}
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samsung_clk_register_alias(ctx, exynos4_aliases,
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ARRAY_SIZE(exynos4_aliases));
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if (soc == EXYNOS4X12)
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exynos4x12_core_down_clock();
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exynos4_clk_sleep_init();
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@ -293,14 +293,14 @@ static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {
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/*
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* CMU_CPU
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*/
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MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
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CLK_SET_RATE_PARENT, 0, "mout_apll"),
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MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
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MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
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CLK_SET_RATE_PARENT, 0),
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MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
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/*
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* CMU_CORE
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*/
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MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
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MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
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/*
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* CMU_TOP
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@ -391,7 +391,7 @@ static const struct samsung_div_clock exynos5250_div_clks[] __initconst = {
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*/
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DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
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DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
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DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"),
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DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
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/*
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* CMU_TOP
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@ -743,10 +743,10 @@ static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = {
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};
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static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
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[apll] = PLL_A(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
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APLL_LOCK, APLL_CON0, "fout_apll", NULL),
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[mpll] = PLL_A(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
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MPLL_LOCK, MPLL_CON0, "fout_mpll", NULL),
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[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
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APLL_CON0, NULL),
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[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
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MPLL_CON0, NULL),
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[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
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BPLL_CON0, NULL),
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[gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
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@ -600,8 +600,7 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
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TOP_SPARE2, 4, 1),
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MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
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MUX_A(0, "mout_aclk400_mscl", mout_group1_p,
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SRC_TOP0, 4, 2, "aclk400_mscl"),
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MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
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MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
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MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
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@ -998,7 +997,7 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
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GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
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GATE_BUS_TOP, 16, 0, 0),
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GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
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GATE_BUS_TOP, 17, 0, 0),
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GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0),
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GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
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GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0),
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GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
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@ -53,8 +53,7 @@ static const struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __
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/* mux clocks */
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static const struct samsung_mux_clock exynos5440_mux_clks[] __initconst = {
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MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
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MUX_A(CLK_ARM_CLK, "arm_clk", mout_armclk_p,
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CPU_CLK_STATUS, 0, 1, "armclk"),
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MUX(CLK_ARM_CLK, "arm_clk", mout_armclk_p, CPU_CLK_STATUS, 0, 1),
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};
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/* divider clocks */
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@ -117,6 +116,13 @@ static const struct samsung_pll_clock exynos5440_plls[] __initconst = {
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PLL(pll_2550x, CLK_CPLLB, "cpllb", "xtal", 0, 0x50, NULL),
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};
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/*
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* Clock aliases for legacy clkdev look-up.
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*/
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static const struct samsung_clock_alias exynos5440_aliases[] __initconst = {
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ALIAS(CLK_ARM_CLK, NULL, "armclk"),
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};
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/* register exynos5440 clocks */
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static void __init exynos5440_clk_init(struct device_node *np)
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||||
{
|
||||
|
|
@ -147,6 +153,8 @@ static void __init exynos5440_clk_init(struct device_node *np)
|
|||
ARRAY_SIZE(exynos5440_div_clks));
|
||||
samsung_clk_register_gate(ctx, exynos5440_gate_clks,
|
||||
ARRAY_SIZE(exynos5440_gate_clks));
|
||||
samsung_clk_register_alias(ctx, exynos5440_aliases,
|
||||
ARRAY_SIZE(exynos5440_aliases));
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
|
||||
|
|
|
|||
|
|
@ -1397,15 +1397,6 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
|||
}
|
||||
|
||||
samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id);
|
||||
|
||||
if (!pll_clk->alias)
|
||||
return;
|
||||
|
||||
ret = clk_hw_register_clkdev(&pll->hw, pll_clk->alias,
|
||||
pll_clk->dev_name);
|
||||
if (ret)
|
||||
pr_err("%s: failed to register lookup for %s : %d",
|
||||
__func__, pll_clk->name, ret);
|
||||
}
|
||||
|
||||
void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
||||
|
|
|
|||
|
|
@ -117,8 +117,8 @@ struct samsung_mux_clock s3c2443_common_muxes[] __initdata = {
|
|||
MUX(0, "epllref", epllref_p, CLKSRC, 7, 2),
|
||||
MUX(ESYSCLK, "esysclk", esysclk_p, CLKSRC, 6, 1),
|
||||
MUX(0, "mpllref", mpllref_p, CLKSRC, 3, 1),
|
||||
MUX_A(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1, "msysclk"),
|
||||
MUX_A(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1, "armclk"),
|
||||
MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
|
||||
MUX(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1),
|
||||
MUX(0, "mux_i2s0", i2s0_p, CLKSRC, 14, 2),
|
||||
};
|
||||
|
||||
|
|
@ -189,6 +189,10 @@ struct samsung_gate_clock s3c2443_common_gates[] __initdata = {
|
|||
};
|
||||
|
||||
struct samsung_clock_alias s3c2443_common_aliases[] __initdata = {
|
||||
ALIAS(MSYSCLK, NULL, "msysclk"),
|
||||
ALIAS(ARMCLK, NULL, "armclk"),
|
||||
ALIAS(MPLL, NULL, "mpll"),
|
||||
ALIAS(EPLL, NULL, "epll"),
|
||||
ALIAS(HCLK, NULL, "hclk"),
|
||||
ALIAS(HCLK_SSMC, NULL, "nand"),
|
||||
ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
|
||||
|
|
@ -221,9 +225,9 @@ struct samsung_clock_alias s3c2443_common_aliases[] __initdata = {
|
|||
/* S3C2416 specific clocks */
|
||||
|
||||
static struct samsung_pll_clock s3c2416_pll_clks[] __initdata = {
|
||||
[mpll] = PLL(pll_6552_s3c2416, 0, "mpll", "mpllref",
|
||||
[mpll] = PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref",
|
||||
LOCKCON0, MPLLCON, NULL),
|
||||
[epll] = PLL(pll_6553, 0, "epll", "epllref",
|
||||
[epll] = PLL(pll_6553, EPLL, "epll", "epllref",
|
||||
LOCKCON1, EPLLCON, NULL),
|
||||
};
|
||||
|
||||
|
|
@ -275,9 +279,9 @@ struct samsung_clock_alias s3c2416_aliases[] __initdata = {
|
|||
/* S3C2443 specific clocks */
|
||||
|
||||
static struct samsung_pll_clock s3c2443_pll_clks[] __initdata = {
|
||||
[mpll] = PLL(pll_3000, 0, "mpll", "mpllref",
|
||||
[mpll] = PLL(pll_3000, MPLL, "mpll", "mpllref",
|
||||
LOCKCON0, MPLLCON, NULL),
|
||||
[epll] = PLL(pll_2126, 0, "epll", "epllref",
|
||||
[epll] = PLL(pll_2126, EPLL, "epll", "epllref",
|
||||
LOCKCON1, EPLLCON, NULL),
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -181,7 +181,7 @@ void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
|
|||
unsigned int nr_clk)
|
||||
{
|
||||
struct clk_hw *clk_hw;
|
||||
unsigned int idx, ret;
|
||||
unsigned int idx;
|
||||
|
||||
for (idx = 0; idx < nr_clk; idx++, list++) {
|
||||
clk_hw = clk_hw_register_mux(ctx->dev, list->name,
|
||||
|
|
@ -195,15 +195,6 @@ void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
|
|||
}
|
||||
|
||||
samsung_clk_add_lookup(ctx, clk_hw, list->id);
|
||||
|
||||
/* register a clock lookup only if a clock alias is specified */
|
||||
if (list->alias) {
|
||||
ret = clk_hw_register_clkdev(clk_hw, list->alias,
|
||||
list->dev_name);
|
||||
if (ret)
|
||||
pr_err("%s: failed to register lookup %s\n",
|
||||
__func__, list->alias);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -213,7 +204,7 @@ void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
|
|||
unsigned int nr_clk)
|
||||
{
|
||||
struct clk_hw *clk_hw;
|
||||
unsigned int idx, ret;
|
||||
unsigned int idx;
|
||||
|
||||
for (idx = 0; idx < nr_clk; idx++, list++) {
|
||||
if (list->table)
|
||||
|
|
@ -234,15 +225,6 @@ void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
|
|||
}
|
||||
|
||||
samsung_clk_add_lookup(ctx, clk_hw, list->id);
|
||||
|
||||
/* register a clock lookup only if a clock alias is specified */
|
||||
if (list->alias) {
|
||||
ret = clk_hw_register_clkdev(clk_hw, list->alias,
|
||||
list->dev_name);
|
||||
if (ret)
|
||||
pr_err("%s: failed to register lookup %s\n",
|
||||
__func__, list->alias);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -252,7 +234,7 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
|
|||
unsigned int nr_clk)
|
||||
{
|
||||
struct clk_hw *clk_hw;
|
||||
unsigned int idx, ret;
|
||||
unsigned int idx;
|
||||
|
||||
for (idx = 0; idx < nr_clk; idx++, list++) {
|
||||
clk_hw = clk_hw_register_gate(ctx->dev, list->name, list->parent_name,
|
||||
|
|
@ -264,15 +246,6 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
|
|||
continue;
|
||||
}
|
||||
|
||||
/* register a clock lookup only if a clock alias is specified */
|
||||
if (list->alias) {
|
||||
ret = clk_hw_register_clkdev(clk_hw, list->alias,
|
||||
list->dev_name);
|
||||
if (ret)
|
||||
pr_err("%s: failed to register lookup %s\n",
|
||||
__func__, list->alias);
|
||||
}
|
||||
|
||||
samsung_clk_add_lookup(ctx, clk_hw, list->id);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -107,7 +107,6 @@ struct samsung_fixed_factor_clock {
|
|||
/**
|
||||
* struct samsung_mux_clock: information about mux clock
|
||||
* @id: platform specific id of the clock.
|
||||
* @dev_name: name of the device to which this clock belongs.
|
||||
* @name: name of this mux clock.
|
||||
* @parent_names: array of pointer to parent clock names.
|
||||
* @num_parents: number of parents listed in @parent_names.
|
||||
|
|
@ -116,11 +115,9 @@ struct samsung_fixed_factor_clock {
|
|||
* @shift: starting bit location of the mux control bit-field in @reg.
|
||||
* @width: width of the mux control bit-field in @reg.
|
||||
* @mux_flags: flags for mux-type clock.
|
||||
* @alias: optional clock alias name to be assigned to this clock.
|
||||
*/
|
||||
struct samsung_mux_clock {
|
||||
unsigned int id;
|
||||
const char *dev_name;
|
||||
const char *name;
|
||||
const char *const *parent_names;
|
||||
u8 num_parents;
|
||||
|
|
@ -129,13 +126,11 @@ struct samsung_mux_clock {
|
|||
u8 shift;
|
||||
u8 width;
|
||||
u8 mux_flags;
|
||||
const char *alias;
|
||||
};
|
||||
|
||||
#define __MUX(_id, dname, cname, pnames, o, s, w, f, mf, a) \
|
||||
#define __MUX(_id, cname, pnames, o, s, w, f, mf) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.dev_name = dname, \
|
||||
.name = cname, \
|
||||
.parent_names = pnames, \
|
||||
.num_parents = ARRAY_SIZE(pnames), \
|
||||
|
|
@ -144,36 +139,26 @@ struct samsung_mux_clock {
|
|||
.shift = s, \
|
||||
.width = w, \
|
||||
.mux_flags = mf, \
|
||||
.alias = a, \
|
||||
}
|
||||
|
||||
#define MUX(_id, cname, pnames, o, s, w) \
|
||||
__MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, NULL)
|
||||
|
||||
#define MUX_A(_id, cname, pnames, o, s, w, a) \
|
||||
__MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, a)
|
||||
__MUX(_id, cname, pnames, o, s, w, 0, 0)
|
||||
|
||||
#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \
|
||||
__MUX(_id, NULL, cname, pnames, o, s, w, f, mf, NULL)
|
||||
|
||||
#define MUX_FA(_id, cname, pnames, o, s, w, f, mf, a) \
|
||||
__MUX(_id, NULL, cname, pnames, o, s, w, f, mf, a)
|
||||
__MUX(_id, cname, pnames, o, s, w, f, mf)
|
||||
|
||||
/**
|
||||
* @id: platform specific id of the clock.
|
||||
* struct samsung_div_clock: information about div clock
|
||||
* @dev_name: name of the device to which this clock belongs.
|
||||
* @name: name of this div clock.
|
||||
* @parent_name: name of the parent clock.
|
||||
* @flags: optional flags for basic clock.
|
||||
* @offset: offset of the register for configuring the div.
|
||||
* @shift: starting bit location of the div control bit-field in @reg.
|
||||
* @div_flags: flags for div-type clock.
|
||||
* @alias: optional clock alias name to be assigned to this clock.
|
||||
*/
|
||||
struct samsung_div_clock {
|
||||
unsigned int id;
|
||||
const char *dev_name;
|
||||
const char *name;
|
||||
const char *parent_name;
|
||||
unsigned long flags;
|
||||
|
|
@ -181,14 +166,12 @@ struct samsung_div_clock {
|
|||
u8 shift;
|
||||
u8 width;
|
||||
u8 div_flags;
|
||||
const char *alias;
|
||||
struct clk_div_table *table;
|
||||
};
|
||||
|
||||
#define __DIV(_id, dname, cname, pname, o, s, w, f, df, a, t) \
|
||||
#define __DIV(_id, cname, pname, o, s, w, f, df, t) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.dev_name = dname, \
|
||||
.name = cname, \
|
||||
.parent_name = pname, \
|
||||
.flags = f, \
|
||||
|
|
@ -196,70 +179,51 @@ struct samsung_div_clock {
|
|||
.shift = s, \
|
||||
.width = w, \
|
||||
.div_flags = df, \
|
||||
.alias = a, \
|
||||
.table = t, \
|
||||
}
|
||||
|
||||
#define DIV(_id, cname, pname, o, s, w) \
|
||||
__DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, NULL)
|
||||
|
||||
#define DIV_A(_id, cname, pname, o, s, w, a) \
|
||||
__DIV(_id, NULL, cname, pname, o, s, w, 0, 0, a, NULL)
|
||||
__DIV(_id, cname, pname, o, s, w, 0, 0, NULL)
|
||||
|
||||
#define DIV_F(_id, cname, pname, o, s, w, f, df) \
|
||||
__DIV(_id, NULL, cname, pname, o, s, w, f, df, NULL, NULL)
|
||||
__DIV(_id, cname, pname, o, s, w, f, df, NULL)
|
||||
|
||||
#define DIV_T(_id, cname, pname, o, s, w, t) \
|
||||
__DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, t)
|
||||
__DIV(_id, cname, pname, o, s, w, 0, 0, t)
|
||||
|
||||
/**
|
||||
* struct samsung_gate_clock: information about gate clock
|
||||
* @id: platform specific id of the clock.
|
||||
* @dev_name: name of the device to which this clock belongs.
|
||||
* @name: name of this gate clock.
|
||||
* @parent_name: name of the parent clock.
|
||||
* @flags: optional flags for basic clock.
|
||||
* @offset: offset of the register for configuring the gate.
|
||||
* @bit_idx: bit index of the gate control bit-field in @reg.
|
||||
* @gate_flags: flags for gate-type clock.
|
||||
* @alias: optional clock alias name to be assigned to this clock.
|
||||
*/
|
||||
struct samsung_gate_clock {
|
||||
unsigned int id;
|
||||
const char *dev_name;
|
||||
const char *name;
|
||||
const char *parent_name;
|
||||
unsigned long flags;
|
||||
unsigned long offset;
|
||||
u8 bit_idx;
|
||||
u8 gate_flags;
|
||||
const char *alias;
|
||||
};
|
||||
|
||||
#define __GATE(_id, dname, cname, pname, o, b, f, gf, a) \
|
||||
#define __GATE(_id, cname, pname, o, b, f, gf) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.dev_name = dname, \
|
||||
.name = cname, \
|
||||
.parent_name = pname, \
|
||||
.flags = f, \
|
||||
.offset = o, \
|
||||
.bit_idx = b, \
|
||||
.gate_flags = gf, \
|
||||
.alias = a, \
|
||||
}
|
||||
|
||||
#define GATE(_id, cname, pname, o, b, f, gf) \
|
||||
__GATE(_id, NULL, cname, pname, o, b, f, gf, NULL)
|
||||
|
||||
#define GATE_A(_id, cname, pname, o, b, f, gf, a) \
|
||||
__GATE(_id, NULL, cname, pname, o, b, f, gf, a)
|
||||
|
||||
#define GATE_D(_id, dname, cname, pname, o, b, f, gf) \
|
||||
__GATE(_id, dname, cname, pname, o, b, f, gf, NULL)
|
||||
|
||||
#define GATE_DA(_id, dname, cname, pname, o, b, f, gf, a) \
|
||||
__GATE(_id, dname, cname, pname, o, b, f, gf, a)
|
||||
__GATE(_id, cname, pname, o, b, f, gf)
|
||||
|
||||
#define PNAME(x) static const char * const x[] __initconst
|
||||
|
||||
|
|
@ -276,18 +240,15 @@ struct samsung_clk_reg_dump {
|
|||
/**
|
||||
* struct samsung_pll_clock: information about pll clock
|
||||
* @id: platform specific id of the clock.
|
||||
* @dev_name: name of the device to which this clock belongs.
|
||||
* @name: name of this pll clock.
|
||||
* @parent_name: name of the parent clock.
|
||||
* @flags: optional flags for basic clock.
|
||||
* @con_offset: offset of the register for configuring the PLL.
|
||||
* @lock_offset: offset of the register for locking the PLL.
|
||||
* @type: Type of PLL to be registered.
|
||||
* @alias: optional clock alias name to be assigned to this clock.
|
||||
*/
|
||||
struct samsung_pll_clock {
|
||||
unsigned int id;
|
||||
const char *dev_name;
|
||||
const char *name;
|
||||
const char *parent_name;
|
||||
unsigned long flags;
|
||||
|
|
@ -295,31 +256,23 @@ struct samsung_pll_clock {
|
|||
int lock_offset;
|
||||
enum samsung_pll_type type;
|
||||
const struct samsung_pll_rate_table *rate_table;
|
||||
const char *alias;
|
||||
};
|
||||
|
||||
#define __PLL(_typ, _id, _dname, _name, _pname, _flags, _lock, _con, \
|
||||
_rtable, _alias) \
|
||||
#define __PLL(_typ, _id, _name, _pname, _flags, _lock, _con, _rtable) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.type = _typ, \
|
||||
.dev_name = _dname, \
|
||||
.name = _name, \
|
||||
.parent_name = _pname, \
|
||||
.flags = CLK_GET_RATE_NOCACHE, \
|
||||
.flags = _flags, \
|
||||
.con_offset = _con, \
|
||||
.lock_offset = _lock, \
|
||||
.rate_table = _rtable, \
|
||||
.alias = _alias, \
|
||||
}
|
||||
|
||||
#define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable) \
|
||||
__PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \
|
||||
_lock, _con, _rtable, _name)
|
||||
|
||||
#define PLL_A(_typ, _id, _name, _pname, _lock, _con, _alias, _rtable) \
|
||||
__PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \
|
||||
_lock, _con, _rtable, _alias)
|
||||
__PLL(_typ, _id, _name, _pname, CLK_GET_RATE_NOCACHE, _lock, \
|
||||
_con, _rtable)
|
||||
|
||||
struct samsung_clock_reg_cache {
|
||||
struct list_head node;
|
||||
|
|
|
|||
|
|
@ -26,6 +26,8 @@
|
|||
#define ARMCLK 4
|
||||
#define HCLK 5
|
||||
#define PCLK 6
|
||||
#define MPLL 7
|
||||
#define EPLL 8
|
||||
|
||||
/* Special clocks */
|
||||
#define SCLK_HSSPI0 16
|
||||
|
|
|
|||
Loading…
Reference in New Issue