powerpc/lib: Use patch_site to patch copy_32 functions once cache is enabled
The symbol memcpy_nocache_branch defined in order to allow patching of memset function once cache is enabled leads to confusing reports by perf tool. Using the new patch_site functionality solves this issue. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -146,6 +146,7 @@ void _kvmppc_save_tm_pr(struct kvm_vcpu *vcpu, u64 guest_msr);
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/* Patch sites */
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/* Patch sites */
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extern s32 patch__call_flush_count_cache;
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extern s32 patch__call_flush_count_cache;
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extern s32 patch__flush_count_cache_return;
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extern s32 patch__flush_count_cache_return;
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extern s32 patch__memset_nocache, patch__memcpy_nocache;
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extern long flush_count_cache;
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extern long flush_count_cache;
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@ -97,11 +97,10 @@ notrace unsigned long __init early_init(unsigned long dt_ptr)
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* We do the initial parsing of the flat device-tree and prepares
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* We do the initial parsing of the flat device-tree and prepares
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* for the MMU to be fully initialized.
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* for the MMU to be fully initialized.
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*/
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*/
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extern unsigned int memset_nocache_branch; /* Insn to be replaced by NOP */
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notrace void __init machine_init(u64 dt_ptr)
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notrace void __init machine_init(u64 dt_ptr)
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{
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{
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unsigned int *addr = &memset_nocache_branch;
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unsigned int *addr = (unsigned int *)((unsigned long)&patch__memset_nocache +
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patch__memset_nocache);
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unsigned long insn;
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unsigned long insn;
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/* Configure static keys first, now that we're relocated. */
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/* Configure static keys first, now that we're relocated. */
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@ -110,7 +109,7 @@ notrace void __init machine_init(u64 dt_ptr)
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/* Enable early debugging if any specified (see udbg.h) */
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/* Enable early debugging if any specified (see udbg.h) */
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udbg_early_init();
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udbg_early_init();
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patch_instruction((unsigned int *)&memcpy, PPC_INST_NOP);
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patch_instruction_site(&patch__memcpy_nocache, PPC_INST_NOP);
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insn = create_cond_branch(addr, branch_target(addr), 0x820000);
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insn = create_cond_branch(addr, branch_target(addr), 0x820000);
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patch_instruction(addr, insn); /* replace b by bne cr0 */
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patch_instruction(addr, insn); /* replace b by bne cr0 */
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@ -13,6 +13,7 @@
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#include <asm/errno.h>
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#include <asm/errno.h>
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#include <asm/ppc_asm.h>
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#include <asm/ppc_asm.h>
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#include <asm/export.h>
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#include <asm/export.h>
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#include <asm/code-patching-asm.h>
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#define COPY_16_BYTES \
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#define COPY_16_BYTES \
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lwz r7,4(r4); \
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lwz r7,4(r4); \
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@ -107,8 +108,8 @@ _GLOBAL(memset)
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* Skip optimised bloc until cache is enabled. Will be replaced
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* Skip optimised bloc until cache is enabled. Will be replaced
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* by 'bne' during boot to use normal procedure if r4 is not zero
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* by 'bne' during boot to use normal procedure if r4 is not zero
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*/
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*/
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_GLOBAL(memset_nocache_branch)
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5: b 2f
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b 2f
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patch_site 5b, patch__memset_nocache
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clrlwi r7,r6,32-LG_CACHELINE_BYTES
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clrlwi r7,r6,32-LG_CACHELINE_BYTES
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add r8,r7,r5
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add r8,r7,r5
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@ -168,7 +169,9 @@ _GLOBAL(memmove)
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/* fall through */
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/* fall through */
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_GLOBAL(memcpy)
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_GLOBAL(memcpy)
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b generic_memcpy
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1: b generic_memcpy
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patch_site 1b, patch__memcpy_nocache
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add r7,r3,r5 /* test if the src & dst overlap */
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add r7,r3,r5 /* test if the src & dst overlap */
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add r8,r4,r5
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add r8,r4,r5
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cmplw 0,r4,r7
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cmplw 0,r4,r7
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