irqchip/stm32: Add host and driver data structures
This patch adds host and driver data structures to support different stm32 exti controllers with variants. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
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d9e2b19b02
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f9fc174550
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@ -29,13 +29,23 @@ struct stm32_exti_bank {
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#define UNDEF_REG ~0
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struct stm32_exti_drv_data {
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const struct stm32_exti_bank **exti_banks;
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u32 bank_nr;
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};
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struct stm32_exti_chip_data {
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struct stm32_exti_host_data *host_data;
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const struct stm32_exti_bank *reg_bank;
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u32 rtsr_cache;
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u32 ftsr_cache;
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};
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static struct stm32_exti_chip_data *stm32_exti_data;
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struct stm32_exti_host_data {
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void __iomem *base;
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struct stm32_exti_chip_data *chips_data;
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const struct stm32_exti_drv_data *drv_data;
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};
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static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
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.imr_ofst = 0x00,
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@ -51,6 +61,11 @@ static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
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&stm32f4xx_exti_b1,
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};
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static const struct stm32_exti_drv_data stm32f4xx_drv_data = {
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.exti_banks = stm32f4xx_exti_banks,
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.bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks),
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};
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static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
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.imr_ofst = 0x80,
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.emr_ofst = 0x84,
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@ -87,6 +102,11 @@ static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
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&stm32h7xx_exti_b3,
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};
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static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
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.exti_banks = stm32h7xx_exti_banks,
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.bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
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};
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static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
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{
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struct stm32_exti_chip_data *chip_data = gc->private;
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@ -237,29 +257,85 @@ static void stm32_irq_ack(struct irq_data *d)
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irq_gc_unlock(gc);
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}
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static int
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__init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
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int bank_nr, struct device_node *node)
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static struct
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stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
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struct device_node *node)
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{
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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int nr_irqs, nr_exti, ret, i;
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struct irq_chip_generic *gc;
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struct irq_domain *domain;
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void *base;
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struct stm32_exti_host_data *host_data;
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base = of_iomap(node, 0);
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if (!base) {
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host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
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if (!host_data)
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return NULL;
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host_data->drv_data = dd;
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host_data->chips_data = kcalloc(dd->bank_nr,
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sizeof(struct stm32_exti_chip_data),
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GFP_KERNEL);
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if (!host_data->chips_data)
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return NULL;
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host_data->base = of_iomap(node, 0);
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if (!host_data->base) {
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pr_err("%pOF: Unable to map registers\n", node);
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return -ENOMEM;
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return NULL;
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}
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stm32_exti_data = kcalloc(bank_nr, sizeof(*stm32_exti_data),
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GFP_KERNEL);
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if (!stm32_exti_data)
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return -ENOMEM;
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return host_data;
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}
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domain = irq_domain_add_linear(node, bank_nr * IRQS_PER_BANK,
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static struct
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stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
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u32 bank_idx,
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struct device_node *node)
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{
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const struct stm32_exti_bank *stm32_bank;
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struct stm32_exti_chip_data *chip_data;
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void __iomem *base = h_data->base;
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u32 irqs_mask;
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stm32_bank = h_data->drv_data->exti_banks[bank_idx];
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chip_data = &h_data->chips_data[bank_idx];
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chip_data->host_data = h_data;
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chip_data->reg_bank = stm32_bank;
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/* Determine number of irqs supported */
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writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst);
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irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst);
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/*
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* This IP has no reset, so after hot reboot we should
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* clear registers to avoid residue
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*/
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writel_relaxed(0, base + stm32_bank->imr_ofst);
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writel_relaxed(0, base + stm32_bank->emr_ofst);
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writel_relaxed(0, base + stm32_bank->rtsr_ofst);
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writel_relaxed(0, base + stm32_bank->ftsr_ofst);
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writel_relaxed(~0UL, base + stm32_bank->rpr_ofst);
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if (stm32_bank->fpr_ofst != UNDEF_REG)
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writel_relaxed(~0UL, base + stm32_bank->fpr_ofst);
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pr_info("%s: bank%d, External IRQs available:%#x\n",
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node->full_name, bank_idx, irqs_mask);
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return chip_data;
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}
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static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
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struct device_node *node)
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{
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struct stm32_exti_host_data *host_data;
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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int nr_irqs, ret, i;
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struct irq_chip_generic *gc;
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struct irq_domain *domain;
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host_data = stm32_exti_host_init(drv_data, node);
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if (!host_data) {
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ret = -ENOMEM;
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goto out_free_mem;
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}
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domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
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&irq_exti_domain_ops, NULL);
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if (!domain) {
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pr_err("%s: Could not register interrupt domain.\n",
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@ -276,16 +352,16 @@ __init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
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goto out_free_domain;
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}
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for (i = 0; i < bank_nr; i++) {
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const struct stm32_exti_bank *stm32_bank = stm32_exti_banks[i];
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struct stm32_exti_chip_data *chip_data = &stm32_exti_data[i];
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u32 irqs_mask;
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for (i = 0; i < drv_data->bank_nr; i++) {
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const struct stm32_exti_bank *stm32_bank;
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struct stm32_exti_chip_data *chip_data;
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chip_data->reg_bank = stm32_bank;
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stm32_bank = drv_data->exti_banks[i];
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chip_data = stm32_exti_chip_init(host_data, i, node);
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gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
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gc->reg_base = base;
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gc->reg_base = host_data->base;
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gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
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gc->chip_types->chip.irq_ack = stm32_irq_ack;
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gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
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@ -298,26 +374,6 @@ __init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
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gc->chip_types->regs.mask = stm32_bank->imr_ofst;
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gc->private = (void *)chip_data;
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/* Determine number of irqs supported */
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writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst);
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irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst);
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nr_exti = fls(readl_relaxed(base + stm32_bank->rtsr_ofst));
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/*
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* This IP has no reset, so after hot reboot we should
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* clear registers to avoid residue
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*/
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writel_relaxed(0, base + stm32_bank->imr_ofst);
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writel_relaxed(0, base + stm32_bank->emr_ofst);
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writel_relaxed(0, base + stm32_bank->rtsr_ofst);
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writel_relaxed(0, base + stm32_bank->ftsr_ofst);
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writel_relaxed(~0UL, base + stm32_bank->rpr_ofst);
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if (stm32_bank->fpr_ofst != UNDEF_REG)
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writel_relaxed(~0UL, base + stm32_bank->fpr_ofst);
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pr_info("%s: bank%d, External IRQs available:%#x\n",
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node->full_name, i, irqs_mask);
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}
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nr_irqs = of_irq_count(node);
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@ -333,16 +389,17 @@ __init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
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out_free_domain:
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irq_domain_remove(domain);
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out_unmap:
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iounmap(base);
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kfree(stm32_exti_data);
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iounmap(host_data->base);
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out_free_mem:
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kfree(host_data->chips_data);
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kfree(host_data);
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return ret;
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}
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static int __init stm32f4_exti_of_init(struct device_node *np,
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struct device_node *parent)
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{
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return stm32_exti_init(stm32f4xx_exti_banks,
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ARRAY_SIZE(stm32f4xx_exti_banks), np);
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return stm32_exti_init(&stm32f4xx_drv_data, np);
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}
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IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
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@ -350,8 +407,7 @@ IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
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static int __init stm32h7_exti_of_init(struct device_node *np,
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struct device_node *parent)
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{
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return stm32_exti_init(stm32h7xx_exti_banks,
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ARRAY_SIZE(stm32h7xx_exti_banks), np);
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return stm32_exti_init(&stm32h7xx_drv_data, np);
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}
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IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);
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