Blackfin: bf537-stamp: update GPIO CS devices
Now that we've rewritten the GPIO CS handling in the Blackfin SPI peripheral, we need to update the platform resources accordingly. Signed-off-by: Barry Song <barry.song@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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@ -824,14 +824,12 @@ static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
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static struct bfin5xx_spi_chip enc28j60_spi_chip_info = {
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.enable_dma = 1,
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.bits_per_word = 8,
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.cs_gpio = GPIO_PF10,
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};
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#endif
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#if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE)
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static struct bfin5xx_spi_chip adf7021_spi_chip_info = {
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.bits_per_word = 16,
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.cs_gpio = GPIO_PF10,
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};
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#include <linux/spi/adf702x.h>
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@ -1103,7 +1101,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
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.max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
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.irq = IRQ_PF6,
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.bus_num = 0,
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.chip_select = 0, /* GPIO controlled SSEL */
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.chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
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.controller_data = &enc28j60_spi_chip_info,
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.mode = SPI_MODE_0,
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},
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@ -1125,7 +1123,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
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.modalias = "adf702x",
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.max_speed_hz = 16000000, /* max spi clock (SCK) speed in HZ */
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.bus_num = 0,
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.chip_select = 0, /* GPIO controlled SSEL */
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.chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
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.controller_data = &adf7021_spi_chip_info,
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.platform_data = &adf7021_platform_data,
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.mode = SPI_MODE_0,
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@ -1148,7 +1146,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
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#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
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/* SPI controller data */
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static struct bfin5xx_spi_master bfin_spi0_info = {
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.num_chipselect = 8,
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.num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
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.enable_dma = 1, /* master has the ability to do dma transfer */
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.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
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};
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