Merge branch 'pci/enumeration' into next
* pci/enumeration: PCI: Enable ECRC only if device supports it PCI: Add sysfs max_link_speed/width, current_link_speed/width, etc PCI: Test INTx masking during enumeration, not at run-time
This commit is contained in:
Bjorn Helgaas
commit
f9bfeccd66
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@ -154,6 +154,129 @@ static ssize_t resource_show(struct device *dev, struct device_attribute *attr,
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}
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static DEVICE_ATTR_RO(resource);
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static ssize_t max_link_speed_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct pci_dev *pci_dev = to_pci_dev(dev);
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u32 linkcap;
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int err;
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const char *speed;
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err = pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &linkcap);
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if (err)
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return -EINVAL;
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switch (linkcap & PCI_EXP_LNKCAP_SLS) {
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case PCI_EXP_LNKCAP_SLS_8_0GB:
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speed = "8 GT/s";
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break;
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case PCI_EXP_LNKCAP_SLS_5_0GB:
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speed = "5 GT/s";
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break;
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case PCI_EXP_LNKCAP_SLS_2_5GB:
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speed = "2.5 GT/s";
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break;
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default:
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speed = "Unknown speed";
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}
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return sprintf(buf, "%s\n", speed);
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}
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static DEVICE_ATTR_RO(max_link_speed);
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static ssize_t max_link_width_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct pci_dev *pci_dev = to_pci_dev(dev);
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u32 linkcap;
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int err;
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err = pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &linkcap);
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if (err)
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return -EINVAL;
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return sprintf(buf, "%u\n", (linkcap & PCI_EXP_LNKCAP_MLW) >> 4);
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}
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static DEVICE_ATTR_RO(max_link_width);
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static ssize_t current_link_speed_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct pci_dev *pci_dev = to_pci_dev(dev);
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u16 linkstat;
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int err;
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const char *speed;
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err = pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &linkstat);
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if (err)
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return -EINVAL;
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switch (linkstat & PCI_EXP_LNKSTA_CLS) {
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case PCI_EXP_LNKSTA_CLS_8_0GB:
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speed = "8 GT/s";
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break;
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case PCI_EXP_LNKSTA_CLS_5_0GB:
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speed = "5 GT/s";
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break;
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case PCI_EXP_LNKSTA_CLS_2_5GB:
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speed = "2.5 GT/s";
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break;
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default:
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speed = "Unknown speed";
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}
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return sprintf(buf, "%s\n", speed);
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}
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static DEVICE_ATTR_RO(current_link_speed);
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static ssize_t current_link_width_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct pci_dev *pci_dev = to_pci_dev(dev);
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u16 linkstat;
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int err;
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err = pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &linkstat);
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if (err)
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return -EINVAL;
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return sprintf(buf, "%u\n",
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(linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT);
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}
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static DEVICE_ATTR_RO(current_link_width);
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static ssize_t secondary_bus_number_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct pci_dev *pci_dev = to_pci_dev(dev);
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u8 sec_bus;
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int err;
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err = pci_read_config_byte(pci_dev, PCI_SECONDARY_BUS, &sec_bus);
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if (err)
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return -EINVAL;
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return sprintf(buf, "%u\n", sec_bus);
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}
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static DEVICE_ATTR_RO(secondary_bus_number);
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static ssize_t subordinate_bus_number_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct pci_dev *pci_dev = to_pci_dev(dev);
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u8 sub_bus;
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int err;
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err = pci_read_config_byte(pci_dev, PCI_SUBORDINATE_BUS, &sub_bus);
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if (err)
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return -EINVAL;
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return sprintf(buf, "%u\n", sub_bus);
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}
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static DEVICE_ATTR_RO(subordinate_bus_number);
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static ssize_t modalias_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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@ -629,12 +752,17 @@ static struct attribute *pci_dev_attrs[] = {
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NULL,
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};
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static const struct attribute_group pci_dev_group = {
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.attrs = pci_dev_attrs,
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static struct attribute *pci_bridge_attrs[] = {
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&dev_attr_subordinate_bus_number.attr,
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&dev_attr_secondary_bus_number.attr,
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NULL,
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};
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const struct attribute_group *pci_dev_groups[] = {
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&pci_dev_group,
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static struct attribute *pcie_dev_attrs[] = {
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&dev_attr_current_link_speed.attr,
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&dev_attr_current_link_width.attr,
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&dev_attr_max_link_width.attr,
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&dev_attr_max_link_speed.attr,
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NULL,
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};
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@ -1557,6 +1685,57 @@ static umode_t pci_dev_hp_attrs_are_visible(struct kobject *kobj,
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return a->mode;
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}
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static umode_t pci_bridge_attrs_are_visible(struct kobject *kobj,
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struct attribute *a, int n)
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{
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struct device *dev = kobj_to_dev(kobj);
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struct pci_dev *pdev = to_pci_dev(dev);
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if (pci_is_bridge(pdev))
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return a->mode;
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return 0;
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}
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static umode_t pcie_dev_attrs_are_visible(struct kobject *kobj,
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struct attribute *a, int n)
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{
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struct device *dev = kobj_to_dev(kobj);
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struct pci_dev *pdev = to_pci_dev(dev);
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if (pci_is_pcie(pdev))
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return a->mode;
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return 0;
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}
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static const struct attribute_group pci_dev_group = {
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.attrs = pci_dev_attrs,
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};
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const struct attribute_group *pci_dev_groups[] = {
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&pci_dev_group,
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NULL,
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};
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static const struct attribute_group pci_bridge_group = {
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.attrs = pci_bridge_attrs,
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};
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const struct attribute_group *pci_bridge_groups[] = {
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&pci_bridge_group,
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NULL,
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};
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static const struct attribute_group pcie_dev_group = {
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.attrs = pcie_dev_attrs,
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};
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const struct attribute_group *pcie_dev_groups[] = {
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&pcie_dev_group,
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NULL,
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};
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static struct attribute_group pci_dev_hp_attr_group = {
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.attrs = pci_dev_hp_attrs,
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.is_visible = pci_dev_hp_attrs_are_visible,
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@ -1592,12 +1771,24 @@ static struct attribute_group pci_dev_attr_group = {
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.is_visible = pci_dev_attrs_are_visible,
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};
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static struct attribute_group pci_bridge_attr_group = {
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.attrs = pci_bridge_attrs,
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.is_visible = pci_bridge_attrs_are_visible,
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};
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static struct attribute_group pcie_dev_attr_group = {
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.attrs = pcie_dev_attrs,
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.is_visible = pcie_dev_attrs_are_visible,
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};
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static const struct attribute_group *pci_dev_attr_groups[] = {
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&pci_dev_attr_group,
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&pci_dev_hp_attr_group,
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#ifdef CONFIG_PCI_IOV
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&sriov_dev_attr_group,
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#endif
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&pci_bridge_attr_group,
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&pcie_dev_attr_group,
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NULL,
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};
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@ -3708,46 +3708,6 @@ void pci_intx(struct pci_dev *pdev, int enable)
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}
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EXPORT_SYMBOL_GPL(pci_intx);
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/**
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* pci_intx_mask_supported - probe for INTx masking support
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* @dev: the PCI device to operate on
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*
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* Check if the device dev support INTx masking via the config space
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* command word.
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*/
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bool pci_intx_mask_supported(struct pci_dev *dev)
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{
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bool mask_supported = false;
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u16 orig, new;
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if (dev->broken_intx_masking)
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return false;
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pci_cfg_access_lock(dev);
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pci_read_config_word(dev, PCI_COMMAND, &orig);
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pci_write_config_word(dev, PCI_COMMAND,
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orig ^ PCI_COMMAND_INTX_DISABLE);
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pci_read_config_word(dev, PCI_COMMAND, &new);
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/*
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* There's no way to protect against hardware bugs or detect them
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* reliably, but as long as we know what the value should be, let's
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* go ahead and check it.
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*/
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if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
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dev_err(&dev->dev, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n",
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orig, new);
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} else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
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mask_supported = true;
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pci_write_config_word(dev, PCI_COMMAND, orig);
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}
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pci_cfg_access_unlock(dev);
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return mask_supported;
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}
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EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
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static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
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{
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struct pci_bus *bus = dev->bus;
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@ -3798,7 +3758,7 @@ done:
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* @dev: the PCI device to operate on
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*
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* Check if the device dev has its INTx line asserted, mask it and
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* return true in that case. False is returned if not interrupt was
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* return true in that case. False is returned if no interrupt was
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* pending.
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*/
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bool pci_check_and_mask_intx(struct pci_dev *dev)
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@ -1329,6 +1329,34 @@ static void pci_msi_setup_pci_dev(struct pci_dev *dev)
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pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
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}
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/**
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* pci_intx_mask_broken - test PCI_COMMAND_INTX_DISABLE writability
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* @dev: PCI device
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*
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* Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
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* at enumeration-time to avoid modifying PCI_COMMAND at run-time.
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*/
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static int pci_intx_mask_broken(struct pci_dev *dev)
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{
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u16 orig, toggle, new;
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pci_read_config_word(dev, PCI_COMMAND, &orig);
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toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
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pci_write_config_word(dev, PCI_COMMAND, toggle);
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pci_read_config_word(dev, PCI_COMMAND, &new);
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pci_write_config_word(dev, PCI_COMMAND, orig);
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/*
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* PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
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* r2.3, so strictly speaking, a device is not *broken* if it's not
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* writable. But we'll live with the misnomer for now.
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*/
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if (new != toggle)
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return 1;
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return 0;
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}
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/**
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* pci_setup_device - fill in class and map information of a device
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* @dev: the device structure to fill
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@ -1399,6 +1427,8 @@ int pci_setup_device(struct pci_dev *dev)
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}
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}
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dev->broken_intx_masking = pci_intx_mask_broken(dev);
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switch (dev->hdr_type) { /* header type */
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case PCI_HEADER_TYPE_NORMAL: /* standard header */
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if (class == PCI_CLASS_BRIDGE_PCI)
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@ -1674,6 +1704,11 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
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/* Initialize Advanced Error Capabilities and Control Register */
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pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
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reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
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/* Don't enable ECRC generation or checking if unsupported */
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if (!(reg32 & PCI_ERR_CAP_ECRC_GENC))
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reg32 &= ~PCI_ERR_CAP_ECRC_GENE;
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if (!(reg32 & PCI_ERR_CAP_ECRC_CHKC))
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reg32 &= ~PCI_ERR_CAP_ECRC_CHKE;
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pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
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/*
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@ -366,7 +366,7 @@ struct pci_dev {
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unsigned int is_thunderbolt:1; /* Thunderbolt controller */
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unsigned int __aer_firmware_first_valid:1;
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unsigned int __aer_firmware_first:1;
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unsigned int broken_intx_masking:1;
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unsigned int broken_intx_masking:1; /* INTx masking can't be used */
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unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
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unsigned int irq_managed:1;
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unsigned int has_secondary_link:1;
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@ -1003,6 +1003,15 @@ int __must_check pci_reenable_device(struct pci_dev *);
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int __must_check pcim_enable_device(struct pci_dev *pdev);
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void pcim_pin_device(struct pci_dev *pdev);
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static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
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{
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/*
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* INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
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* writable and no quirk has marked the feature broken.
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*/
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return !pdev->broken_intx_masking;
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}
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static inline int pci_is_enabled(struct pci_dev *pdev)
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{
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return (atomic_read(&pdev->enable_cnt) > 0);
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@ -1026,7 +1035,6 @@ int __must_check pci_set_mwi(struct pci_dev *dev);
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int pci_try_set_mwi(struct pci_dev *dev);
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void pci_clear_mwi(struct pci_dev *dev);
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void pci_intx(struct pci_dev *dev, int enable);
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bool pci_intx_mask_supported(struct pci_dev *dev);
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bool pci_check_and_mask_intx(struct pci_dev *dev);
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bool pci_check_and_unmask_intx(struct pci_dev *dev);
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int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
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@ -517,6 +517,7 @@
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#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
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#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
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#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
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#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
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#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
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#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
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#define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
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