Sprinkle a few more .set mipsX over xchg to make sure we dont' end up with
64-bit instructions on 32-bit processors, they tend to be unhappy about that kind of food ;-) Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -302,7 +302,9 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
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" .set mips3 \n"
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"1: ll %0, %2 # __cmpxchg_u32 \n"
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" bne %0, %z3, 2f \n"
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" .set mips0 \n"
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" move $1, %z4 \n"
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" .set mips3 \n"
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" sc $1, %1 \n"
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" beqzl $1, 1b \n"
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#ifdef CONFIG_SMP
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@ -320,7 +322,9 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
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" .set mips3 \n"
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"1: ll %0, %2 # __cmpxchg_u32 \n"
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" bne %0, %z3, 2f \n"
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" .set mips0 \n"
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" move $1, %z4 \n"
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" .set mips3 \n"
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" sc $1, %1 \n"
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" beqz $1, 1b \n"
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#ifdef CONFIG_SMP
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