MIPS: ingenic: Drop obsolete code, merge the rest in setup.c
Drop a bootload of 10-years-old dirty code, that is not used anymore, as it has been replaced with clean code over the ages. Merge the very few bits left inside setup.c, so that everything is clean and tidy now. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Paul Cercueil
Thomas Bogendoerfer
parent
8827af9427
commit
f932449c11
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@ -1,27 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_MACH_JZ4740_BASE_H__
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#define __ASM_MACH_JZ4740_BASE_H__
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#define JZ4740_CPM_BASE_ADDR 0x10000000
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#define JZ4740_INTC_BASE_ADDR 0x10001000
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#define JZ4740_WDT_BASE_ADDR 0x10002000
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#define JZ4740_TCU_BASE_ADDR 0x10002010
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#define JZ4740_RTC_BASE_ADDR 0x10003000
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#define JZ4740_GPIO_BASE_ADDR 0x10010000
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#define JZ4740_AIC_BASE_ADDR 0x10020000
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#define JZ4740_MSC_BASE_ADDR 0x10021000
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#define JZ4740_UART0_BASE_ADDR 0x10030000
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#define JZ4740_UART1_BASE_ADDR 0x10031000
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#define JZ4740_I2C_BASE_ADDR 0x10042000
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#define JZ4740_SSI_BASE_ADDR 0x10043000
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#define JZ4740_SADC_BASE_ADDR 0x10070000
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#define JZ4740_EMC_BASE_ADDR 0x13010000
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#define JZ4740_DMAC_BASE_ADDR 0x13020000
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#define JZ4740_UHC_BASE_ADDR 0x13030000
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#define JZ4740_UDC_BASE_ADDR 0x13040000
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#define JZ4740_LCD_BASE_ADDR 0x13050000
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#define JZ4740_SLCD_BASE_ADDR 0x13050000
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#define JZ4740_CIM_BASE_ADDR 0x13060000
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#define JZ4740_IPU_BASE_ADDR 0x13080000
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#endif
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@ -1,23 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
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* JZ7420/JZ4740 DMA definitions
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*/
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#ifndef __ASM_MACH_JZ4740_DMA_H__
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#define __ASM_MACH_JZ4740_DMA_H__
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enum jz4740_dma_request_type {
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JZ4740_DMA_TYPE_AUTO_REQUEST = 8,
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JZ4740_DMA_TYPE_UART_TRANSMIT = 20,
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JZ4740_DMA_TYPE_UART_RECEIVE = 21,
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JZ4740_DMA_TYPE_SPI_TRANSMIT = 22,
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JZ4740_DMA_TYPE_SPI_RECEIVE = 23,
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JZ4740_DMA_TYPE_MMC_TRANSMIT = 26,
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JZ4740_DMA_TYPE_MMC_RECEIVE = 27,
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JZ4740_DMA_TYPE_TCU = 28,
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JZ4740_DMA_TYPE_SADC = 29,
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JZ4740_DMA_TYPE_SLCD = 30,
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};
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#endif /* __ASM_JZ4740_DMA_H__ */
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@ -8,49 +8,6 @@
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#define __ASM_MACH_JZ4740_IRQ_H__
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#define MIPS_CPU_IRQ_BASE 0
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#define JZ4740_IRQ_BASE 8
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#ifdef CONFIG_MACH_JZ4740
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# define NR_INTC_IRQS 32
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#else
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# define NR_INTC_IRQS 64
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#endif
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/* 1st-level interrupts */
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#define JZ4740_IRQ(x) (JZ4740_IRQ_BASE + (x))
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#define JZ4740_IRQ_I2C JZ4740_IRQ(1)
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#define JZ4740_IRQ_UHC JZ4740_IRQ(3)
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#define JZ4740_IRQ_UART1 JZ4740_IRQ(8)
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#define JZ4740_IRQ_UART0 JZ4740_IRQ(9)
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#define JZ4740_IRQ_SADC JZ4740_IRQ(12)
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#define JZ4740_IRQ_MSC JZ4740_IRQ(14)
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#define JZ4740_IRQ_RTC JZ4740_IRQ(15)
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#define JZ4740_IRQ_SSI JZ4740_IRQ(16)
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#define JZ4740_IRQ_CIM JZ4740_IRQ(17)
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#define JZ4740_IRQ_AIC JZ4740_IRQ(18)
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#define JZ4740_IRQ_ETH JZ4740_IRQ(19)
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#define JZ4740_IRQ_DMAC JZ4740_IRQ(20)
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#define JZ4740_IRQ_TCU2 JZ4740_IRQ(21)
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#define JZ4740_IRQ_TCU1 JZ4740_IRQ(22)
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#define JZ4740_IRQ_TCU0 JZ4740_IRQ(23)
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#define JZ4740_IRQ_UDC JZ4740_IRQ(24)
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#define JZ4740_IRQ_GPIO3 JZ4740_IRQ(25)
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#define JZ4740_IRQ_GPIO2 JZ4740_IRQ(26)
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#define JZ4740_IRQ_GPIO1 JZ4740_IRQ(27)
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#define JZ4740_IRQ_GPIO0 JZ4740_IRQ(28)
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#define JZ4740_IRQ_IPU JZ4740_IRQ(29)
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#define JZ4740_IRQ_LCD JZ4740_IRQ(30)
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#define JZ4780_IRQ_TCU2 JZ4740_IRQ(25)
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/* 2nd-level interrupts */
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#define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(NR_INTC_IRQS) + (x))
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#define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))
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#define JZ4740_IRQ_GPIO(x) (JZ4740_IRQ(NR_INTC_IRQS + 16) + (x))
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#define JZ4740_IRQ_ADC_BASE JZ4740_IRQ(NR_INTC_IRQS + 144)
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#define NR_IRQS (JZ4740_IRQ_ADC_BASE + 6)
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#define NR_IRQS 256
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#endif
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@ -1,126 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
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* JZ4740 platform timer support
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*/
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#ifndef __ASM_MACH_JZ4740_TIMER
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#define __ASM_MACH_JZ4740_TIMER
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#define JZ_REG_TIMER_STOP 0x0C
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#define JZ_REG_TIMER_STOP_SET 0x1C
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#define JZ_REG_TIMER_STOP_CLEAR 0x2C
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#define JZ_REG_TIMER_ENABLE 0x00
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#define JZ_REG_TIMER_ENABLE_SET 0x04
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#define JZ_REG_TIMER_ENABLE_CLEAR 0x08
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#define JZ_REG_TIMER_FLAG 0x10
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#define JZ_REG_TIMER_FLAG_SET 0x14
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#define JZ_REG_TIMER_FLAG_CLEAR 0x18
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#define JZ_REG_TIMER_MASK 0x20
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#define JZ_REG_TIMER_MASK_SET 0x24
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#define JZ_REG_TIMER_MASK_CLEAR 0x28
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#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30)
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#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34)
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#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38)
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#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C)
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#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
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#define JZ_TIMER_IRQ_FULL(x) BIT(x)
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#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9)
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#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8)
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#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7)
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#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c
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#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3
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#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3)
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#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3)
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#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3)
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#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3)
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#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3)
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#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3)
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#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET)
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#define JZ_TIMER_CTRL_SRC_EXT BIT(2)
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#define JZ_TIMER_CTRL_SRC_RTC BIT(1)
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#define JZ_TIMER_CTRL_SRC_PCLK BIT(0)
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extern void __iomem *jz4740_timer_base;
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void __init jz4740_timer_init(void);
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void jz4740_timer_enable_watchdog(void);
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void jz4740_timer_disable_watchdog(void);
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static inline void jz4740_timer_stop(unsigned int timer)
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{
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writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
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}
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static inline void jz4740_timer_start(unsigned int timer)
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{
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writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
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}
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static inline bool jz4740_timer_is_enabled(unsigned int timer)
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{
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return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
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}
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static inline void jz4740_timer_enable(unsigned int timer)
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{
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writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
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}
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static inline void jz4740_timer_disable(unsigned int timer)
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{
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writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
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}
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static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
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{
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writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
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}
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static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
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{
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writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
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}
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static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count)
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{
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writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
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}
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static inline uint16_t jz4740_timer_get_count(unsigned int timer)
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{
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return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
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}
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static inline void jz4740_timer_ack_full(unsigned int timer)
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{
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writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
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}
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static inline void jz4740_timer_irq_full_enable(unsigned int timer)
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{
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writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
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writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
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}
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static inline void jz4740_timer_irq_full_disable(unsigned int timer)
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{
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writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
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}
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static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl)
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{
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writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
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}
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static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer)
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{
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return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
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}
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#endif
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@ -4,11 +4,6 @@
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#
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# Object file lists.
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obj-y += prom.o time.o reset.o setup.o timer.o
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obj-y += setup.o
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CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt
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# PM support
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obj-$(CONFIG_PM) += pm.o
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@ -1,34 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
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* JZ4740 SoC power management support
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*/
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#include <linux/init.h>
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#include <linux/pm.h>
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#include <linux/delay.h>
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#include <linux/suspend.h>
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static int jz4740_pm_enter(suspend_state_t state)
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{
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__asm__(".set\tmips3\n\t"
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"wait\n\t"
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".set\tmips0");
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return 0;
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}
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static const struct platform_suspend_ops jz4740_pm_ops = {
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.valid = suspend_valid_only_mem,
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.enter = jz4740_pm_enter,
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};
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static int __init jz4740_pm_init(void)
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{
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suspend_set_ops(&jz4740_pm_ops);
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return 0;
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}
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late_initcall(jz4740_pm_init);
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@ -1,19 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
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* JZ4740 SoC prom code
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*/
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#include <linux/init.h>
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#include <asm/bootinfo.h>
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#include <asm/fw/fw.h>
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void __init prom_init(void)
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{
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fw_init_cmdline();
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}
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void __init prom_free_prom_memory(void)
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{
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}
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@ -1,24 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
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*/
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#include <asm/reboot.h>
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#include "reset.h"
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static void jz4740_halt(void)
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{
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while (1) {
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__asm__(".set push;\n"
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".set mips3;\n"
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"wait;\n"
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".set pop;\n"
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);
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}
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}
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void jz4740_reset_init(void)
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{
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_machine_halt = jz4740_halt;
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}
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __MIPS_JZ4740_RESET_H__
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#define __MIPS_JZ4740_RESET_H__
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extern void jz4740_reset_init(void);
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#endif
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* JZ4740 setup code
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*/
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#include <linux/clk-provider.h>
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#include <linux/clocksource.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/kernel.h>
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#include <linux/libfdt.h>
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#include <linux/of_fdt.h>
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#include <linux/pm.h>
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#include <linux/suspend.h>
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#include <asm/bootinfo.h>
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#include <asm/fw/fw.h>
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#include <asm/prom.h>
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#include "reset.h"
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#include <asm/reboot.h>
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#define JZ4740_EMC_BASE_ADDR 0x13010000
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@ -61,8 +65,6 @@ void __init plat_mem_setup(void)
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int offset;
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void *dtb;
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jz4740_reset_init();
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if (__dtb_start != __dtb_end)
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dtb = __dtb_start;
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else
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@ -105,3 +107,56 @@ void __init arch_init_irq(void)
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{
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irqchip_init();
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}
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void __init plat_time_init(void)
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{
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of_clk_init(NULL);
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timer_probe();
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}
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void __init prom_init(void)
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{
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fw_init_cmdline();
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}
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void __init prom_free_prom_memory(void)
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{
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}
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static void jz4740_wait_instr(void)
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{
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__asm__(".set push;\n"
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".set mips3;\n"
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"wait;\n"
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".set pop;\n"
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);
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}
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static void jz4740_halt(void)
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{
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for (;;)
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jz4740_wait_instr();
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}
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static int __maybe_unused jz4740_pm_enter(suspend_state_t state)
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{
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jz4740_wait_instr();
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return 0;
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}
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static const struct platform_suspend_ops jz4740_pm_ops __maybe_unused = {
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.valid = suspend_valid_only_mem,
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.enter = jz4740_pm_enter,
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};
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static int __init jz4740_pm_init(void)
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{
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if (IS_ENABLED(CONFIG_PM_SLEEP))
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suspend_set_ops(&jz4740_pm_ops);
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_machine_halt = jz4740_halt;
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return 0;
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}
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late_initcall(jz4740_pm_init);
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@ -1,17 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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||||
/*
|
||||
* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
|
||||
* JZ4740 platform time support
|
||||
*/
|
||||
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/of_clk.h>
|
||||
|
||||
#include <asm/mach-jz4740/timer.h>
|
||||
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
of_clk_init(NULL);
|
||||
jz4740_timer_init();
|
||||
timer_probe();
|
||||
}
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
|
||||
* JZ4740 platform timer support
|
||||
*/
|
||||
|
||||
#include <linux/export.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <asm/mach-jz4740/base.h>
|
||||
#include <asm/mach-jz4740/timer.h>
|
||||
|
||||
void __iomem *jz4740_timer_base;
|
||||
EXPORT_SYMBOL_GPL(jz4740_timer_base);
|
||||
|
||||
void jz4740_timer_enable_watchdog(void)
|
||||
{
|
||||
writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(jz4740_timer_enable_watchdog);
|
||||
|
||||
void jz4740_timer_disable_watchdog(void)
|
||||
{
|
||||
writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(jz4740_timer_disable_watchdog);
|
||||
|
||||
void __init jz4740_timer_init(void)
|
||||
{
|
||||
jz4740_timer_base = ioremap(JZ4740_TCU_BASE_ADDR, 0x100);
|
||||
|
||||
if (!jz4740_timer_base)
|
||||
panic("Failed to ioremap timer registers");
|
||||
|
||||
/* Disable all timer clocks except for those used as system timers */
|
||||
writel(0x000100fc, jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
|
||||
|
||||
/* Timer irqs are unmasked by default, mask them */
|
||||
writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
|
||||
}
|
||||
Loading…
Reference in New Issue