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scsi: qla2xxx: Cleanups for NVRAM/Flash read/write path 

This patch does following:

 - Clean up NVRAM code.
 - Optimizes reading of primary/secondary flash image validation.
 - Remove 0xff mask and make correct width in FLT structure.
 - Use endian macros to assign static fields in fwdump header.
 - Correct fdwt checksum calculation.
 - Simplify ql_dump_buffer() interface usage.
 - Add endianizers to 27xx firmware image validator.
 - fixes compiler warnings for big endian architecture.

Signed-off-by: Joe Carnuccio <joe.carnuccio@cavium.com>
Signed-off-by: Himanshu Madhani <hmadhani@marvell.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Joe Carnuccio 2019-03-12 11:08:16 -07:00 committed by Martin K. Petersen
parent 72a92df210
commit f8f97b0c5b
15 changed files with 292 additions and 274 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/scsi/qla2xxx/qla_bsg.c
View File

@ -1962,7 +1962,7 @@ qlafx00_mgmt_cmd(struct bsg_job *bsg_job)
/* Dump the vendor information */
ql_dump_buffer(ql_dbg_user + ql_dbg_verbose , vha, 0x70cf,
(uint8_t *)piocb_rqst, sizeof(struct qla_mt_iocb_rqst_fx00));
piocb_rqst, sizeof(*piocb_rqst));
if (!vha->flags.online) {
ql_log(ql_log_warn, vha, 0x70d0,
@ -2324,8 +2324,8 @@ qla2x00_get_priv_stats(struct bsg_job *bsg_job)
rval = qla24xx_get_isp_stats(base_vha, stats, stats_dma, options);
if (rval == QLA_SUCCESS) {
ql_dump_buffer(ql_dbg_user + ql_dbg_verbose, vha, 0x70e3,
(uint8_t *)stats, sizeof(*stats));
ql_dump_buffer(ql_dbg_user + ql_dbg_verbose, vha, 0x70e5,
stats, sizeof(*stats));
sg_copy_from_buffer(bsg_job->reply_payload.sg_list,
bsg_job->reply_payload.sg_cnt, stats, sizeof(*stats));
}

19
drivers/scsi/qla2xxx/qla_dbg.c
View File

@ -2520,7 +2520,7 @@ qla83xx_fw_dump_failed:
/****************************************************************************/
static inline int
ql_mask_match(uint32_t level)
ql_mask_match(uint level)
{
return (level & ql2xextended_error_logging) == level;
}
@ -2539,7 +2539,7 @@ ql_mask_match(uint32_t level)
* msg: The message to be displayed.
*/
void
ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
ql_dbg(uint level, scsi_qla_host_t *vha, uint id, const char *fmt, ...)
{
va_list va;
struct va_format vaf;
@ -2582,8 +2582,7 @@ ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
* msg: The message to be displayed.
*/
void
ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
const char *fmt, ...)
ql_dbg_pci(uint level, struct pci_dev *pdev, uint id, const char *fmt, ...)
{
va_list va;
struct va_format vaf;
@ -2619,7 +2618,7 @@ ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
* msg: The message to be displayed.
*/
void
ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
ql_log(uint level, scsi_qla_host_t *vha, uint id, const char *fmt, ...)
{
va_list va;
struct va_format vaf;
@ -2677,8 +2676,7 @@ ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
* msg: The message to be displayed.
*/
void
ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
const char *fmt, ...)
ql_log_pci(uint level, struct pci_dev *pdev, uint id, const char *fmt, ...)
{
va_list va;
struct va_format vaf;
@ -2718,7 +2716,7 @@ ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
}
void
ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
ql_dump_regs(uint level, scsi_qla_host_t *vha, uint id)
{
int i;
struct qla_hw_data *ha = vha->hw;
@ -2740,13 +2738,12 @@ ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
ql_dbg(level, vha, id, "Mailbox registers:\n");
for (i = 0; i < 6; i++, mbx_reg++)
ql_dbg(level, vha, id,
"mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg));
"mbox[%d] %#04x\n", i, RD_REG_WORD(mbx_reg));
}
void
ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
uint8_t *buf, uint size)
ql_dump_buffer(uint level, scsi_qla_host_t *vha, uint id, void *buf, uint size)
{
uint cnt;

10
drivers/scsi/qla2xxx/qla_dbg.h
View File

@ -318,20 +318,20 @@ struct qla2xxx_fw_dump {
* as compared to other log levels.
*/
extern int ql_errlev;
extern uint ql_errlev;
void __attribute__((format (printf, 4, 5)))
ql_dbg(uint32_t, scsi_qla_host_t *vha, int32_t, const char *fmt, ...);
ql_dbg(uint, scsi_qla_host_t *vha, uint, const char *fmt, ...);
void __attribute__((format (printf, 4, 5)))
ql_dbg_pci(uint32_t, struct pci_dev *pdev, int32_t, const char *fmt, ...);
ql_dbg_pci(uint, struct pci_dev *pdev, uint, const char *fmt, ...);
void __attribute__((format (printf, 4, 5)))
ql_dbg_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...);
void __attribute__((format (printf, 4, 5)))
ql_log(uint32_t, scsi_qla_host_t *vha, int32_t, const char *fmt, ...);
ql_log(uint, scsi_qla_host_t *vha, uint, const char *fmt, ...);
void __attribute__((format (printf, 4, 5)))
ql_log_pci(uint32_t, struct pci_dev *pdev, int32_t, const char *fmt, ...);
ql_log_pci(uint, struct pci_dev *pdev, uint, const char *fmt, ...);
void __attribute__((format (printf, 4, 5)))
ql_log_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...);

2
drivers/scsi/qla2xxx/qla_def.h
View File

@ -4467,7 +4467,7 @@ typedef struct scsi_qla_host {
struct qla27xx_image_status {
uint8_t image_status_mask;
uint16_t generation_number;
uint16_t generation;
uint8_t reserved[3];
uint8_t ver_minor;
uint8_t ver_major;

4
drivers/scsi/qla2xxx/qla_fw.h
View File

@ -1516,7 +1516,9 @@ struct qla_flt_header {
#define FLT_REG_VPD_SEC_27XX_3 0xDA
struct qla_flt_region {
uint32_t code;
uint16_t code;
uint8_t attribute;
uint8_t reserved;
uint32_t size;
uint32_t start;
uint32_t end;

10
drivers/scsi/qla2xxx/qla_gbl.h
View File

@ -118,6 +118,7 @@ int qla_post_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport);
void qla_do_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport);
int qla2x00_reserve_mgmt_server_loop_id(scsi_qla_host_t *);
void qla_rscn_replay(fc_port_t *fcport);
extern bool qla24xx_risc_firmware_invalid(uint32_t *);
/*
* Global Data in qla_os.c source file.
@ -614,14 +615,9 @@ extern ulong qla27xx_fwdt_calculate_dump_size(struct scsi_qla_host *);
extern int qla27xx_fwdt_template_valid(void *);
extern ulong qla27xx_fwdt_template_size(void *);
extern void qla2x00_dump_regs(scsi_qla_host_t *);
extern void qla2x00_dump_buffer(uint8_t *, uint32_t);
extern void qla2x00_dump_buffer_zipped(uint8_t *, uint32_t);
extern void ql_dump_regs(uint32_t, scsi_qla_host_t *, int32_t);
extern void ql_dump_buffer(uint32_t, scsi_qla_host_t *, int32_t,
uint8_t *, uint32_t);
extern void qla2xxx_dump_post_process(scsi_qla_host_t *, int);
extern void ql_dump_regs(uint, scsi_qla_host_t *, uint);
extern void ql_dump_buffer(uint, scsi_qla_host_t *, uint, void *, uint);
/*
* Global Function Prototypes in qla_gs.c source file.
*/

4
drivers/scsi/qla2xxx/qla_gs.c
View File

@ -152,8 +152,8 @@ qla2x00_chk_ms_status(scsi_qla_host_t *vha, ms_iocb_entry_t *ms_pkt,
vha->d_id.b.area, vha->d_id.b.al_pa,
comp_status, ct_rsp->header.response);
ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha,
0x2078, (uint8_t *)&ct_rsp->header,
sizeof(struct ct_rsp_hdr));
0x2078, ct_rsp,
offsetof(typeof(*ct_rsp), rsp));
rval = QLA_INVALID_COMMAND;
} else
rval = QLA_SUCCESS;

143
drivers/scsi/qla2xxx/qla_init.c
View File

@ -3650,8 +3650,7 @@ qla2x00_update_fw_options(scsi_qla_host_t *vha)
ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
"Serial link options.\n");
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
(uint8_t *)&ha->fw_seriallink_options,
sizeof(ha->fw_seriallink_options));
ha->fw_seriallink_options, sizeof(ha->fw_seriallink_options));
ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
if (ha->fw_seriallink_options[3] & BIT_2) {
@ -4362,7 +4361,7 @@ qla2x00_nvram_config(scsi_qla_host_t *vha)
rval = QLA_SUCCESS;
/* Determine NVRAM starting address. */
ha->nvram_size = sizeof(nvram_t);
ha->nvram_size = sizeof(*nv);
ha->nvram_base = 0;
if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
@ -4376,7 +4375,7 @@ qla2x00_nvram_config(scsi_qla_host_t *vha)
ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
"Contents of NVRAM.\n");
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
(uint8_t *)nv, ha->nvram_size);
nv, ha->nvram_size);
/* Bad NVRAM data, set defaults parameters. */
if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
@ -4948,8 +4947,7 @@ qla2x00_configure_local_loop(scsi_qla_host_t *vha)
ql_dbg(ql_dbg_disc, vha, 0x2011,
"Entries in ID list (%d).\n", entries);
ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
(uint8_t *)ha->gid_list,
entries * sizeof(struct gid_list_info));
ha->gid_list, entries * sizeof(*ha->gid_list));
if (entries == 0) {
spin_lock_irqsave(&vha->work_lock, flags);
@ -6967,7 +6965,7 @@ qla24xx_nvram_config(scsi_qla_host_t *vha)
ha->vpd_base = FA_NVRAM_VPD1_ADDR;
}
ha->nvram_size = sizeof(struct nvram_24xx);
ha->nvram_size = sizeof(*nv);
ha->vpd_size = FA_NVRAM_VPD_SIZE;
/* Get VPD data into cache */
@ -6985,7 +6983,7 @@ qla24xx_nvram_config(scsi_qla_host_t *vha)
ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
"Contents of NVRAM\n");
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
(uint8_t *)nv, ha->nvram_size);
nv, ha->nvram_size);
/* Bad NVRAM data, set defaults parameters. */
if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
@ -6995,6 +6993,7 @@ qla24xx_nvram_config(scsi_qla_host_t *vha)
ql_log(ql_log_warn, vha, 0x006b,
"Inconsistent NVRAM detected: checksum=0x%x id=%c "
"version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
ql_dump_buffer(ql_dbg_init, vha, 0x006b, nv, 32);
ql_log(ql_log_warn, vha, 0x006c,
"Falling back to functioning (yet invalid -- WWPN) "
"defaults.\n");
@ -7206,18 +7205,16 @@ qla24xx_nvram_config(scsi_qla_host_t *vha)
uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha)
{
struct qla27xx_image_status pri_image_status, sec_image_status;
uint8_t valid_pri_image, valid_sec_image;
bool valid_pri_image = true, valid_sec_image = true;
uint32_t *wptr;
uint32_t cnt, chksum, size;
uint chksum, cnt, size = sizeof(pri_image_status) / sizeof(*wptr);
struct qla_hw_data *ha = vha->hw;
uint32_t signature;
valid_pri_image = valid_sec_image = 1;
ha->active_image = 0;
size = sizeof(struct qla27xx_image_status) / sizeof(uint32_t);
if (!ha->flt_region_img_status_pri) {
valid_pri_image = 0;
valid_pri_image = false;
goto check_sec_image;
}
@ -7228,9 +7225,9 @@ uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha)
if (signature != QLA27XX_IMG_STATUS_SIGN &&
signature != QLA28XX_IMG_STATUS_SIGN) {
ql_dbg(ql_dbg_init, vha, 0x018b,
"Primary image signature (0x%x) not valid\n",
pri_image_status.signature);
valid_pri_image = 0;
"Primary image signature (%#x) not valid\n",
le32_to_cpu(pri_image_status.signature));
valid_pri_image = false;
goto check_sec_image;
}
@ -7242,14 +7239,13 @@ uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha)
if (chksum) {
ql_dbg(ql_dbg_init, vha, 0x018c,
"Checksum validation failed for primary image (0x%x)\n",
chksum);
valid_pri_image = 0;
"Primary image checksum failed (%#x)\n", chksum);
valid_pri_image = false;
}
check_sec_image:
if (!ha->flt_region_img_status_sec) {
valid_sec_image = 0;
valid_sec_image = false;
goto check_valid_image;
}
@ -7260,9 +7256,9 @@ check_sec_image:
if (signature != QLA27XX_IMG_STATUS_SIGN &&
signature != QLA28XX_IMG_STATUS_SIGN) {
ql_dbg(ql_dbg_init, vha, 0x018d,
"Secondary image signature(0x%x) not valid\n",
sec_image_status.signature);
valid_sec_image = 0;
"Secondary image signature (%#x) not valid\n",
le32_to_cpu(sec_image_status.signature));
valid_sec_image = false;
goto check_valid_image;
}
@ -7272,19 +7268,20 @@ check_sec_image:
chksum += le32_to_cpu(*wptr);
if (chksum) {
ql_dbg(ql_dbg_init, vha, 0x018e,
"Checksum validation failed for secondary image (0x%x)\n",
chksum);
valid_sec_image = 0;
"Secondary image checksum failed (%#x)\n", chksum);
valid_sec_image = false;
}
check_valid_image:
if (valid_pri_image && (pri_image_status.image_status_mask & 0x1))
if (valid_pri_image && (pri_image_status.image_status_mask & 1))
ha->active_image = QLA27XX_PRIMARY_IMAGE;
if (valid_sec_image && (sec_image_status.image_status_mask & 0x1)) {
if (valid_sec_image && (sec_image_status.image_status_mask & 1)) {
if (!ha->active_image ||
pri_image_status.generation_number <
sec_image_status.generation_number)
le16_to_cpu(pri_image_status.generation) <
le16_to_cpu(sec_image_status.generation)) {
ha->active_image = QLA27XX_SECONDARY_IMAGE;
}
}
ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x018f, "%s image\n",
@ -7296,6 +7293,13 @@ check_valid_image:
return ha->active_image;
}
bool qla24xx_risc_firmware_invalid(uint32_t *dword)
{
return
!(dword[4] | dword[5] | dword[6] | dword[7]) ||
!(~dword[4] | ~dword[5] | ~dword[6] | ~dword[7]);
}
static int
qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
uint32_t faddr)
@ -7312,24 +7316,9 @@ qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
ql_dbg(ql_dbg_init, vha, 0x008b,
"FW: Loading firmware from flash (%x).\n", faddr);
rval = QLA_SUCCESS;
segments = FA_RISC_CODE_SEGMENTS;
dcode = (uint32_t *)req->ring;
*srisc_addr = 0;
if ((IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
faddr = ha->flt_region_fw_sec;
/* Validate firmware image by checking version. */
qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
for (i = 0; i < 4; i++)
dcode[i] = be32_to_cpu(dcode[i]);
if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
(dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
dcode[3] == 0)) {
dcode = (void *)req->ring;
qla24xx_read_flash_data(vha, dcode, faddr, 8);
if (qla24xx_risc_firmware_invalid(dcode)) {
ql_log(ql_log_fatal, vha, 0x008c,
"Unable to verify the integrity of flash firmware "
"image.\n");
@ -7554,7 +7543,7 @@ qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
uint32_t risc_size;
uint32_t i;
struct fw_blob *blob;
const uint32_t *fwcode;
uint32_t *fwcode;
uint32_t fwclen;
struct qla_hw_data *ha = vha->hw;
struct req_que *req = ha->req_q_map[0];
@ -7571,19 +7560,9 @@ qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
return QLA_FUNCTION_FAILED;
}
ql_dbg(ql_dbg_init, vha, 0x0092,
"FW: Loading via request-firmware.\n");
rval = QLA_SUCCESS;
segments = FA_RISC_CODE_SEGMENTS;
dcode = (uint32_t *)req->ring;
*srisc_addr = 0;
fwcode = (uint32_t *)blob->fw->data;
fwclen = 0;
/* Validate firmware image by checking version. */
if (blob->fw->size < 8 * sizeof(uint32_t)) {
fwcode = (void *)blob->fw->data;
dcode = fwcode;
if (qla24xx_risc_firmware_invalid(dcode)) {
ql_log(ql_log_fatal, vha, 0x0093,
"Unable to verify integrity of firmware image (%zd).\n",
blob->fw->size);
@ -7740,28 +7719,43 @@ qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
if (ql2xfwloadbin == 2)
goto try_blob_fw;
/*
* FW Load priority:
/* FW Load priority:
* 1) Firmware residing in flash.
* 2) Firmware via request-firmware interface (.bin file).
* 3) Golden-Firmware residing in flash -- limited operation.
* 3) Golden-Firmware residing in flash -- (limited operation).
*/
if (!IS_QLA27XX(ha) || !IS_QLA28XX(ha))
goto try_primary_fw;
if (qla27xx_find_valid_image(vha) != QLA27XX_SECONDARY_IMAGE)
goto try_primary_fw;
ql_dbg(ql_dbg_init, vha, 0x008b,
"Loading secondary firmware image.\n");
rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw_sec);
if (!rval)
return rval;
try_primary_fw:
ql_dbg(ql_dbg_init, vha, 0x008b,
"Loading primary firmware image.\n");
rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
if (rval == QLA_SUCCESS)
if (!rval)
return rval;
try_blob_fw:
rval = qla24xx_load_risc_blob(vha, srisc_addr);
if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
if (!rval || !ha->flt_region_gold_fw)
return rval;
ql_log(ql_log_info, vha, 0x0099,
"Attempting to fallback to golden firmware.\n");
rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
if (rval != QLA_SUCCESS)
if (rval)
return rval;
ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
ql_log(ql_log_info, vha, 0x009a, "Need firmware flash update.\n");
ha->flags.running_gold_fw = 1;
return rval;
}
@ -7936,7 +7930,7 @@ qla81xx_nvram_config(scsi_qla_host_t *vha)
nv = ha->nvram;
/* Determine NVRAM starting address. */
ha->nvram_size = sizeof(struct nvram_81xx);
ha->nvram_size = sizeof(*nv);
ha->vpd_size = FA_NVRAM_VPD_SIZE;
if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
ha->vpd_size = FA_VPD_SIZE_82XX;
@ -7956,7 +7950,7 @@ qla81xx_nvram_config(scsi_qla_host_t *vha)
ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
"Contents of NVRAM:\n");
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
(uint8_t *)nv, ha->nvram_size);
nv, ha->nvram_size);
/* Bad NVRAM data, set defaults parameters. */
if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
@ -7967,6 +7961,7 @@ qla81xx_nvram_config(scsi_qla_host_t *vha)
"Inconsistent NVRAM detected: checksum=0x%x id=%c "
"version=0x%x.\n", chksum, nv->id[0],
le16_to_cpu(nv->nvram_version));
ql_dump_buffer(ql_dbg_init, vha, 0x0073, nv, 32);
ql_log(ql_log_info, vha, 0x0074,
"Falling back to functioning (yet invalid -- WWPN) "
"defaults.\n");
@ -8189,12 +8184,6 @@ qla81xx_nvram_config(scsi_qla_host_t *vha)
/* N2N: driver will initiate Login instead of FW */
icb->firmware_options_3 |= BIT_8;
if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
icb->firmware_options_3 |= BIT_8;
ql_dbg(ql_log_info, vha, 0x0075,
"Enabling direct connection.\n");
}
if (rval) {
ql_log(ql_log_warn, vha, 0x0076,
"NVRAM configuration failed.\n");

12
drivers/scsi/qla2xxx/qla_isr.c
View File

@ -1375,7 +1375,7 @@ qla2x00_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
le16_to_cpu(mbx->status_flags));
ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5029,
(uint8_t *)mbx, sizeof(*mbx));
mbx, sizeof(*mbx));
goto logio_done;
}
@ -1519,7 +1519,7 @@ qla2x00_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
bsg_reply->reply_payload_rcv_len = 0;
}
ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5035,
(uint8_t *)pkt, sizeof(*pkt));
pkt, sizeof(*pkt));
} else {
res = DID_OK << 16;
bsg_reply->reply_payload_rcv_len =
@ -1659,7 +1659,7 @@ qla24xx_els_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
memcpy(bsg_job->reply + sizeof(struct fc_bsg_reply),
fw_status, sizeof(fw_status));
ql_dump_buffer(ql_dbg_user + ql_dbg_buffer, vha, 0x5056,
(uint8_t *)pkt, sizeof(*pkt));
pkt, sizeof(*pkt));
}
else {
res = DID_OK << 16;
@ -1703,7 +1703,7 @@ qla24xx_logio_entry(scsi_qla_host_t *vha, struct req_que *req,
fcport->d_id.b.area, fcport->d_id.b.al_pa,
logio->entry_status);
ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x504d,
(uint8_t *)logio, sizeof(*logio));
logio, sizeof(*logio));
goto logio_done;
}
@ -1849,8 +1849,8 @@ qla24xx_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req, void *tsk)
}
if (iocb->u.tmf.data != QLA_SUCCESS)
ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5055,
(uint8_t *)sts, sizeof(*sts));
ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, sp->vha, 0x5055,
sts, sizeof(*sts));
sp->done(sp, 0);
}

16
drivers/scsi/qla2xxx/qla_mbx.c
View File

@ -1829,8 +1829,18 @@ qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
if (rval != QLA_SUCCESS) {
/*EMPTY*/
ql_dbg(ql_dbg_mbx, vha, 0x104d,
"Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
"Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x.\n",
rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
if (ha->init_cb) {
ql_dbg(ql_dbg_mbx, vha, 0x104d, "init_cb:\n");
ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha,
0x0104d, ha->init_cb, sizeof(*ha->init_cb));
}
if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
ql_dbg(ql_dbg_mbx, vha, 0x104d, "ex_init_cb:\n");
ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha,
0x0104d, ha->ex_init_cb, sizeof(*ha->ex_init_cb));
}
} else {
if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
if (mcp->mb[2] == 6 || mcp->mb[3] == 2)
@ -4243,7 +4253,7 @@ qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
"Dump of Verify Request.\n");
ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
(uint8_t *)mn, sizeof(*mn));
mn, sizeof(*mn));
rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
if (rval != QLA_SUCCESS) {
@ -4255,7 +4265,7 @@ qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
"Dump of Verify Response.\n");
ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
(uint8_t *)mn, sizeof(*mn));
mn, sizeof(*mn));
status[0] = le16_to_cpu(mn->p.rsp.comp_status);
status[1] = status[0] == CS_VCS_CHIP_FAILURE ?

39
drivers/scsi/qla2xxx/qla_mr.c
View File

@ -1138,8 +1138,8 @@ qlafx00_find_all_targets(scsi_qla_host_t *vha,
ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x2088,
"Listing Target bit map...\n");
ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha,
0x2089, (uint8_t *)ha->gid_list, 32);
ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha, 0x2089,
ha->gid_list, 32);
/* Allocate temporary rmtport for any new rmtports discovered. */
new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
@ -1913,8 +1913,7 @@ qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
phost_info->domainname,
phost_info->hostdriver);
ql_dump_buffer(ql_dbg_init + ql_dbg_disc, vha, 0x014d,
(uint8_t *)phost_info,
sizeof(struct host_system_info));
phost_info, sizeof(*phost_info));
}
}
@ -1968,7 +1967,7 @@ qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
vha->d_id.b.al_pa = pinfo->port_id[2];
qlafx00_update_host_attr(vha, pinfo);
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0141,
(uint8_t *)pinfo, 16);
pinfo, 16);
} else if (fx_type == FXDISC_GET_TGT_NODE_INFO) {
struct qlafx00_tgt_node_info *pinfo =
(struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
@ -1976,12 +1975,12 @@ qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
memcpy(fcport->port_name, pinfo->tgt_node_wwpn, WWN_SIZE);
fcport->port_type = FCT_TARGET;
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0144,
(uint8_t *)pinfo, 16);
pinfo, 16);
} else if (fx_type == FXDISC_GET_TGT_NODE_LIST) {
struct qlafx00_tgt_node_info *pinfo =
(struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0146,
(uint8_t *)pinfo, 16);
pinfo, 16);
memcpy(vha->hw->gid_list, pinfo, QLAFX00_TGT_NODE_LIST_SIZE);
} else if (fx_type == FXDISC_ABORT_IOCTL)
fdisc->u.fxiocb.result =
@ -2248,18 +2247,16 @@ qlafx00_ioctl_iosb_entry(scsi_qla_host_t *vha, struct req_que *req,
fw_sts_ptr = bsg_job->reply + sizeof(struct fc_bsg_reply);
memcpy(fw_sts_ptr, (uint8_t *)&fstatus,
sizeof(struct qla_mt_iocb_rsp_fx00));
memcpy(fw_sts_ptr, &fstatus, sizeof(fstatus));
bsg_job->reply_len = sizeof(struct fc_bsg_reply) +
sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t);
ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
sp->fcport->vha, 0x5080,
(uint8_t *)pkt, sizeof(struct ioctl_iocb_entry_fx00));
sp->vha, 0x5080, pkt, sizeof(*pkt));
ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
sp->fcport->vha, 0x5074,
(uint8_t *)fw_sts_ptr, sizeof(struct qla_mt_iocb_rsp_fx00));
sp->vha, 0x5074,
fw_sts_ptr, sizeof(fstatus));
res = bsg_reply->result = DID_OK << 16;
bsg_reply->reply_payload_rcv_len =
@ -2597,7 +2594,7 @@ qlafx00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
/* Move sense data. */
ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304e,
(uint8_t *)pkt, sizeof(sts_cont_entry_t));
pkt, sizeof(*pkt));
memcpy(sense_ptr, pkt->data, sense_sz);
ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304a,
sense_ptr, sense_sz);
@ -3056,13 +3053,13 @@ qlafx00_build_scsi_iocbs(srb_t *sp, struct cmd_type_7_fx00 *cmd_pkt,
if (avail_dsds == 0 && cont == 1) {
cont = 0;
memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
REQUEST_ENTRY_SIZE);
sizeof(lcont_pkt));
}
}
if (avail_dsds != 0 && cont == 1) {
memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
REQUEST_ENTRY_SIZE);
sizeof(lcont_pkt));
}
}
@ -3172,9 +3169,9 @@ qlafx00_start_scsi(srb_t *sp)
lcmd_pkt.entry_status = (uint8_t) rsp->id;
ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302e,
(uint8_t *)cmd->cmnd, cmd->cmd_len);
cmd->cmnd, cmd->cmd_len);
ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3032,
(uint8_t *)&lcmd_pkt, REQUEST_ENTRY_SIZE);
&lcmd_pkt, sizeof(lcmd_pkt));
memcpy_toio((void __iomem *)cmd_pkt, &lcmd_pkt, REQUEST_ENTRY_SIZE);
wmb();
@ -3454,10 +3451,8 @@ qlafx00_fxdisc_iocb(srb_t *sp, struct fxdisc_entry_fx00 *pfxiocb)
}
ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
sp->vha, 0x3047,
(uint8_t *)&fx_iocb, sizeof(struct fxdisc_entry_fx00));
sp->vha, 0x3047, &fx_iocb, sizeof(fx_iocb));
memcpy_toio((void __iomem *)pfxiocb, &fx_iocb,
sizeof(struct fxdisc_entry_fx00));
memcpy_toio((void __iomem *)pfxiocb, &fx_iocb, sizeof(fx_iocb));
wmb();
}

2
drivers/scsi/qla2xxx/qla_os.c
View File

@ -42,7 +42,7 @@ static struct kmem_cache *ctx_cachep;
/*
* error level for logging
*/
int ql_errlev = ql_log_all;
uint ql_errlev = ql_log_all;
static int ql2xenableclass2;
module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);

41
drivers/scsi/qla2xxx/qla_sup.c
View File

@ -619,7 +619,7 @@ qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
ql_log(ql_log_fatal, vha, 0x0045,
"Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e,
buf, sizeof(struct qla_flt_location));
fltl, sizeof(*fltl));
return QLA_FUNCTION_FAILED;
}
@ -721,12 +721,12 @@ qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
/* Store addresses as DWORD offsets. */
start = le32_to_cpu(region->start) >> 2;
ql_dbg(ql_dbg_init, vha, 0x0049,
"FLT[%02x]: start=0x%x "
"end=0x%x size=0x%x.\n", le32_to_cpu(region->code) & 0xff,
"FLT[%#x]: start=%#x end=%#x size=%#x.\n",
le16_to_cpu(region->code),
start, le32_to_cpu(region->end) >> 2,
le32_to_cpu(region->size));
switch (le32_to_cpu(region->code) & 0xff) {
switch (le16_to_cpu(region->code)) {
case FLT_REG_FCOE_FW:
if (!IS_QLA8031(ha))
break;
@ -941,7 +941,7 @@ qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
" checksum=0x%x id=%c version0x%x.\n", chksum,
fdt->sig[0], le16_to_cpu(fdt->version));
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113,
(uint8_t *)fdt, sizeof(*fdt));
fdt, sizeof(*fdt));
goto no_flash_data;
}
@ -2879,7 +2879,7 @@ qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
"Dumping fw "
"ver from flash:.\n");
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b,
(uint8_t *)dbyte, 8);
dbyte, 8);
if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
dcode[2] == 0xffff && dcode[3] == 0xffff) ||
@ -3128,24 +3128,16 @@ qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
faddr = ha->flt_region_fw_sec;
qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
for (i = 0; i < 4; i++)
dcode[i] = be32_to_cpu(dcode[i]);
if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
(dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
dcode[3] == 0)) {
qla24xx_read_flash_data(vha, dcode, faddr, 8);
if (qla24xx_risc_firmware_invalid(dcode)) {
ql_log(ql_log_warn, vha, 0x005f,
"Unrecognized fw revision at %x.\n",
ha->flt_region_fw * 4);
} else {
ha->fw_revision[0] = dcode[0];
ha->fw_revision[1] = dcode[1];
ha->fw_revision[2] = dcode[2];
ha->fw_revision[3] = dcode[3];
for (i = 0; i < 4; i++)
ha->fw_revision[i] = be32_to_cpu(dcode[4+i]);
ql_dbg(ql_dbg_init, vha, 0x0060,
"Firmware revision %d.%d.%d (%x).\n",
"Firmware revision (flash) %d.%d.%d (%x).\n",
ha->fw_revision[0], ha->fw_revision[1],
ha->fw_revision[2], ha->fw_revision[3]);
}
@ -3158,19 +3150,16 @@ qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version));
dcode = mbuf;
ha->isp_ops->read_optrom(vha, (uint8_t *)dcode,
ha->flt_region_gold_fw << 2, 32);
if (dcode[4] == 0xFFFFFFFF && dcode[5] == 0xFFFFFFFF &&
dcode[6] == 0xFFFFFFFF && dcode[7] == 0xFFFFFFFF) {
qla24xx_read_flash_data(vha, dcode, ha->flt_region_gold_fw, 8);
if (qla24xx_risc_firmware_invalid(dcode)) {
ql_log(ql_log_warn, vha, 0x0056,
"Unrecognized golden fw at 0x%x.\n",
ha->flt_region_gold_fw * 4);
return ret;
}
for (i = 4; i < 8; i++)
ha->gold_fw_version[i-4] = be32_to_cpu(dcode[i]);
for (i = 0; i < 4; i++)
ha->gold_fw_version[i] = be32_to_cpu(dcode[4+i]);
return ret;
}

184
drivers/scsi/qla2xxx/qla_tmpl.c
View File

@ -134,7 +134,7 @@ qla27xx_skip_entry(struct qla27xx_fwdt_entry *ent, void *buf)
static inline struct qla27xx_fwdt_entry *
qla27xx_next_entry(struct qla27xx_fwdt_entry *ent)
{
return (void *)ent + ent->hdr.size;
return (void *)ent + le32_to_cpu(ent->hdr.size);
}
static struct qla27xx_fwdt_entry *
@ -165,11 +165,14 @@ qla27xx_fwdt_entry_t256(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
ulong addr = le32_to_cpu(ent->t256.base_addr);
uint offset = ent->t256.pci_offset;
ulong count = le16_to_cpu(ent->t256.reg_count);
uint width = ent->t256.reg_width;
ql_dbg(ql_dbg_misc, vha, 0xd200,
"%s: rdio t1 [%lx]\n", __func__, *len);
qla27xx_read_window(reg, ent->t256.base_addr, ent->t256.pci_offset,
ent->t256.reg_count, ent->t256.reg_width, buf, len);
qla27xx_read_window(reg, addr, offset, count, width, buf, len);
return qla27xx_next_entry(ent);
}
@ -179,11 +182,14 @@ qla27xx_fwdt_entry_t257(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
ulong addr = le32_to_cpu(ent->t257.base_addr);
uint offset = ent->t257.pci_offset;
ulong data = le32_to_cpu(ent->t257.write_data);
ql_dbg(ql_dbg_misc, vha, 0xd201,
"%s: wrio t1 [%lx]\n", __func__, *len);
qla27xx_write_reg(reg, IOBASE_ADDR, ent->t257.base_addr, buf);
qla27xx_write_reg(reg, ent->t257.pci_offset, ent->t257.write_data, buf);
qla27xx_write_reg(reg, IOBASE(reg), addr, buf);
qla27xx_write_reg(reg, offset, data, buf);
return qla27xx_next_entry(ent);
}
@ -193,12 +199,17 @@ qla27xx_fwdt_entry_t258(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
uint banksel = ent->t258.banksel_offset;
ulong bank = le32_to_cpu(ent->t258.bank);
ulong addr = le32_to_cpu(ent->t258.base_addr);
uint offset = ent->t258.pci_offset;
uint count = le16_to_cpu(ent->t258.reg_count);
uint width = ent->t258.reg_width;
ql_dbg(ql_dbg_misc, vha, 0xd202,
"%s: rdio t2 [%lx]\n", __func__, *len);
qla27xx_write_reg(reg, ent->t258.banksel_offset, ent->t258.bank, buf);
qla27xx_read_window(reg, ent->t258.base_addr, ent->t258.pci_offset,
ent->t258.reg_count, ent->t258.reg_width, buf, len);
qla27xx_write_reg(reg, banksel, bank, buf);
qla27xx_read_window(reg, addr, offset, count, width, buf, len);
return qla27xx_next_entry(ent);
}
@ -208,12 +219,17 @@ qla27xx_fwdt_entry_t259(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
ulong addr = le32_to_cpu(ent->t259.base_addr);
uint banksel = ent->t259.banksel_offset;
ulong bank = le32_to_cpu(ent->t259.bank);
uint offset = ent->t259.pci_offset;
ulong data = le32_to_cpu(ent->t259.write_data);
ql_dbg(ql_dbg_misc, vha, 0xd203,
"%s: wrio t2 [%lx]\n", __func__, *len);
qla27xx_write_reg(reg, IOBASE_ADDR, ent->t259.base_addr, buf);
qla27xx_write_reg(reg, ent->t259.banksel_offset, ent->t259.bank, buf);
qla27xx_write_reg(reg, ent->t259.pci_offset, ent->t259.write_data, buf);
qla27xx_write_reg(reg, IOBASE(reg), addr, buf);
qla27xx_write_reg(reg, banksel, bank, buf);
qla27xx_write_reg(reg, offset, data, buf);
return qla27xx_next_entry(ent);
}
@ -223,11 +239,12 @@ qla27xx_fwdt_entry_t260(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
uint offset = ent->t260.pci_offset;
ql_dbg(ql_dbg_misc, vha, 0xd204,
"%s: rdpci [%lx]\n", __func__, *len);
qla27xx_insert32(ent->t260.pci_offset, buf, len);
qla27xx_read_reg(reg, ent->t260.pci_offset, buf, len);
qla27xx_insert32(offset, buf, len);
qla27xx_read_reg(reg, offset, buf, len);
return qla27xx_next_entry(ent);
}
@ -237,10 +254,12 @@ qla27xx_fwdt_entry_t261(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
uint offset = ent->t261.pci_offset;
ulong data = le32_to_cpu(ent->t261.write_data);
ql_dbg(ql_dbg_misc, vha, 0xd205,
"%s: wrpci [%lx]\n", __func__, *len);
qla27xx_write_reg(reg, ent->t261.pci_offset, ent->t261.write_data, buf);
qla27xx_write_reg(reg, offset, data, buf);
return qla27xx_next_entry(ent);
}
@ -249,51 +268,50 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t262(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
uint area = ent->t262.ram_area;
ulong start = le32_to_cpu(ent->t262.start_addr);
ulong end = le32_to_cpu(ent->t262.end_addr);
ulong dwords;
ulong start;
ulong end;
ql_dbg(ql_dbg_misc, vha, 0xd206,
"%s: rdram(%x) [%lx]\n", __func__, ent->t262.ram_area, *len);
start = ent->t262.start_addr;
end = ent->t262.end_addr;
if (ent->t262.ram_area == T262_RAM_AREA_CRITICAL_RAM) {
if (area == T262_RAM_AREA_CRITICAL_RAM) {
;
} else if (ent->t262.ram_area == T262_RAM_AREA_EXTERNAL_RAM) {
} else if (area == T262_RAM_AREA_EXTERNAL_RAM) {
end = vha->hw->fw_memory_size;
if (buf)
ent->t262.end_addr = end;
} else if (ent->t262.ram_area == T262_RAM_AREA_SHARED_RAM) {
ent->t262.end_addr = cpu_to_le32(end);
} else if (area == T262_RAM_AREA_SHARED_RAM) {
start = vha->hw->fw_shared_ram_start;
end = vha->hw->fw_shared_ram_end;
if (buf) {
ent->t262.start_addr = start;
ent->t262.end_addr = end;
ent->t262.start_addr = cpu_to_le32(start);
ent->t262.end_addr = cpu_to_le32(end);
}
} else if (ent->t262.ram_area == T262_RAM_AREA_DDR_RAM) {
} else if (area == T262_RAM_AREA_DDR_RAM) {
start = vha->hw->fw_ddr_ram_start;
end = vha->hw->fw_ddr_ram_end;
if (buf) {
ent->t262.start_addr = start;
ent->t262.end_addr = end;
ent->t262.start_addr = cpu_to_le32(start);
ent->t262.end_addr = cpu_to_le32(end);
}
} else if (ent->t262.ram_area == T262_RAM_AREA_MISC) {
} else if (area == T262_RAM_AREA_MISC) {
if (buf) {
ent->t262.start_addr = start;
ent->t262.end_addr = end;
ent->t262.start_addr = cpu_to_le32(start);
ent->t262.end_addr = cpu_to_le32(end);
}
} else {
ql_dbg(ql_dbg_misc, vha, 0xd022,
"%s: unknown area %x\n", __func__, ent->t262.ram_area);
"%s: unknown area %x\n", __func__, area);
qla27xx_skip_entry(ent, buf);
goto done;
}
if (end < start || start == 0 || end == 0) {
ql_dbg(ql_dbg_misc, vha, 0xd023,
"%s: unusable range (start=%x end=%x)\n", __func__,
ent->t262.end_addr, ent->t262.start_addr);
"%s: unusable range (start=%lx end=%lx)\n",
__func__, start, end);
qla27xx_skip_entry(ent, buf);
goto done;
}
@ -312,13 +330,14 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t263(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
uint type = ent->t263.queue_type;
uint count = 0;
uint i;
uint length;
ql_dbg(ql_dbg_misc, vha, 0xd207,
"%s: getq(%x) [%lx]\n", __func__, ent->t263.queue_type, *len);
if (ent->t263.queue_type == T263_QUEUE_TYPE_REQ) {
ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd207,
"%s: getq(%x) [%lx]\n", __func__, type, *len);
if (type == T263_QUEUE_TYPE_REQ) {
for (i = 0; i < vha->hw->max_req_queues; i++) {
struct req_que *req = vha->hw->req_q_map[i];
@ -332,7 +351,7 @@ qla27xx_fwdt_entry_t263(struct scsi_qla_host *vha,
count++;
}
}
} else if (ent->t263.queue_type == T263_QUEUE_TYPE_RSP) {
} else if (type == T263_QUEUE_TYPE_RSP) {
for (i = 0; i < vha->hw->max_rsp_queues; i++) {
struct rsp_que *rsp = vha->hw->rsp_q_map[i];
@ -360,7 +379,7 @@ qla27xx_fwdt_entry_t263(struct scsi_qla_host *vha,
}
} else {
ql_dbg(ql_dbg_misc, vha, 0xd026,
"%s: unknown queue %x\n", __func__, ent->t263.queue_type);
"%s: unknown queue %x\n", __func__, type);
qla27xx_skip_entry(ent, buf);
}
@ -433,10 +452,12 @@ qla27xx_fwdt_entry_t267(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
uint offset = ent->t267.pci_offset;
ulong data = le32_to_cpu(ent->t267.data);
ql_dbg(ql_dbg_misc, vha, 0xd20b,
"%s: dis intr [%lx]\n", __func__, *len);
qla27xx_write_reg(reg, ent->t267.pci_offset, ent->t267.data, buf);
qla27xx_write_reg(reg, offset, data, buf);
return qla27xx_next_entry(ent);
}
@ -533,8 +554,8 @@ qla27xx_fwdt_entry_t270(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
ulong dwords = ent->t270.count;
ulong addr = ent->t270.addr;
ulong addr = le32_to_cpu(ent->t270.addr);
ulong dwords = le32_to_cpu(ent->t270.count);
ql_dbg(ql_dbg_misc, vha, 0xd20e,
"%s: rdremreg [%lx]\n", __func__, *len);
@ -554,8 +575,8 @@ qla27xx_fwdt_entry_t271(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
ulong addr = ent->t271.addr;
ulong data = ent->t271.data;
ulong addr = le32_to_cpu(ent->t271.addr);
ulong data = le32_to_cpu(ent->t271.data);
ql_dbg(ql_dbg_misc, vha, 0xd20f,
"%s: wrremreg [%lx]\n", __func__, *len);
@ -570,8 +591,8 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t272(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
ulong dwords = ent->t272.count;
ulong start = ent->t272.addr;
ulong dwords = le32_to_cpu(ent->t272.count);
ulong start = le32_to_cpu(ent->t272.addr);
ql_dbg(ql_dbg_misc, vha, 0xd210,
"%s: rdremram [%lx]\n", __func__, *len);
@ -590,8 +611,8 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t273(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
ulong dwords = ent->t273.count;
ulong addr = ent->t273.addr;
ulong dwords = le32_to_cpu(ent->t273.count);
ulong addr = le32_to_cpu(ent->t273.addr);
uint32_t value;
ql_dbg(ql_dbg_misc, vha, 0xd211,
@ -613,12 +634,13 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t274(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
ulong type = ent->t274.queue_type;
uint count = 0;
uint i;
ql_dbg(ql_dbg_misc, vha, 0xd212,
"%s: getqsh(%x) [%lx]\n", __func__, ent->t274.queue_type, *len);
if (ent->t274.queue_type == T274_QUEUE_TYPE_REQ_SHAD) {
ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd212,
"%s: getqsh(%lx) [%lx]\n", __func__, type, *len);
if (type == T274_QUEUE_TYPE_REQ_SHAD) {
for (i = 0; i < vha->hw->max_req_queues; i++) {
struct req_que *req = vha->hw->req_q_map[i];
@ -630,7 +652,7 @@ qla27xx_fwdt_entry_t274(struct scsi_qla_host *vha,
count++;
}
}
} else if (ent->t274.queue_type == T274_QUEUE_TYPE_RSP_SHAD) {
} else if (type == T274_QUEUE_TYPE_RSP_SHAD) {
for (i = 0; i < vha->hw->max_rsp_queues; i++) {
struct rsp_que *rsp = vha->hw->rsp_q_map[i];
@ -656,7 +678,7 @@ qla27xx_fwdt_entry_t274(struct scsi_qla_host *vha,
}
} else {
ql_dbg(ql_dbg_misc, vha, 0xd02f,
"%s: unknown queue %x\n", __func__, ent->t274.queue_type);
"%s: unknown queue %lx\n", __func__, type);
qla27xx_skip_entry(ent, buf);
}
@ -675,23 +697,26 @@ qla27xx_fwdt_entry_t275(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
ulong offset = offsetof(typeof(*ent), t275.buffer);
ulong length = le32_to_cpu(ent->t275.length);
ulong size = le32_to_cpu(ent->hdr.size);
void *buffer = ent->t275.buffer;
ql_dbg(ql_dbg_misc, vha, 0xd213,
"%s: buffer(%x) [%lx]\n", __func__, ent->t275.length, *len);
if (!ent->t275.length) {
ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd213,
"%s: buffer(%lx) [%lx]\n", __func__, length, *len);
if (!length) {
ql_dbg(ql_dbg_misc, vha, 0xd020,
"%s: buffer zero length\n", __func__);
qla27xx_skip_entry(ent, buf);
goto done;
}
if (offset + ent->t275.length > ent->hdr.size) {
if (offset + length > size) {
ql_dbg(ql_dbg_misc, vha, 0xd030,
"%s: buffer overflow\n", __func__);
qla27xx_skip_entry(ent, buf);
goto done;
}
qla27xx_insertbuf(ent->t275.buffer, ent->t275.length, buf, len);
qla27xx_insertbuf(buffer, length, buf, len);
done:
return qla27xx_next_entry(ent);
}
@ -700,13 +725,15 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t276(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
ulong cond1 = le32_to_cpu(ent->t276.cond1);
ulong cond2 = le32_to_cpu(ent->t276.cond2);
uint type = vha->hw->pdev->device >> 4 & 0xf;
uint func = vha->hw->port_no & 0x3;
ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd214,
"%s: cond [%lx]\n", __func__, *len);
if (type != ent->t276.cond1 || func != ent->t276.cond2) {
if (type != cond1 || func != cond2) {
ent = qla27xx_next_entry(ent);
qla27xx_skip_entry(ent, buf);
}
@ -719,12 +746,15 @@ qla27xx_fwdt_entry_t277(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
ulong cmd_addr = le32_to_cpu(ent->t277.cmd_addr);
ulong wr_cmd_data = le32_to_cpu(ent->t277.wr_cmd_data);
ulong data_addr = le32_to_cpu(ent->t277.data_addr);
ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd215,
"%s: rdpep [%lx]\n", __func__, *len);
qla27xx_insert32(ent->t277.wr_cmd_data, buf, len);
qla27xx_write_reg(reg, ent->t277.cmd_addr, ent->t277.wr_cmd_data, buf);
qla27xx_read_reg(reg, ent->t277.data_addr, buf, len);
qla27xx_insert32(wr_cmd_data, buf, len);
qla27xx_write_reg(reg, cmd_addr, wr_cmd_data, buf);
qla27xx_read_reg(reg, data_addr, buf, len);
return qla27xx_next_entry(ent);
}
@ -734,11 +764,15 @@ qla27xx_fwdt_entry_t278(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
ulong cmd_addr = le32_to_cpu(ent->t278.cmd_addr);
ulong wr_cmd_data = le32_to_cpu(ent->t278.wr_cmd_data);
ulong data_addr = le32_to_cpu(ent->t278.data_addr);
ulong wr_data = le32_to_cpu(ent->t278.wr_data);
ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd216,
"%s: wrpep [%lx]\n", __func__, *len);
qla27xx_write_reg(reg, ent->t278.data_addr, ent->t278.wr_data, buf);
qla27xx_write_reg(reg, ent->t278.cmd_addr, ent->t278.wr_cmd_data, buf);
qla27xx_write_reg(reg, data_addr, wr_data, buf);
qla27xx_write_reg(reg, cmd_addr, wr_cmd_data, buf);
return qla27xx_next_entry(ent);
}
@ -747,8 +781,10 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_other(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
ulong type = le32_to_cpu(ent->hdr.type);
ql_dbg(ql_dbg_misc, vha, 0xd2ff,
"%s: type %x [%lx]\n", __func__, ent->hdr.type, *len);
"%s: other %lx [%lx]\n", __func__, type, *len);
qla27xx_skip_entry(ent, buf);
return qla27xx_next_entry(ent);
@ -803,13 +839,16 @@ static void
qla27xx_walk_template(struct scsi_qla_host *vha,
struct qla27xx_fwdt_template *tmp, void *buf, ulong *len)
{
struct qla27xx_fwdt_entry *ent = (void *)tmp + tmp->entry_offset;
ulong count = tmp->entry_count;
struct qla27xx_fwdt_entry *ent = (void *)tmp +
le32_to_cpu(tmp->entry_offset);
ulong count = le32_to_cpu(tmp->entry_count);
ulong type = 0;
ql_dbg(ql_dbg_misc, vha, 0xd01a,
"%s: entry count %lx\n", __func__, count);
while (count--) {
ent = qla27xx_find_entry(ent->hdr.type)(vha, ent, buf, len);
type = le32_to_cpu(ent->hdr.type);
ent = qla27xx_find_entry(type)(vha, ent, buf, len);
if (!ent)
break;
}
@ -879,13 +918,13 @@ ql27xx_edit_template(struct scsi_qla_host *vha,
static inline uint32_t
qla27xx_template_checksum(void *p, ulong size)
{
uint32_t *buf = p;
__le32 *buf = p;
uint64_t sum = 0;
size /= sizeof(*buf);
while (size--)
sum += *buf++;
for ( ; size--; buf++)
sum += le32_to_cpu(*buf);
sum = (sum & 0xffffffff) + (sum >> 32);
@ -901,7 +940,7 @@ qla27xx_verify_template_checksum(struct qla27xx_fwdt_template *tmp)
static inline int
qla27xx_verify_template_header(struct qla27xx_fwdt_template *tmp)
{
return tmp->template_type == TEMPLATE_TYPE_FWDUMP;
return le32_to_cpu(tmp->template_type) == TEMPLATE_TYPE_FWDUMP;
}
static void
@ -949,7 +988,8 @@ qla27xx_fwdt_template_valid(void *p)
if (!qla27xx_verify_template_header(tmp)) {
ql_log(ql_log_warn, NULL, 0xd01c,
"%s: template type %x\n", __func__, tmp->template_type);
"%s: template type %x\n", __func__,
le32_to_cpu(tmp->template_type));
return false;
}

74
drivers/scsi/qla2xxx/qla_tmpl.h
View File

@ -11,12 +11,12 @@
#define IOBASE_ADDR offsetof(struct device_reg_24xx, iobase_addr)
struct __packed qla27xx_fwdt_template {
uint32_t template_type;
uint32_t entry_offset;
__le32 template_type;
__le32 entry_offset;
uint32_t template_size;
uint32_t reserved_1;
uint32_t entry_count;
__le32 entry_count;
uint32_t template_version;
uint32_t capture_timestamp;
uint32_t template_checksum;
@ -65,8 +65,8 @@ struct __packed qla27xx_fwdt_template {
struct __packed qla27xx_fwdt_entry {
struct __packed {
uint32_t type;
uint32_t size;
__le32 type;
__le32 size;
uint32_t reserved_1;
uint8_t capture_flags;
@ -81,36 +81,36 @@ struct __packed qla27xx_fwdt_entry {
} t255;
struct __packed {
uint32_t base_addr;
__le32 base_addr;
uint8_t reg_width;
uint16_t reg_count;
__le16 reg_count;
uint8_t pci_offset;
} t256;
struct __packed {
uint32_t base_addr;
uint32_t write_data;
__le32 base_addr;
__le32 write_data;
uint8_t pci_offset;
uint8_t reserved[3];
} t257;
struct __packed {
uint32_t base_addr;
__le32 base_addr;
uint8_t reg_width;
uint16_t reg_count;
__le16 reg_count;
uint8_t pci_offset;
uint8_t banksel_offset;
uint8_t reserved[3];
uint32_t bank;
__le32 bank;
} t258;
struct __packed {
uint32_t base_addr;
uint32_t write_data;
__le32 base_addr;
__le32 write_data;
uint8_t reserved[2];
uint8_t pci_offset;
uint8_t banksel_offset;
uint32_t bank;
__le32 bank;
} t259;
struct __packed {
@ -121,14 +121,14 @@ struct __packed qla27xx_fwdt_entry {
struct __packed {
uint8_t pci_offset;
uint8_t reserved[3];
uint32_t write_data;
__le32 write_data;
} t261;
struct __packed {
uint8_t ram_area;
uint8_t reserved[3];
uint32_t start_addr;
uint32_t end_addr;
__le32 start_addr;
__le32 end_addr;
} t262;
struct __packed {
@ -158,7 +158,7 @@ struct __packed qla27xx_fwdt_entry {
struct __packed {
uint8_t pci_offset;
uint8_t reserved[3];
uint32_t data;
__le32 data;
} t267;
struct __packed {
@ -173,23 +173,23 @@ struct __packed qla27xx_fwdt_entry {
} t269;
struct __packed {
uint32_t addr;
uint32_t count;
__le32 addr;
__le32 count;
} t270;
struct __packed {
uint32_t addr;
uint32_t data;
__le32 addr;
__le32 data;
} t271;
struct __packed {
uint32_t addr;
uint32_t count;
__le32 addr;
__le32 count;
} t272;
struct __packed {
uint32_t addr;
uint32_t count;
__le32 addr;
__le32 count;
} t273;
struct __packed {
@ -199,26 +199,26 @@ struct __packed qla27xx_fwdt_entry {
} t274;
struct __packed {
uint32_t length;
__le32 length;
uint8_t buffer[];
} t275;
struct __packed {
uint32_t cond1;
uint32_t cond2;
__le32 cond1;
__le32 cond2;
} t276;
struct __packed {
uint32_t cmd_addr;
uint32_t wr_cmd_data;
uint32_t data_addr;
__le32 cmd_addr;
__le32 wr_cmd_data;
__le32 data_addr;
} t277;
struct __packed {
uint32_t cmd_addr;
uint32_t wr_cmd_data;
uint32_t data_addr;
uint32_t wr_data;
__le32 cmd_addr;
__le32 wr_cmd_data;
__le32 data_addr;
__le32 wr_data;
} t278;
};
};