[PATCH] x86_64: Rename oem_force_hpet_timer to apic_is_clustered_box

Rename oem_force_hpet_timer to apic_is_clustered_box, to give the
function a better fitting name - it really isn't at all about HPET.

Signed-off-by: Vojtech Pavlik <vojtech@suse.cz>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Vojtech Pavlik 2006-06-26 13:58:23 +02:00 committed by Linus Torvalds
parent 05ebb76109
commit f8bf3c65a9
3 changed files with 6 additions and 7 deletions

View File

@ -983,7 +983,7 @@ void smp_apic_timer_interrupt(struct pt_regs *regs)
}
/*
* oem_force_hpet_timer -- force HPET mode for some boxes.
* apic_is_clustered_box() -- Check if we can expect good TSC
*
* Thus far, the major user of this is IBM's Summit2 series:
*
@ -991,7 +991,7 @@ void smp_apic_timer_interrupt(struct pt_regs *regs)
* multi-chassis. Use available data to take a good guess.
* If in doubt, go HPET.
*/
__cpuinit int oem_force_hpet_timer(void)
__cpuinit int apic_is_clustered_box(void)
{
int i, clusters, zeros;
unsigned id;
@ -1022,8 +1022,7 @@ __cpuinit int oem_force_hpet_timer(void)
}
/*
* If clusters > 2, then should be multi-chassis. Return 1 for HPET.
* Else return 0 to use TSC.
* If clusters > 2, then should be multi-chassis.
* May have to revisit this when multi-core + hyperthreaded CPUs come
* out, but AFAIK this will work even for them.
*/

View File

@ -956,10 +956,10 @@ void __init time_init(void)
__cpuinit int unsynchronized_tsc(void)
{
#ifdef CONFIG_SMP
if (oem_force_hpet_timer())
if (apic_is_clustered_box())
return 1;
/* Intel systems are normally all synchronized. Exceptions
are handled in the OEM check above. */
are handled in the check above. */
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
return 0;
#endif

View File

@ -55,7 +55,7 @@
extern int is_hpet_enabled(void);
extern int hpet_rtc_timer_init(void);
extern int oem_force_hpet_timer(void);
extern int apic_is_clustered_box(void);
extern int hpet_use_timer;