PCI: dwc: designware: Add EP mode support
Add endpoint mode support to designware driver. This uses the EP Core layer introduced recently to add endpoint mode support. *Any* function driver can now use this designware device in order to achieve the EP functionality. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Kishon Vijay Abraham I
Bjorn Helgaas
parent
1357053381
commit
f8aed6ec62
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@ -9,6 +9,11 @@ config PCIE_DW_HOST
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW
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config PCIE_DW_EP
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bool
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depends on PCI_ENDPOINT
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select PCIE_DW
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config PCI_DRA7XX
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bool "TI DRA7xx PCIe controller"
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depends on PCI
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@ -1,5 +1,6 @@
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obj-$(CONFIG_PCIE_DW) += pcie-designware.o
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obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
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obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
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obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
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obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
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obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
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@ -0,0 +1,342 @@
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/**
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* Synopsys Designware PCIe Endpoint controller driver
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*
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* Copyright (C) 2017 Texas Instruments
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* Author: Kishon Vijay Abraham I <kishon@ti.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 of
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* the License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/of.h>
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#include "pcie-designware.h"
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#include <linux/pci-epc.h>
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#include <linux/pci-epf.h>
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void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
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{
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struct pci_epc *epc = ep->epc;
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pci_epc_linkup(epc);
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}
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static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
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{
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u32 reg;
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reg = PCI_BASE_ADDRESS_0 + (4 * bar);
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dw_pcie_writel_dbi2(pci, reg, 0x0);
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dw_pcie_writel_dbi(pci, reg, 0x0);
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}
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static int dw_pcie_ep_write_header(struct pci_epc *epc,
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struct pci_epf_header *hdr)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid);
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dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid);
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dw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid);
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dw_pcie_writeb_dbi(pci, PCI_CLASS_PROG, hdr->progif_code);
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dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE,
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hdr->subclass_code | hdr->baseclass_code << 8);
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dw_pcie_writeb_dbi(pci, PCI_CACHE_LINE_SIZE,
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hdr->cache_line_size);
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dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_VENDOR_ID,
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hdr->subsys_vendor_id);
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dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id);
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dw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN,
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hdr->interrupt_pin);
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return 0;
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}
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static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
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dma_addr_t cpu_addr,
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enum dw_pcie_as_type as_type)
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{
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int ret;
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u32 free_win;
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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free_win = find_first_zero_bit(&ep->ib_window_map,
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sizeof(ep->ib_window_map));
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if (free_win >= ep->num_ib_windows) {
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dev_err(pci->dev, "no free inbound window\n");
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return -EINVAL;
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}
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ret = dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr,
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as_type);
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if (ret < 0) {
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dev_err(pci->dev, "Failed to program IB window\n");
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return ret;
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}
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ep->bar_to_atu[bar] = free_win;
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set_bit(free_win, &ep->ib_window_map);
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return 0;
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}
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static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr,
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u64 pci_addr, size_t size)
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{
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u32 free_win;
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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free_win = find_first_zero_bit(&ep->ob_window_map,
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sizeof(ep->ob_window_map));
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if (free_win >= ep->num_ob_windows) {
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dev_err(pci->dev, "no free outbound window\n");
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return -EINVAL;
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}
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dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
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phys_addr, pci_addr, size);
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set_bit(free_win, &ep->ob_window_map);
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ep->outbound_addr[free_win] = phys_addr;
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return 0;
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}
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static void dw_pcie_ep_clear_bar(struct pci_epc *epc, enum pci_barno bar)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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u32 atu_index = ep->bar_to_atu[bar];
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dw_pcie_ep_reset_bar(pci, bar);
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dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
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clear_bit(atu_index, &ep->ib_window_map);
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}
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static int dw_pcie_ep_set_bar(struct pci_epc *epc, enum pci_barno bar,
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dma_addr_t bar_phys, size_t size, int flags)
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{
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int ret;
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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enum dw_pcie_as_type as_type;
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u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
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if (!(flags & PCI_BASE_ADDRESS_SPACE))
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as_type = DW_PCIE_AS_MEM;
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else
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as_type = DW_PCIE_AS_IO;
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ret = dw_pcie_ep_inbound_atu(ep, bar, bar_phys, as_type);
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if (ret)
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return ret;
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dw_pcie_writel_dbi2(pci, reg, size - 1);
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dw_pcie_writel_dbi(pci, reg, flags);
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return 0;
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}
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static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr,
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u32 *atu_index)
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{
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u32 index;
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for (index = 0; index < ep->num_ob_windows; index++) {
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if (ep->outbound_addr[index] != addr)
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continue;
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*atu_index = index;
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return 0;
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}
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return -EINVAL;
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}
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static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, phys_addr_t addr)
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{
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int ret;
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u32 atu_index;
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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ret = dw_pcie_find_index(ep, addr, &atu_index);
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if (ret < 0)
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return;
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dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND);
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clear_bit(atu_index, &ep->ob_window_map);
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}
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static int dw_pcie_ep_map_addr(struct pci_epc *epc, phys_addr_t addr,
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u64 pci_addr, size_t size)
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{
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int ret;
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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ret = dw_pcie_ep_outbound_atu(ep, addr, pci_addr, size);
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if (ret) {
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dev_err(pci->dev, "failed to enable address\n");
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return ret;
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}
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return 0;
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}
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static int dw_pcie_ep_get_msi(struct pci_epc *epc)
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{
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int val;
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u32 lower_addr;
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u32 upper_addr;
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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val = dw_pcie_readb_dbi(pci, MSI_MESSAGE_CONTROL);
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val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
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lower_addr = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_L32);
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upper_addr = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_U32);
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if (!(lower_addr || upper_addr))
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return -EINVAL;
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return val;
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}
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static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int)
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{
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int val;
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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val = (encode_int << MSI_CAP_MMC_SHIFT);
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dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
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return 0;
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}
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static int dw_pcie_ep_raise_irq(struct pci_epc *epc,
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enum pci_epc_irq_type type, u8 interrupt_num)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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if (!ep->ops->raise_irq)
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return -EINVAL;
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return ep->ops->raise_irq(ep, type, interrupt_num);
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}
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static void dw_pcie_ep_stop(struct pci_epc *epc)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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if (!pci->ops->stop_link)
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return;
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pci->ops->stop_link(pci);
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}
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static int dw_pcie_ep_start(struct pci_epc *epc)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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if (!pci->ops->start_link)
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return -EINVAL;
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return pci->ops->start_link(pci);
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}
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static const struct pci_epc_ops epc_ops = {
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.write_header = dw_pcie_ep_write_header,
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.set_bar = dw_pcie_ep_set_bar,
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.clear_bar = dw_pcie_ep_clear_bar,
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.map_addr = dw_pcie_ep_map_addr,
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.unmap_addr = dw_pcie_ep_unmap_addr,
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.set_msi = dw_pcie_ep_set_msi,
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.get_msi = dw_pcie_ep_get_msi,
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.raise_irq = dw_pcie_ep_raise_irq,
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.start = dw_pcie_ep_start,
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.stop = dw_pcie_ep_stop,
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};
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void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
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{
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struct pci_epc *epc = ep->epc;
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pci_epc_mem_exit(epc);
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}
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int dw_pcie_ep_init(struct dw_pcie_ep *ep)
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{
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int ret;
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void *addr;
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enum pci_barno bar;
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struct pci_epc *epc;
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct device *dev = pci->dev;
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struct device_node *np = dev->of_node;
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if (!pci->dbi_base || !pci->dbi_base2) {
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dev_err(dev, "dbi_base/deb_base2 is not populated\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows);
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if (ret < 0) {
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dev_err(dev, "unable to read *num-ib-windows* property\n");
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return ret;
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}
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ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
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if (ret < 0) {
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dev_err(dev, "unable to read *num-ob-windows* property\n");
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return ret;
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}
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addr = devm_kzalloc(dev, sizeof(phys_addr_t) * ep->num_ob_windows,
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GFP_KERNEL);
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if (!addr)
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return -ENOMEM;
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ep->outbound_addr = addr;
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for (bar = BAR_0; bar <= BAR_5; bar++)
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dw_pcie_ep_reset_bar(pci, bar);
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if (ep->ops->ep_init)
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ep->ops->ep_init(ep);
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epc = devm_pci_epc_create(dev, &epc_ops);
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if (IS_ERR(epc)) {
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dev_err(dev, "failed to create epc device\n");
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return PTR_ERR(epc);
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}
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ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
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if (ret < 0)
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epc->max_functions = 1;
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ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size);
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if (ret < 0) {
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dev_err(dev, "Failed to initialize address space\n");
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return ret;
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}
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ep->epc = epc;
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epc_set_drvdata(epc, ep);
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dw_pcie_setup(pci);
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return 0;
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}
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@ -185,6 +185,131 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
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dev_err(pci->dev, "outbound iATU is not being enabled\n");
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}
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static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg)
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{
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u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
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return dw_pcie_readl_dbi(pci, offset + reg);
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}
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static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg,
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u32 val)
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{
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u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
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dw_pcie_writel_dbi(pci, offset + reg, val);
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}
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int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index, int bar,
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u64 cpu_addr, enum dw_pcie_as_type as_type)
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{
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int type;
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u32 retries, val;
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dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
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lower_32_bits(cpu_addr));
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dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
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upper_32_bits(cpu_addr));
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switch (as_type) {
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case DW_PCIE_AS_MEM:
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type = PCIE_ATU_TYPE_MEM;
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break;
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case DW_PCIE_AS_IO:
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type = PCIE_ATU_TYPE_IO;
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break;
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default:
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return -EINVAL;
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}
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dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type);
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dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
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PCIE_ATU_ENABLE |
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PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
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/*
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* Make sure ATU enable takes effect before any subsequent config
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* and I/O accesses.
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*/
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for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
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val = dw_pcie_readl_ib_unroll(pci, index,
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PCIE_ATU_UNR_REGION_CTRL2);
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if (val & PCIE_ATU_ENABLE)
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return 0;
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usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
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}
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dev_err(pci->dev, "inbound iATU is not being enabled\n");
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return -EBUSY;
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}
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int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
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u64 cpu_addr, enum dw_pcie_as_type as_type)
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{
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int type;
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u32 retries, val;
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if (pci->iatu_unroll_enabled)
|
||||
return dw_pcie_prog_inbound_atu_unroll(pci, index, bar,
|
||||
cpu_addr, as_type);
|
||||
|
||||
dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND |
|
||||
index);
|
||||
dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr));
|
||||
dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr));
|
||||
|
||||
switch (as_type) {
|
||||
case DW_PCIE_AS_MEM:
|
||||
type = PCIE_ATU_TYPE_MEM;
|
||||
break;
|
||||
case DW_PCIE_AS_IO:
|
||||
type = PCIE_ATU_TYPE_IO;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
|
||||
dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE
|
||||
| PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
|
||||
|
||||
/*
|
||||
* Make sure ATU enable takes effect before any subsequent config
|
||||
* and I/O accesses.
|
||||
*/
|
||||
for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
|
||||
val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
|
||||
if (val & PCIE_ATU_ENABLE)
|
||||
return 0;
|
||||
|
||||
usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
|
||||
}
|
||||
dev_err(pci->dev, "inbound iATU is not being enabled\n");
|
||||
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
|
||||
enum dw_pcie_region_type type)
|
||||
{
|
||||
int region;
|
||||
|
||||
switch (type) {
|
||||
case DW_PCIE_REGION_INBOUND:
|
||||
region = PCIE_ATU_REGION_INBOUND;
|
||||
break;
|
||||
case DW_PCIE_REGION_OUTBOUND:
|
||||
region = PCIE_ATU_REGION_OUTBOUND;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
|
||||
dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~PCIE_ATU_ENABLE);
|
||||
}
|
||||
|
||||
int dw_pcie_wait_for_link(struct dw_pcie *pci)
|
||||
{
|
||||
int retries;
|
||||
|
|
|
|||
|
|
@ -18,6 +18,9 @@
|
|||
#include <linux/msi.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
#include <linux/pci-epc.h>
|
||||
#include <linux/pci-epf.h>
|
||||
|
||||
/* Parameters for the waiting for link up routine */
|
||||
#define LINK_WAIT_MAX_RETRIES 10
|
||||
#define LINK_WAIT_USLEEP_MIN 90000
|
||||
|
|
@ -89,6 +92,16 @@
|
|||
#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \
|
||||
((0x3 << 20) | ((region) << 9))
|
||||
|
||||
#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \
|
||||
((0x3 << 20) | ((region) << 9) | (0x1 << 8))
|
||||
|
||||
#define MSI_MESSAGE_CONTROL 0x52
|
||||
#define MSI_CAP_MMC_SHIFT 1
|
||||
#define MSI_CAP_MME_SHIFT 4
|
||||
#define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT)
|
||||
#define MSI_MESSAGE_ADDR_L32 0x54
|
||||
#define MSI_MESSAGE_ADDR_U32 0x58
|
||||
|
||||
/*
|
||||
* Maximum number of MSI IRQs can be 256 per controller. But keep
|
||||
* it 32 as of now. Probably we will never need more than 32. If needed,
|
||||
|
|
@ -99,6 +112,13 @@
|
|||
|
||||
struct pcie_port;
|
||||
struct dw_pcie;
|
||||
struct dw_pcie_ep;
|
||||
|
||||
enum dw_pcie_region_type {
|
||||
DW_PCIE_REGION_UNKNOWN,
|
||||
DW_PCIE_REGION_INBOUND,
|
||||
DW_PCIE_REGION_OUTBOUND,
|
||||
};
|
||||
|
||||
struct dw_pcie_host_ops {
|
||||
int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
|
||||
|
|
@ -142,6 +162,31 @@ struct pcie_port {
|
|||
DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
|
||||
};
|
||||
|
||||
enum dw_pcie_as_type {
|
||||
DW_PCIE_AS_UNKNOWN,
|
||||
DW_PCIE_AS_MEM,
|
||||
DW_PCIE_AS_IO,
|
||||
};
|
||||
|
||||
struct dw_pcie_ep_ops {
|
||||
void (*ep_init)(struct dw_pcie_ep *ep);
|
||||
int (*raise_irq)(struct dw_pcie_ep *ep, enum pci_epc_irq_type type,
|
||||
u8 interrupt_num);
|
||||
};
|
||||
|
||||
struct dw_pcie_ep {
|
||||
struct pci_epc *epc;
|
||||
struct dw_pcie_ep_ops *ops;
|
||||
phys_addr_t phys_base;
|
||||
size_t addr_size;
|
||||
u8 bar_to_atu[6];
|
||||
phys_addr_t *outbound_addr;
|
||||
unsigned long ib_window_map;
|
||||
unsigned long ob_window_map;
|
||||
u32 num_ib_windows;
|
||||
u32 num_ob_windows;
|
||||
};
|
||||
|
||||
struct dw_pcie_ops {
|
||||
u64 (*cpu_addr_fixup)(u64 cpu_addr);
|
||||
u32 (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
|
||||
|
|
@ -149,19 +194,26 @@ struct dw_pcie_ops {
|
|||
void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
|
||||
size_t size, u32 val);
|
||||
int (*link_up)(struct dw_pcie *pcie);
|
||||
int (*start_link)(struct dw_pcie *pcie);
|
||||
void (*stop_link)(struct dw_pcie *pcie);
|
||||
};
|
||||
|
||||
struct dw_pcie {
|
||||
struct device *dev;
|
||||
void __iomem *dbi_base;
|
||||
void __iomem *dbi_base2;
|
||||
u32 num_viewport;
|
||||
u8 iatu_unroll_enabled;
|
||||
struct pcie_port pp;
|
||||
struct dw_pcie_ep ep;
|
||||
const struct dw_pcie_ops *ops;
|
||||
};
|
||||
|
||||
#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
|
||||
|
||||
#define to_dw_pcie_from_ep(endpoint) \
|
||||
container_of((endpoint), struct dw_pcie, ep)
|
||||
|
||||
int dw_pcie_read(void __iomem *addr, int size, u32 *val);
|
||||
int dw_pcie_write(void __iomem *addr, int size, u32 val);
|
||||
|
||||
|
|
@ -174,6 +226,10 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci);
|
|||
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
|
||||
int type, u64 cpu_addr, u64 pci_addr,
|
||||
u32 size);
|
||||
int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
|
||||
u64 cpu_addr, enum dw_pcie_as_type as_type);
|
||||
void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
|
||||
enum dw_pcie_region_type type);
|
||||
void dw_pcie_setup(struct dw_pcie *pci);
|
||||
|
||||
static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
|
||||
|
|
@ -186,6 +242,36 @@ static inline u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
|
|||
return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x4);
|
||||
}
|
||||
|
||||
static inline void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val)
|
||||
{
|
||||
__dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x2, val);
|
||||
}
|
||||
|
||||
static inline u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg)
|
||||
{
|
||||
return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x2);
|
||||
}
|
||||
|
||||
static inline void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val)
|
||||
{
|
||||
__dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x1, val);
|
||||
}
|
||||
|
||||
static inline u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg)
|
||||
{
|
||||
return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x1);
|
||||
}
|
||||
|
||||
static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val)
|
||||
{
|
||||
__dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, val);
|
||||
}
|
||||
|
||||
static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg)
|
||||
{
|
||||
return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCIE_DW_HOST
|
||||
irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
|
||||
void dw_pcie_msi_init(struct pcie_port *pp);
|
||||
|
|
@ -210,4 +296,23 @@ static inline int dw_pcie_host_init(struct pcie_port *pp)
|
|||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE_DW_EP
|
||||
void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
|
||||
int dw_pcie_ep_init(struct dw_pcie_ep *ep);
|
||||
void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
|
||||
#else
|
||||
static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
#endif /* _PCIE_DESIGNWARE_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue