From b6862193ca12e4bce6a18f31bb36eaa6d801b377 Mon Sep 17 00:00:00 2001 From: Xu Yilun Date: Mon, 18 Nov 2019 13:20:41 +0800 Subject: [PATCH 01/10] fpga: dfl: support multiple opens on feature device node. Each DFL functional block, e.g. AFU (Accelerated Function Unit) and FME (FPGA Management Engine), could implement more than one function within its region, but current driver only allows one user application to access it by exclusive open on device node. So this is not convenient and flexible for userspace applications, as they have to combine lots of different functions into one single application. This patch removes the limitation here to allow multiple opens to each feature device node for AFU and FME from userspace applications. If user still needs exclusive access to these device node, O_EXCL flag must be issued together with open. Signed-off-by: Wu Hao Signed-off-by: Xu Yilun Signed-off-by: Moritz Fischer --- drivers/fpga/dfl-afu-main.c | 26 +++++++++++++++----------- drivers/fpga/dfl-fme-main.c | 19 ++++++++++++------- drivers/fpga/dfl.c | 15 +++++++++++++-- drivers/fpga/dfl.h | 35 +++++++++++++++++++++++++++-------- 4 files changed, 67 insertions(+), 28 deletions(-) diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c index 65437b6a6842..435bde40f361 100644 --- a/drivers/fpga/dfl-afu-main.c +++ b/drivers/fpga/dfl-afu-main.c @@ -561,14 +561,16 @@ static int afu_open(struct inode *inode, struct file *filp) if (WARN_ON(!pdata)) return -ENODEV; - ret = dfl_feature_dev_use_begin(pdata); - if (ret) - return ret; + mutex_lock(&pdata->lock); + ret = dfl_feature_dev_use_begin(pdata, filp->f_flags & O_EXCL); + if (!ret) { + dev_dbg(&fdev->dev, "Device File Opened %d Times\n", + dfl_feature_dev_use_count(pdata)); + filp->private_data = fdev; + } + mutex_unlock(&pdata->lock); - dev_dbg(&fdev->dev, "Device File Open\n"); - filp->private_data = fdev; - - return 0; + return ret; } static int afu_release(struct inode *inode, struct file *filp) @@ -581,12 +583,14 @@ static int afu_release(struct inode *inode, struct file *filp) pdata = dev_get_platdata(&pdev->dev); mutex_lock(&pdata->lock); - __port_reset(pdev); - afu_dma_region_destroy(pdata); - mutex_unlock(&pdata->lock); - dfl_feature_dev_use_end(pdata); + if (!dfl_feature_dev_use_count(pdata)) { + __port_reset(pdev); + afu_dma_region_destroy(pdata); + } + mutex_unlock(&pdata->lock); + return 0; } diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c index 1d4690c99268..56d720c1af39 100644 --- a/drivers/fpga/dfl-fme-main.c +++ b/drivers/fpga/dfl-fme-main.c @@ -600,14 +600,16 @@ static int fme_open(struct inode *inode, struct file *filp) if (WARN_ON(!pdata)) return -ENODEV; - ret = dfl_feature_dev_use_begin(pdata); - if (ret) - return ret; + mutex_lock(&pdata->lock); + ret = dfl_feature_dev_use_begin(pdata, filp->f_flags & O_EXCL); + if (!ret) { + dev_dbg(&fdev->dev, "Device File Opened %d Times\n", + dfl_feature_dev_use_count(pdata)); + filp->private_data = pdata; + } + mutex_unlock(&pdata->lock); - dev_dbg(&fdev->dev, "Device File Open\n"); - filp->private_data = pdata; - - return 0; + return ret; } static int fme_release(struct inode *inode, struct file *filp) @@ -616,7 +618,10 @@ static int fme_release(struct inode *inode, struct file *filp) struct platform_device *pdev = pdata->dev; dev_dbg(&pdev->dev, "Device File Release\n"); + + mutex_lock(&pdata->lock); dfl_feature_dev_use_end(pdata); + mutex_unlock(&pdata->lock); return 0; } diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index 96a2b8274a33..990994874bf1 100644 --- a/drivers/fpga/dfl.c +++ b/drivers/fpga/dfl.c @@ -1079,6 +1079,7 @@ static int __init dfl_fpga_init(void) */ int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id) { + struct dfl_feature_platform_data *pdata; struct platform_device *port_pdev; int ret = -ENODEV; @@ -1093,7 +1094,11 @@ int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id) goto put_dev_exit; } - ret = dfl_feature_dev_use_begin(dev_get_platdata(&port_pdev->dev)); + pdata = dev_get_platdata(&port_pdev->dev); + + mutex_lock(&pdata->lock); + ret = dfl_feature_dev_use_begin(pdata, true); + mutex_unlock(&pdata->lock); if (ret) goto put_dev_exit; @@ -1120,6 +1125,7 @@ EXPORT_SYMBOL_GPL(dfl_fpga_cdev_release_port); */ int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id) { + struct dfl_feature_platform_data *pdata; struct platform_device *port_pdev; int ret = -ENODEV; @@ -1138,7 +1144,12 @@ int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id) if (ret) goto put_dev_exit; - dfl_feature_dev_use_end(dev_get_platdata(&port_pdev->dev)); + pdata = dev_get_platdata(&port_pdev->dev); + + mutex_lock(&pdata->lock); + dfl_feature_dev_use_end(pdata); + mutex_unlock(&pdata->lock); + cdev->released_port_num--; put_dev_exit: put_device(&port_pdev->dev); diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index 9f0e656de720..4a9a33cd9979 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -205,8 +205,6 @@ struct dfl_feature { const struct dfl_feature_ops *ops; }; -#define DEV_STATUS_IN_USE 0 - #define FEATURE_DEV_ID_UNUSED (-1) /** @@ -219,8 +217,9 @@ struct dfl_feature { * @dfl_cdev: ptr to container device. * @id: id used for this feature device. * @disable_count: count for port disable. + * @excl_open: set on feature device exclusive open. + * @open_count: count for feature device open. * @num: number for sub features. - * @dev_status: dev status (e.g. DEV_STATUS_IN_USE). * @private: ptr to feature dev private data. * @features: sub features of this feature dev. */ @@ -232,26 +231,46 @@ struct dfl_feature_platform_data { struct dfl_fpga_cdev *dfl_cdev; int id; unsigned int disable_count; - unsigned long dev_status; + bool excl_open; + int open_count; void *private; int num; struct dfl_feature features[0]; }; static inline -int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata) +int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata, + bool excl) { - /* Test and set IN_USE flags to ensure file is exclusively used */ - if (test_and_set_bit_lock(DEV_STATUS_IN_USE, &pdata->dev_status)) + if (pdata->excl_open) return -EBUSY; + if (excl) { + if (pdata->open_count) + return -EBUSY; + + pdata->excl_open = true; + } + pdata->open_count++; + return 0; } static inline void dfl_feature_dev_use_end(struct dfl_feature_platform_data *pdata) { - clear_bit_unlock(DEV_STATUS_IN_USE, &pdata->dev_status); + pdata->excl_open = false; + + if (WARN_ON(pdata->open_count <= 0)) + return; + + pdata->open_count--; +} + +static inline +int dfl_feature_dev_use_count(struct dfl_feature_platform_data *pdata) +{ + return pdata->open_count; } static inline From 1493674ba3c0f0d48f5f1bdd8a32cbc3bb7be619 Mon Sep 17 00:00:00 2001 From: Sergiu Cuciurean Date: Thu, 27 Feb 2020 14:09:32 +0200 Subject: [PATCH 02/10] fpga: ice40-spi: Use new structure for SPI transfer delays In a recent change to the SPI subsystem [1], a new `delay` struct was added to replace the `delay_usecs`. This change replaces the current `delay_usecs` with `delay` for this driver. The `spi_transfer_delay_exec()` function [in the SPI framework] makes sure that both `delay_usecs` & `delay` are used (in this order to preserve backwards compatibility). [1] commit bebcfd272df6 ("spi: introduce `delay` field for `spi_transfer` + spi_transfer_delay_exec()") Signed-off-by: Sergiu Cuciurean Signed-off-by: Moritz Fischer --- drivers/fpga/ice40-spi.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/fpga/ice40-spi.c b/drivers/fpga/ice40-spi.c index 56e112e14a10..8d689fea0dab 100644 --- a/drivers/fpga/ice40-spi.c +++ b/drivers/fpga/ice40-spi.c @@ -46,10 +46,16 @@ static int ice40_fpga_ops_write_init(struct fpga_manager *mgr, struct spi_message message; struct spi_transfer assert_cs_then_reset_delay = { .cs_change = 1, - .delay_usecs = ICE40_SPI_RESET_DELAY + .delay = { + .value = ICE40_SPI_RESET_DELAY, + .unit = SPI_DELAY_UNIT_USECS + } }; struct spi_transfer housekeeping_delay_then_release_cs = { - .delay_usecs = ICE40_SPI_HOUSEKEEPING_DELAY + .delay = { + .value = ICE40_SPI_HOUSEKEEPING_DELAY, + .unit = SPI_DELAY_UNIT_USECS + } }; int ret; From a1d1f5d490a475db9fbf7e9d164009f9c26345b2 Mon Sep 17 00:00:00 2001 From: Sergiu Cuciurean Date: Thu, 27 Feb 2020 16:24:14 +0200 Subject: [PATCH 03/10] fpga: machxo2-spi: Use new structure for SPI transfer delays In a recent change to the SPI subsystem [1], a new `delay` struct was added to replace the `delay_usecs`. This change replaces the current `delay_usecs` with `delay` for this driver. The `spi_transfer_delay_exec()` function [in the SPI framework] makes sure that both `delay_usecs` & `delay` are used (in this order to preserve backwards compatibility). [1] commit bebcfd272df6 ("spi: introduce `delay` field for `spi_transfer` + spi_transfer_delay_exec()") Signed-off-by: Sergiu Cuciurean Signed-off-by: Moritz Fischer --- drivers/fpga/machxo2-spi.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/fpga/machxo2-spi.c b/drivers/fpga/machxo2-spi.c index 4d8a87641587..b316369156fe 100644 --- a/drivers/fpga/machxo2-spi.c +++ b/drivers/fpga/machxo2-spi.c @@ -157,7 +157,8 @@ static int machxo2_cleanup(struct fpga_manager *mgr) spi_message_init(&msg); tx[1].tx_buf = &refresh; tx[1].len = sizeof(refresh); - tx[1].delay_usecs = MACHXO2_REFRESH_USEC; + tx[1].delay.value = MACHXO2_REFRESH_USEC; + tx[1].delay.unit = SPI_DELAY_UNIT_USECS; spi_message_add_tail(&tx[1], &msg); ret = spi_sync(spi, &msg); if (ret) @@ -208,7 +209,8 @@ static int machxo2_write_init(struct fpga_manager *mgr, spi_message_init(&msg); tx[0].tx_buf = &enable; tx[0].len = sizeof(enable); - tx[0].delay_usecs = MACHXO2_LOW_DELAY_USEC; + tx[0].delay.value = MACHXO2_LOW_DELAY_USEC; + tx[0].delay.unit = SPI_DELAY_UNIT_USECS; spi_message_add_tail(&tx[0], &msg); tx[1].tx_buf = &erase; @@ -269,7 +271,8 @@ static int machxo2_write(struct fpga_manager *mgr, const char *buf, spi_message_init(&msg); tx.tx_buf = payload; tx.len = MACHXO2_BUF_SIZE; - tx.delay_usecs = MACHXO2_HIGH_DELAY_USEC; + tx.delay.value = MACHXO2_HIGH_DELAY_USEC; + tx.delay.unit = SPI_DELAY_UNIT_USECS; spi_message_add_tail(&tx, &msg); ret = spi_sync(spi, &msg); if (ret) { @@ -317,7 +320,8 @@ static int machxo2_write_complete(struct fpga_manager *mgr, spi_message_init(&msg); tx[1].tx_buf = &refresh; tx[1].len = sizeof(refresh); - tx[1].delay_usecs = MACHXO2_REFRESH_USEC; + tx[1].delay.value = MACHXO2_REFRESH_USEC; + tx[1].delay.unit = SPI_DELAY_UNIT_USECS; spi_message_add_tail(&tx[1], &msg); ret = spi_sync(spi, &msg); if (ret) From 2e00dd1bd6567148c331469c60ded9715ac749c7 Mon Sep 17 00:00:00 2001 From: Richard Gong Date: Fri, 14 Feb 2020 10:00:46 -0600 Subject: [PATCH 04/10] dt-bindings: fpga: add compatible value to Stratix10 SoC FPGA manager binding Add a compatible property value to Stratix10 SoC FPGA manager binding file Signed-off-by: Richard Gong Acked-by: Rob Herring Signed-off-by: Moritz Fischer --- .../devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt index 6e03f79287fb..0f874137ca46 100644 --- a/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt +++ b/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt @@ -4,7 +4,8 @@ Required properties: The fpga_mgr node has the following mandatory property, must be located under firmware/svc node. -- compatible : should contain "intel,stratix10-soc-fpga-mgr" +- compatible : should contain "intel,stratix10-soc-fpga-mgr" or + "intel,agilex-soc-fpga-mgr" Example: From 8d6b6bbe6ddec1a37bbdebf5b7a1ad989b510b7f Mon Sep 17 00:00:00 2001 From: Richard Gong Date: Fri, 14 Feb 2020 10:00:47 -0600 Subject: [PATCH 05/10] arm64: dts: agilex: correct FPGA manager driver's compatible value Correct the compatible property value for FPGA manager driver on Intel Agilex SoC platform. Signed-off-by: Richard Gong Signed-off-by: Moritz Fischer --- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index d8c44d3ca15a..ef10d604e183 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -544,7 +544,7 @@ memory-region = <&service_reserved>; fpga_mgr: fpga-mgr { - compatible = "intel,stratix10-soc-fpga-mgr"; + compatible = "intel,agilex-soc-fpga-mgr"; }; }; }; From d299253cf5b4e0f21ff1ce1d2f02e5ea634ebcb9 Mon Sep 17 00:00:00 2001 From: Richard Gong Date: Fri, 14 Feb 2020 10:00:48 -0600 Subject: [PATCH 06/10] fpga: stratix10-soc: add compatible property value for intel agilex Add compatible property value so we can reuse FPGA manager driver on Intel Agilex SoC platform. Signed-off-by: Richard Gong Signed-off-by: Moritz Fischer --- drivers/fpga/stratix10-soc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/stratix10-soc.c index 215d33789c74..bac93d009170 100644 --- a/drivers/fpga/stratix10-soc.c +++ b/drivers/fpga/stratix10-soc.c @@ -482,7 +482,8 @@ static int s10_remove(struct platform_device *pdev) } static const struct of_device_id s10_of_match[] = { - { .compatible = "intel,stratix10-soc-fpga-mgr", }, + {.compatible = "intel,stratix10-soc-fpga-mgr"}, + {.compatible = "intel,agilex-soc-fpga-mgr"}, {}, }; From fba965a79b925b35bee69472c7caa5ff8d6a8672 Mon Sep 17 00:00:00 2001 From: Richard Gong Date: Fri, 14 Feb 2020 10:00:49 -0600 Subject: [PATCH 07/10] dt-bindings, firmware: add compatible value Intel Stratix10 service layer binding A a compatible property value to Intel Stratix10 service layer binding Signed-off-by: Richard Gong Acked-by: Rob Herring Signed-off-by: Moritz Fischer --- .../devicetree/bindings/firmware/intel,stratix10-svc.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt index 1fa66065acc6..6eff1afd8daf 100644 --- a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt +++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt @@ -23,7 +23,7 @@ Required properties: The svc node has the following mandatory properties, must be located under the firmware node. -- compatible: "intel,stratix10-svc" +- compatible: "intel,stratix10-svc" or "intel,agilex-svc" - method: smc or hvc smc - Secure Monitor Call hvc - Hypervisor Call From fd0d094531db812750bba0367a8822d10a43f444 Mon Sep 17 00:00:00 2001 From: Richard Gong Date: Fri, 14 Feb 2020 10:00:50 -0600 Subject: [PATCH 08/10] arm64: dts: agilex: correct service layer driver's compatible value Correct the compatible property value for Intel Service Layer driver on Intel Agilex SoC platform. Signed-off-by: Richard Gong Signed-off-by: Moritz Fischer --- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index ef10d604e183..f52de8f7806a 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -539,7 +539,7 @@ firmware { svc { - compatible = "intel,stratix10-svc"; + compatible = "intel,agilex-svc"; method = "smc"; memory-region = <&service_reserved>; From 5a53881580f90a5e4404954af16a5646ee9d7842 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Thu, 19 Mar 2020 16:21:53 -0500 Subject: [PATCH 09/10] fpga: dfl.h: Replace zero-length array with flexible-array member The current codebase makes use of the zero-length array language extension to the C90 standard, but the preferred mechanism to declare variable-length types such as these ones is a flexible array member[1][2], introduced in C99: struct foo { int stuff; struct boo array[]; }; By making use of the mechanism above, we will get a compiler warning in case the flexible array does not occur last in the structure, which will help us prevent some kind of undefined behavior bugs from being inadvertently introduced[3] to the codebase from now on. Also, notice that, dynamic memory allocations won't be affected by this change: "Flexible array members have incomplete type, and so the sizeof operator may not be applied. As a quirk of the original implementation of zero-length arrays, sizeof evaluates to zero."[1] This issue was found with the help of Coccinelle. [1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html [2] https://github.com/KSPP/linux/issues/21 [3] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour") Signed-off-by: Gustavo A. R. Silva Signed-off-by: Moritz Fischer --- drivers/fpga/dfl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index 4a9a33cd9979..74784d3cfe7c 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -235,7 +235,7 @@ struct dfl_feature_platform_data { int open_count; void *private; int num; - struct dfl_feature features[0]; + struct dfl_feature features[]; }; static inline From a2b9d4eadb7727772698d06e4cbeb1a1e2538675 Mon Sep 17 00:00:00 2001 From: Dominic Chen Date: Mon, 9 Mar 2020 14:53:23 -0400 Subject: [PATCH 10/10] fpga: dfl: afu: support debug access to memory-mapped afu regions Allow debug access to memory-mapped regions using e.g. gdb. Signed-off-by: Dominic Chen Acked-by: Wu Hao Signed-off-by: Moritz Fischer --- drivers/fpga/dfl-afu-main.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c index 435bde40f361..b0c31789a909 100644 --- a/drivers/fpga/dfl-afu-main.c +++ b/drivers/fpga/dfl-afu-main.c @@ -750,6 +750,12 @@ static long afu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) return -EINVAL; } +static const struct vm_operations_struct afu_vma_ops = { +#ifdef CONFIG_HAVE_IOREMAP_PROT + .access = generic_access_phys, +#endif +}; + static int afu_mmap(struct file *filp, struct vm_area_struct *vma) { struct platform_device *pdev = filp->private_data; @@ -779,6 +785,9 @@ static int afu_mmap(struct file *filp, struct vm_area_struct *vma) !(region.flags & DFL_PORT_REGION_WRITE)) return -EPERM; + /* Support debug access to the mapping */ + vma->vm_ops = &afu_vma_ops; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); return remap_pfn_range(vma, vma->vm_start,