spi: mediatek: add tick_delay support
This patch support tick_delay setting, some users need use high-speed spi speed, which can use tick_delay to tuning spi clk timing. Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com> Link: https://lore.kernel.org/r/20210713114048.29509-1-mason.zhang@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -42,8 +42,9 @@
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#define SPI_CFG1_CS_IDLE_OFFSET 0
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#define SPI_CFG1_PACKET_LOOP_OFFSET 8
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#define SPI_CFG1_PACKET_LENGTH_OFFSET 16
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#define SPI_CFG1_GET_TICK_DLY_OFFSET 30
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#define SPI_CFG1_GET_TICK_DLY_OFFSET 29
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#define SPI_CFG1_GET_TICK_DLY_MASK 0xe0000000
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#define SPI_CFG1_CS_IDLE_MASK 0xff
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#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
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#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
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@ -152,6 +153,7 @@ static const struct mtk_spi_compatible mt6893_compat = {
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*/
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static const struct mtk_chip_config mtk_default_chip_info = {
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.sample_sel = 0,
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.tick_delay = 0,
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};
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static const struct of_device_id mtk_spi_of_match[] = {
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@ -275,6 +277,13 @@ static int mtk_spi_prepare_message(struct spi_master *master,
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writel(mdata->pad_sel[spi->chip_select],
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mdata->base + SPI_PAD_SEL_REG);
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/* tick delay */
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reg_val = readl(mdata->base + SPI_CFG1_REG);
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reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
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reg_val |= ((chip_config->tick_delay & 0x7)
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<< SPI_CFG1_GET_TICK_DLY_OFFSET);
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writel(reg_val, mdata->base + SPI_CFG1_REG);
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return 0;
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}
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@ -12,5 +12,6 @@
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/* Board specific platform_data */
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struct mtk_chip_config {
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u32 sample_sel;
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u32 tick_delay;
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};
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#endif
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