iwlagn: enable shadow register
For 6000 series devices and up, enable automatic update MAC's register for better power usage in PSP mode Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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6fe8efb221
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f81c1f4838
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@ -487,6 +487,7 @@ static struct iwl_base_params iwl6000_base_params = {
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.ucode_tracing = true,
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.sensitivity_calib_by_driver = true,
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.chain_noise_calib_by_driver = true,
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.shadow_reg_enable = true,
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};
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static struct iwl_base_params iwl6050_base_params = {
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@ -510,6 +511,7 @@ static struct iwl_base_params iwl6050_base_params = {
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.ucode_tracing = true,
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.sensitivity_calib_by_driver = true,
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.chain_noise_calib_by_driver = true,
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.shadow_reg_enable = true,
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};
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static struct iwl_base_params iwl6000_coex_base_params = {
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.eeprom_size = OTP_LOW_IMAGE_SIZE,
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@ -532,6 +534,7 @@ static struct iwl_base_params iwl6000_coex_base_params = {
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.ucode_tracing = true,
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.sensitivity_calib_by_driver = true,
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.chain_noise_calib_by_driver = true,
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.shadow_reg_enable = true,
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};
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static struct iwl_ht_params iwl6000_ht_params = {
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@ -753,6 +753,12 @@ int iwlagn_hw_nic_init(struct iwl_priv *priv)
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} else
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iwlagn_txq_ctx_reset(priv);
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if (priv->cfg->base_params->shadow_reg_enable) {
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/* enable shadow regs in HW */
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iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
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0x800FFFFF);
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}
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set_bit(STATUS_INIT, &priv->status);
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return 0;
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@ -290,6 +290,7 @@ struct iwl_mod_params {
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* sensitivity calibration operation
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* @chain_noise_calib_by_driver: driver has the capability to perform
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* chain noise calibration operation
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* @shadow_reg_enable: HW shadhow register bit
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*/
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struct iwl_base_params {
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int eeprom_size;
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@ -320,6 +321,7 @@ struct iwl_base_params {
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const bool ucode_tracing;
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const bool sensitivity_calib_by_driver;
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const bool chain_noise_calib_by_driver;
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const bool shadow_reg_enable;
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};
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/*
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* @advanced_bt_coexist: support advanced bt coexist
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@ -132,6 +132,8 @@
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#define CSR_LED_REG (CSR_BASE+0x094)
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#define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0)
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#define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE+0x0A8) /* 6000 and up */
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/* GIO Chicken Bits (PCI Express bus link power management) */
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#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
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@ -134,28 +134,37 @@ void iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q
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if (q->need_update == 0)
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goto exit_unlock;
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/* If power-saving is in use, make sure device is awake */
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if (test_bit(STATUS_POWER_PMI, &priv->status)) {
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reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
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if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
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IWL_DEBUG_INFO(priv, "Rx queue requesting wakeup, GP1 = 0x%x\n",
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reg);
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iwl_set_bit(priv, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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goto exit_unlock;
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}
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q->write_actual = (q->write & ~0x7);
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iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write_actual);
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/* Else device is assumed to be awake */
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} else {
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if (priv->cfg->base_params->shadow_reg_enable) {
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/* shadow register enabled */
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/* Device expects a multiple of 8 */
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q->write_actual = (q->write & ~0x7);
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iwl_write32(priv, rx_wrt_ptr_reg, q->write_actual);
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}
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} else {
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/* If power-saving is in use, make sure device is awake */
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if (test_bit(STATUS_POWER_PMI, &priv->status)) {
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reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
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if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
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IWL_DEBUG_INFO(priv,
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"Rx queue requesting wakeup,"
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" GP1 = 0x%x\n", reg);
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iwl_set_bit(priv, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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goto exit_unlock;
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}
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q->write_actual = (q->write & ~0x7);
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iwl_write_direct32(priv, rx_wrt_ptr_reg,
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q->write_actual);
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/* Else device is assumed to be awake */
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} else {
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/* Device expects a multiple of 8 */
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q->write_actual = (q->write & ~0x7);
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iwl_write_direct32(priv, rx_wrt_ptr_reg,
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q->write_actual);
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}
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}
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q->need_update = 0;
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exit_unlock:
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@ -49,30 +49,39 @@ void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
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if (txq->need_update == 0)
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return;
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/* if we're trying to save power */
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if (test_bit(STATUS_POWER_PMI, &priv->status)) {
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/* wake up nic if it's powered down ...
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* uCode will wake up, and interrupt us again, so next
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* time we'll skip this part. */
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reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
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if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
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IWL_DEBUG_INFO(priv, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
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txq_id, reg);
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iwl_set_bit(priv, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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return;
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}
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iwl_write_direct32(priv, HBUS_TARG_WRPTR,
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txq->q.write_ptr | (txq_id << 8));
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/* else not in power-save mode, uCode will never sleep when we're
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* trying to tx (during RFKILL, we're not trying to tx). */
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} else
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if (priv->cfg->base_params->shadow_reg_enable) {
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/* shadow register enabled */
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iwl_write32(priv, HBUS_TARG_WRPTR,
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txq->q.write_ptr | (txq_id << 8));
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} else {
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/* if we're trying to save power */
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if (test_bit(STATUS_POWER_PMI, &priv->status)) {
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/* wake up nic if it's powered down ...
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* uCode will wake up, and interrupt us again, so next
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* time we'll skip this part. */
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reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
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if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
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IWL_DEBUG_INFO(priv,
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"Tx queue %d requesting wakeup,"
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" GP1 = 0x%x\n", txq_id, reg);
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iwl_set_bit(priv, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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return;
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}
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iwl_write_direct32(priv, HBUS_TARG_WRPTR,
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txq->q.write_ptr | (txq_id << 8));
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/*
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* else not in power-save mode,
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* uCode will never sleep when we're
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* trying to tx (during RFKILL, we're not trying to tx).
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*/
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} else
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iwl_write32(priv, HBUS_TARG_WRPTR,
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txq->q.write_ptr | (txq_id << 8));
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}
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txq->need_update = 0;
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}
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EXPORT_SYMBOL(iwl_txq_update_write_ptr);
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