[ARM] 4192/1: AT91: Support for AT91SAM9XE processors.
Add support for the Atmel AT91SAM9XE range of processors. These are basically AT91SAM9260's with different amounts of internal SRAM and Flash. We make use of the existing AT91SAM9260 support, but just perform run-time detection of the size of the internal SRAM. Original patch from Nicolas Ferre. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Andrew Victor
Russell King
parent
69b2e99cf5
commit
f7eee89b2a
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@ -9,7 +9,7 @@ config ARCH_AT91RM9200
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bool "AT91RM9200"
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config ARCH_AT91SAM9260
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bool "AT91SAM9260"
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bool "AT91SAM9260 or AT91SAM9XE"
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config ARCH_AT91SAM9261
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bool "AT91SAM9261"
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@ -93,13 +93,22 @@ endif
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if ARCH_AT91SAM9260
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comment "AT91SAM9260 Board Type"
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comment "AT91SAM9260 Variants"
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config MACH_AT91SAM9260EK
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bool "Atmel AT91SAM9260-EK Evaluation Kit"
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config ARCH_AT91SAM9260_SAM9XE
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bool "AT91SAM9XE"
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depends on ARCH_AT91SAM9260
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help
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Select this if you are using Atmel's AT91SAM9260-EK Evaluation Kit.
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Select this if you are using Atmel's AT91SAM9XE System-on-Chip.
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They are basicaly AT91SAM9260s with various sizes of embedded Flash.
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comment "AT91SAM9260 / AT91SAM9XE Board Type"
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config MACH_AT91SAM9260EK
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bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit"
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depends on ARCH_AT91SAM9260
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help
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Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit
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<http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
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endif
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@ -14,6 +14,7 @@
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/at91sam9260.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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@ -27,7 +28,11 @@ static struct map_desc at91sam9260_io_desc[] __initdata = {
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.pfn = __phys_to_pfn(AT91_BASE_SYS),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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}
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};
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static struct map_desc at91sam9260_sram_desc[] __initdata = {
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{
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.virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE,
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.pfn = __phys_to_pfn(AT91SAM9260_SRAM0_BASE),
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.length = AT91SAM9260_SRAM0_SIZE,
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@ -37,7 +42,14 @@ static struct map_desc at91sam9260_io_desc[] __initdata = {
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.pfn = __phys_to_pfn(AT91SAM9260_SRAM1_BASE),
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.length = AT91SAM9260_SRAM1_SIZE,
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.type = MT_DEVICE,
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},
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}
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};
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static struct map_desc at91sam9xe_sram_desc[] __initdata = {
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{
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.pfn = __phys_to_pfn(AT91SAM9XE_SRAM_BASE),
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.type = MT_DEVICE,
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}
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};
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/* --------------------------------------------------------------------
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@ -255,11 +267,37 @@ static void at91sam9260_reset(void)
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* AT91SAM9260 processor initialization
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* -------------------------------------------------------------------- */
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static void __init at91sam9xe_initialize(void)
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{
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unsigned long cidr, sram_size;
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cidr = at91_sys_read(AT91_DBGU_CIDR);
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switch (cidr & AT91_CIDR_SRAMSIZ) {
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case AT91_CIDR_SRAMSIZ_32K:
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sram_size = 2 * SZ_16K;
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break;
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case AT91_CIDR_SRAMSIZ_16K:
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default:
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sram_size = SZ_16K;
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}
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at91sam9xe_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
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at91sam9xe_sram_desc->length = sram_size;
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iotable_init(at91sam9xe_sram_desc, ARRAY_SIZE(at91sam9xe_sram_desc));
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}
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void __init at91sam9260_initialize(unsigned long main_clock)
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{
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/* Map peripherals */
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iotable_init(at91sam9260_io_desc, ARRAY_SIZE(at91sam9260_io_desc));
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if (cpu_is_at91sam9xe())
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at91sam9xe_initialize();
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else
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iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
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at91_arch_reset = at91sam9260_reset;
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at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
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| (1 << AT91SAM9260_ID_IRQ2);
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@ -35,6 +35,20 @@
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#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */
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#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */
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#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */
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#define AT91_CIDR_SRAMSIZ_1K (1 << 16)
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#define AT91_CIDR_SRAMSIZ_2K (2 << 16)
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#define AT91_CIDR_SRAMSIZ_112K (4 << 16)
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#define AT91_CIDR_SRAMSIZ_4K (5 << 16)
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#define AT91_CIDR_SRAMSIZ_80K (6 << 16)
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#define AT91_CIDR_SRAMSIZ_160K (7 << 16)
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#define AT91_CIDR_SRAMSIZ_8K (8 << 16)
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#define AT91_CIDR_SRAMSIZ_16K (9 << 16)
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#define AT91_CIDR_SRAMSIZ_32K (10 << 16)
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#define AT91_CIDR_SRAMSIZ_64K (11 << 16)
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#define AT91_CIDR_SRAMSIZ_128K (12 << 16)
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#define AT91_CIDR_SRAMSIZ_256K (13 << 16)
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#define AT91_CIDR_SRAMSIZ_96K (14 << 16)
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#define AT91_CIDR_SRAMSIZ_512K (15 << 16)
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#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */
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#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
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#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
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@ -113,6 +113,10 @@
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#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */
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#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */
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#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */
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#if 0
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/*
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* PIO pin definitions (peripheral A/B multiplexing).
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@ -22,6 +22,9 @@
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#define ARCH_ID_AT91SAM9261 0x019703a0
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#define ARCH_ID_AT91SAM9263 0x019607a0
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#define ARCH_ID_AT91SAM9XE128 0x329973a0
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#define ARCH_ID_AT91SAM9XE256 0x329a93a0
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#define ARCH_ID_AT91SAM9XE512 0x329aa3a0
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static inline unsigned long at91_cpu_identify(void)
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{
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@ -29,6 +32,16 @@ static inline unsigned long at91_cpu_identify(void)
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}
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#define ARCH_FAMILY_AT91X92 0x09200000
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#define ARCH_FAMILY_AT91SAM9 0x01900000
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#define ARCH_FAMILY_AT91SAM9XE 0x02900000
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static inline unsigned long at91_arch_identify(void)
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{
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return (at91_sys_read(AT91_DBGU_CIDR) & AT91_CIDR_ARCH);
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}
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#ifdef CONFIG_ARCH_AT91RM9200
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#define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200)
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#else
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@ -36,8 +49,10 @@ static inline unsigned long at91_cpu_identify(void)
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#endif
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#ifdef CONFIG_ARCH_AT91SAM9260
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#define cpu_is_at91sam9260() (at91_cpu_identify() == ARCH_ID_AT91SAM9260)
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#define cpu_is_at91sam9xe() (at91_arch_identify() == ARCH_FAMILY_AT91SAM9XE)
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#define cpu_is_at91sam9260() ((at91_cpu_identify() == ARCH_ID_AT91SAM9260) || cpu_is_at91sam9xe())
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#else
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#define cpu_is_at91sam9xe() (0)
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#define cpu_is_at91sam9260() (0)
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#endif
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