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power supply and reset changes for the v6.0 series 

power-supply core:
  - none
 
 drivers:
  - pwr-mlxbf: new reset driver for Mellanox BlueField
  - at91-reset: SAMA7G5 support
  - ab8500: continue refurbishing
  - misc. minor fixes
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Merge tag 'for-v6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply

Pull power supply and reset updates from Sebastian Reichel:
 "No core patches, only driver updates:

   - pwr-mlxbf: new reset driver for Mellanox BlueField

   - at91-reset: SAMA7G5 support

   - ab8500: continue refurbishing

   - misc minor fixes"

* tag 'for-v6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply: (29 commits)
  power: supply: olpc_battery: Hold the reference returned by of_find_compatible_node
  power: supply: ab8500: add missing destroy_workqueue in ab8500_charger_bind
  power: supply: ab8500: Remove flush_scheduled_work() call.
  power: supply: ab8500_fg: drop duplicated 'is' in comment
  power: supply: ab8500: Drop external charger leftovers
  power: supply: ab8500: Add MAINTAINERS entry
  dt-bindings: power: reset: qcom,pshold: convert to dtschema
  power: supply: Fix typo in power_supply_check_supplies
  power: reset: pwr-mlxbf: change rst_pwr_hid and low_pwr_hid from global to local variables
  power: reset: pwr-mlxbf: add missing include
  power: reset: at91-reset: add support for SAMA7G5
  power: reset: at91-reset: add reset_controller_dev support
  power: reset: at91-reset: add at91_reset_data
  power: reset: at91-reset: document structures and enums
  dt-bindings: reset: add sama7g5 definitions
  dt-bindings: reset: atmel,at91sam9260-reset: add sama7g5 bindings
  dt-bindings: reset: convert Atmel/Microchip reset controller to YAML
  power: reset: pwr-mlxbf: add BlueField SoC power control driver
  power: supply: ab8500: Exit maintenance if too low voltage
  power: supply: ab8500: Respect charge_restart_voltage_uv
  ...
This commit is contained in:
Linus Torvalds 2022-08-12 09:37:33 -07:00
parent d16b418fac c9d8468158
commit f7cdaeeab8
26 changed files with 462 additions and 630 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
Documentation/devicetree/bindings/arm/atmel-sysregs.txt
View File

@ -25,21 +25,6 @@ System Timer (ST) required properties:
Its subnodes can be:
- watchdog: compatible should be "atmel,at91rm9200-wdt"
RSTC Reset Controller required properties:
- compatible: Should be "atmel,<chip>-rstc".
<chip> can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7"
it also can be "microchip,sam9x60-rstc"
- reg: Should contain registers location and length
- clocks: phandle to input clock.
Example:
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&clk32k>;
};
RAMC SDRAM/DDR Controller required properties:
- compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
"atmel,at91sam9260-sdramc",

17
Documentation/devicetree/bindings/power/reset/msm-poweroff.txt
View File

@ -1,17 +0,0 @@
MSM Restart Driver
A power supply hold (ps-hold) bit is set to power the msm chipsets.
Clearing that bit allows us to restart/poweroff. The difference
between poweroff and restart is determined by unique power manager IC
settings.
Required Properties:
-compatible: "qcom,pshold"
-reg: Specifies the physical address of the ps-hold register
Example:
restart@fc4ab000 {
compatible = "qcom,pshold";
reg = <0xfc4ab000 0x4>;
};

35
Documentation/devicetree/bindings/power/reset/qcom,pshold.yaml Normal file
View File

@ -0,0 +1,35 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/reset/qcom,pshold.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SoC restart and power off
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description:
A power supply hold (ps-hold) bit is set to power the Qualcomm chipsets.
Clearing that bit allows us to restart/power off. The difference between
power off and restart is determined by unique power manager IC settings.
properties:
compatible:
const: qcom,pshold
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
reset-controller@fc4ab000 {
compatible = "qcom,pshold";
reg = <0xfc4ab000 0x4>;
};

2
Documentation/devicetree/bindings/power/supply/bq24190.yaml
View File

@ -28,7 +28,7 @@ properties:
maxItems: 1
usb-otg-vbus:
type: object
$ref: /schemas/regulator/regulator.yaml#
description: |
Regulator that is used to control the VBUS voltage direction for
either USB host mode or for charging on the OTG port

9
Documentation/devicetree/bindings/power/supply/qcom,pm8941-charger.yaml
View File

@ -117,11 +117,18 @@ properties:
be done externally to fully comply with the JEITA safety guidelines if this flag
is set.
usb-charge-current-limit:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 100000
maximum: 2500000
description: |
Default USB charge current limit in uA.
usb-otg-in-supply:
description: Reference to the regulator supplying power to the USB_OTG_IN pin.
otg-vbus:
type: object
$ref: /schemas/regulator/regulator.yaml#
description: |
This node defines a regulator used to control the direction of VBUS voltage.
Specifically whether to supply voltage to VBUS for host mode operation of the OTG port,

2
Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml
View File

@ -82,7 +82,7 @@ properties:
- 1 # SMB3XX_SYSOK_INOK_ACTIVE_HIGH
usb-vbus:
$ref: "../../regulator/regulator.yaml#"
$ref: /schemas/regulator/regulator.yaml#
type: object
properties:

68
Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml Normal file
View File

@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/atmel,at91sam9260-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel/Microchip System Reset Controller
maintainers:
- Claudiu Beznea <claudiu.beznea@microchip.com>
description: |
The system reset controller can be used to reset the CPU. In case of
SAMA7G5 it can also reset some devices (e.g. USB PHYs).
properties:
compatible:
oneOf:
- items:
- enum:
- atmel,at91sam9260-rstc
- atmel,at91sam9g45-rstc
- atmel,sama5d3-rstc
- microchip,sam9x60-rstc
- microchip,sama7g5-rstc
- items:
- const: atmel,sama5d3-rstc
- const: atmel,at91sam9g45-rstc
reg:
minItems: 1
items:
- description: base registers for system reset control
- description: registers for device specific reset control
clocks:
maxItems: 1
"#reset-cells":
const: 1
required:
- compatible
- reg
- clocks
allOf:
- if:
properties:
compatible:
contains:
enum:
- microchip,sama7g5-rstc
then:
required:
- "#reset-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/at91.h>
reset-controller@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
};

5
MAINTAINERS
View File

@ -264,6 +264,11 @@ W: http://www.adaptec.com/
F: Documentation/scsi/aacraid.rst
F: drivers/scsi/aacraid/
AB8500 BATTERY AND CHARGER DRIVERS
M: Linus Walleij <linus.walleij@linaro.org>
F: Documentation/devicetree/bindings/power/supply/*ab8500*
F: drivers/power/supply/*ab8500*
ABI/API
L: linux-api@vger.kernel.org
F: include/linux/syscalls.h

6
drivers/power/reset/Kconfig
View File

@ -297,4 +297,10 @@ config NVMEM_REBOOT_MODE
then the bootloader can read it and take different
action according to the mode.
config POWER_MLXBF
tristate "Mellanox BlueField power handling driver"
depends on (GPIO_MLXBF2 && ACPI)
help
This driver supports reset or low power mode handling for Mellanox BlueField.
endif

1
drivers/power/reset/Makefile
View File

@ -35,3 +35,4 @@ obj-$(CONFIG_REBOOT_MODE) += reboot-mode.o
obj-$(CONFIG_SYSCON_REBOOT_MODE) += syscon-reboot-mode.o
obj-$(CONFIG_POWER_RESET_SC27XX) += sc27xx-poweroff.o
obj-$(CONFIG_NVMEM_REBOOT_MODE) += nvmem-reboot-mode.o
obj-$(CONFIG_POWER_MLXBF) += pwr-mlxbf.o

184
drivers/power/reset/at91-reset.c
View File

@ -17,10 +17,13 @@
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/reset-controller.h>
#include <soc/at91/at91sam9_ddrsdr.h>
#include <soc/at91/at91sam9_sdramc.h>
#include <dt-bindings/reset/sama7g5-reset.h>
#define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */
#define AT91_RSTC_PROCRST BIT(0) /* Processor Reset */
#define AT91_RSTC_PERRST BIT(2) /* Peripheral Reset */
@ -39,6 +42,17 @@
#define AT91_RSTC_URSTIEN BIT(4) /* User Reset Interrupt Enable */
#define AT91_RSTC_ERSTL GENMASK(11, 8) /* External Reset Length */
/**
* enum reset_type - reset types
* @RESET_TYPE_GENERAL: first power-up reset
* @RESET_TYPE_WAKEUP: return from backup mode
* @RESET_TYPE_WATCHDOG: watchdog fault
* @RESET_TYPE_SOFTWARE: processor reset required by software
* @RESET_TYPE_USER: NRST pin detected low
* @RESET_TYPE_CPU_FAIL: CPU clock failure detection
* @RESET_TYPE_XTAL_FAIL: 32KHz crystal failure dectection fault
* @RESET_TYPE_ULP2: ULP2 reset
*/
enum reset_type {
RESET_TYPE_GENERAL = 0,
RESET_TYPE_WAKEUP = 1,
@ -50,15 +64,48 @@ enum reset_type {
RESET_TYPE_ULP2 = 8,
};
/**
* struct at91_reset - AT91 reset specific data structure
* @rstc_base: base address for system reset
* @ramc_base: array with base addresses of RAM controllers
* @dev_base: base address for devices reset
* @sclk: slow clock
* @data: platform specific reset data
* @rcdev: reset controller device
* @lock: lock for devices reset register access
* @nb: reset notifier block
* @args: SoC specific system reset arguments
* @ramc_lpr: SDRAM Controller Low Power Register
*/
struct at91_reset {
void __iomem *rstc_base;
void __iomem *ramc_base[2];
void __iomem *dev_base;
struct clk *sclk;
const struct at91_reset_data *data;
struct reset_controller_dev rcdev;
spinlock_t lock;
struct notifier_block nb;
u32 args;
u32 ramc_lpr;
};
#define to_at91_reset(r) container_of(r, struct at91_reset, rcdev)
/**
* struct at91_reset_data - AT91 reset data
* @reset_args: SoC specific system reset arguments
* @n_device_reset: number of device resets
* @device_reset_min_id: min id for device reset
* @device_reset_max_id: max id for device reset
*/
struct at91_reset_data {
u32 reset_args;
u32 n_device_reset;
u8 device_reset_min_id;
u8 device_reset_max_id;
};
/*
* unless the SDRAM is cleanly shutdown before we hit the
* reset register it can be left driving the data bus and
@ -95,7 +142,7 @@ static int at91_reset(struct notifier_block *this, unsigned long mode,
"r" (reset->rstc_base),
"r" (1),
"r" cpu_to_le32(AT91_DDRSDRC_LPCB_POWER_DOWN),
"r" (reset->args),
"r" (reset->data->reset_args),
"r" (reset->ramc_lpr)
: "r4");
@ -153,34 +200,133 @@ static const struct of_device_id at91_ramc_of_match[] = {
{ /* sentinel */ }
};
static const struct at91_reset_data sam9260 = {
.reset_args = AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST,
};
static const struct at91_reset_data samx7 = {
.reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST,
};
static const struct at91_reset_data sama7g5 = {
.reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST,
.n_device_reset = 3,
.device_reset_min_id = SAMA7G5_RESET_USB_PHY1,
.device_reset_max_id = SAMA7G5_RESET_USB_PHY3,
};
static const struct of_device_id at91_reset_of_match[] = {
{
.compatible = "atmel,at91sam9260-rstc",
.data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST |
AT91_RSTC_PROCRST),
.data = &sam9260,
},
{
.compatible = "atmel,at91sam9g45-rstc",
.data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST |
AT91_RSTC_PROCRST)
.data = &sam9260,
},
{
.compatible = "atmel,sama5d3-rstc",
.data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST |
AT91_RSTC_PROCRST)
.data = &sam9260,
},
{
.compatible = "atmel,samx7-rstc",
.data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PROCRST)
.data = &samx7,
},
{
.compatible = "microchip,sam9x60-rstc",
.data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PROCRST)
.data = &samx7,
},
{
.compatible = "microchip,sama7g5-rstc",
.data = &sama7g5,
},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, at91_reset_of_match);
static int at91_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct at91_reset *reset = to_at91_reset(rcdev);
unsigned long flags;
u32 val;
spin_lock_irqsave(&reset->lock, flags);
val = readl_relaxed(reset->dev_base);
if (assert)
val |= BIT(id);
else
val &= ~BIT(id);
writel_relaxed(val, reset->dev_base);
spin_unlock_irqrestore(&reset->lock, flags);
return 0;
}
static int at91_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return at91_reset_update(rcdev, id, true);
}
static int at91_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return at91_reset_update(rcdev, id, false);
}
static int at91_reset_dev_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct at91_reset *reset = to_at91_reset(rcdev);
u32 val;
val = readl_relaxed(reset->dev_base);
return !!(val & BIT(id));
}
static const struct reset_control_ops at91_reset_ops = {
.assert = at91_reset_assert,
.deassert = at91_reset_deassert,
.status = at91_reset_dev_status,
};
static int at91_reset_of_xlate(struct reset_controller_dev *rcdev,
const struct of_phandle_args *reset_spec)
{
struct at91_reset *reset = to_at91_reset(rcdev);
if (!reset->data->n_device_reset ||
(reset_spec->args[0] < reset->data->device_reset_min_id ||
reset_spec->args[0] > reset->data->device_reset_max_id))
return -EINVAL;
return reset_spec->args[0];
}
static int at91_rcdev_init(struct at91_reset *reset,
struct platform_device *pdev)
{
if (!reset->data->n_device_reset)
return 0;
reset->dev_base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 1,
NULL);
if (IS_ERR(reset->dev_base))
return -ENODEV;
spin_lock_init(&reset->lock);
reset->rcdev.ops = &at91_reset_ops;
reset->rcdev.owner = THIS_MODULE;
reset->rcdev.of_node = pdev->dev.of_node;
reset->rcdev.nr_resets = reset->data->n_device_reset;
reset->rcdev.of_reset_n_cells = 1;
reset->rcdev.of_xlate = at91_reset_of_xlate;
return devm_reset_controller_register(&pdev->dev, &reset->rcdev);
}
static int __init at91_reset_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
@ -212,10 +358,12 @@ static int __init at91_reset_probe(struct platform_device *pdev)
}
}
match = of_match_node(at91_reset_of_match, pdev->dev.of_node);
reset->data = device_get_match_data(&pdev->dev);
if (!reset->data)
return -ENODEV;
reset->nb.notifier_call = at91_reset;
reset->nb.priority = 192;
reset->args = (u32)match->data;
reset->sclk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(reset->sclk))
@ -229,6 +377,10 @@ static int __init at91_reset_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, reset);
ret = at91_rcdev_init(reset, pdev);
if (ret)
goto disable_clk;
if (of_device_is_compatible(pdev->dev.of_node, "microchip,sam9x60-rstc")) {
u32 val = readl(reset->rstc_base + AT91_RSTC_MR);
@ -237,14 +389,16 @@ static int __init at91_reset_probe(struct platform_device *pdev)
}
ret = register_restart_handler(&reset->nb);
if (ret) {
clk_disable_unprepare(reset->sclk);
return ret;
}
if (ret)
goto disable_clk;
at91_reset_status(pdev, reset->rstc_base);
return 0;
disable_clk:
clk_disable_unprepare(reset->sclk);
return ret;
}
static int __exit at91_reset_remove(struct platform_device *pdev)

97
drivers/power/reset/pwr-mlxbf.c Normal file
View File

@ -0,0 +1,97 @@
// SPDX-License-Identifier: GPL-2.0-only or BSD-3-Clause
/*
* Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES.
*/
#include <linux/acpi.h>
#include <linux/device.h>
#include <linux/devm-helpers.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/reboot.h>
#include <linux/types.h>
struct pwr_mlxbf {
struct work_struct send_work;
const char *hid;
};
static void pwr_mlxbf_send_work(struct work_struct *work)
{
acpi_bus_generate_netlink_event("button/power.*", "Power Button", 0x80, 1);
}
static irqreturn_t pwr_mlxbf_irq(int irq, void *ptr)
{
const char *rst_pwr_hid = "MLNXBF24";
const char *low_pwr_hid = "MLNXBF29";
struct pwr_mlxbf *priv = ptr;
if (!strncmp(priv->hid, rst_pwr_hid, 8))
emergency_restart();
if (!strncmp(priv->hid, low_pwr_hid, 8))
schedule_work(&priv->send_work);
return IRQ_HANDLED;
}
static int pwr_mlxbf_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct acpi_device *adev;
struct pwr_mlxbf *priv;
const char *hid;
int irq, err;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
adev = ACPI_COMPANION(dev);
if (!adev)
return -ENXIO;
hid = acpi_device_hid(adev);
priv->hid = hid;
irq = acpi_dev_gpio_irq_get(ACPI_COMPANION(dev), 0);
if (irq < 0)
return dev_err_probe(dev, irq, "Error getting %s irq.\n", priv->hid);
err = devm_work_autocancel(dev, &priv->send_work, pwr_mlxbf_send_work);
if (err)
return err;
err = devm_request_irq(dev, irq, pwr_mlxbf_irq, 0, hid, priv);
if (err)
dev_err(dev, "Failed request of %s irq\n", priv->hid);
return err;
}
static const struct acpi_device_id __maybe_unused pwr_mlxbf_acpi_match[] = {
{ "MLNXBF24", 0 },
{ "MLNXBF29", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, pwr_mlxbf_acpi_match);
static struct platform_driver pwr_mlxbf_driver = {
.driver = {
.name = "pwr_mlxbf",
.acpi_match_table = pwr_mlxbf_acpi_match,
},
.probe = pwr_mlxbf_probe,
};
module_platform_driver(pwr_mlxbf_driver);
MODULE_DESCRIPTION("Mellanox BlueField power driver");
MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");
MODULE_LICENSE("Dual BSD/GPL");

4
drivers/power/supply/ab8500-chargalg.h
View File

@ -34,7 +34,6 @@ struct ux500_charger_ops {
* @max_out_volt_uv maximum output charger voltage in uV
* @max_out_curr_ua maximum output charger current in uA
* @enabled indicates if this charger is used or not
* @external external charger unit (pm2xxx)
*/
struct ux500_charger {
struct power_supply *psy;
@ -43,9 +42,6 @@ struct ux500_charger {
int max_out_curr_ua;
int wdt_refresh;
bool enabled;
bool external;
};
extern struct blocking_notifier_head charger_notifier_list;
#endif /* _AB8500_CHARGALG_H_ */

1
drivers/power/supply/ab8500_btemp.c
View File

@ -697,7 +697,6 @@ static void ab8500_btemp_unbind(struct device *dev, struct device *master,
/* Delete the work queue */
destroy_workqueue(di->btemp_wq);
flush_scheduled_work();
}
static const struct component_ops ab8500_btemp_component_ops = {

70
drivers/power/supply/ab8500_chargalg.c
View File

@ -246,9 +246,6 @@ struct ab8500_chargalg {
struct kobject chargalg_kobject;
};
/*External charger prepare notifier*/
BLOCKING_NOTIFIER_HEAD(charger_notifier_list);
/* Main battery properties */
static enum power_supply_property ab8500_chargalg_props[] = {
POWER_SUPPLY_PROP_STATUS,
@ -343,8 +340,7 @@ static int ab8500_chargalg_check_charger_enable(struct ab8500_chargalg *di)
return di->usb_chg->ops.check_enable(di->usb_chg,
bi->constant_charge_voltage_max_uv,
bi->constant_charge_current_max_ua);
} else if ((di->chg_info.charger_type & AC_CHG) &&
!(di->ac_chg->external)) {
} else if (di->chg_info.charger_type & AC_CHG) {
return di->ac_chg->ops.check_enable(di->ac_chg,
bi->constant_charge_voltage_max_uv,
bi->constant_charge_current_max_ua);
@ -473,15 +469,6 @@ static int ab8500_chargalg_kick_watchdog(struct ab8500_chargalg *di)
/* Check if charger exists and kick watchdog if charging */
if (di->ac_chg && di->ac_chg->ops.kick_wd &&
di->chg_info.online_chg & AC_CHG) {
/*
* If AB charger watchdog expired, pm2xxx charging
* gets disabled. To be safe, kick both AB charger watchdog
* and pm2xxx watchdog.
*/
if (di->ac_chg->external &&
di->usb_chg && di->usb_chg->ops.kick_wd)
di->usb_chg->ops.kick_wd(di->usb_chg);
return di->ac_chg->ops.kick_wd(di->ac_chg);
} else if (di->usb_chg && di->usb_chg->ops.kick_wd &&
di->chg_info.online_chg & USB_CHG)
@ -517,14 +504,6 @@ static int ab8500_chargalg_ac_en(struct ab8500_chargalg *di, int enable,
di->chg_info.ac_iset_ua = iset_ua;
di->chg_info.ac_vset_uv = vset_uv;
/* Enable external charger */
if (enable && di->ac_chg->external &&
!ab8500_chargalg_ex_ac_enable_toggle) {
blocking_notifier_call_chain(&charger_notifier_list,
0, di->dev);
ab8500_chargalg_ex_ac_enable_toggle++;
}
return di->ac_chg->ops.enable(di->ac_chg, enable, vset_uv, iset_ua);
}
@ -1216,6 +1195,34 @@ static void ab8500_chargalg_external_power_changed(struct power_supply *psy)
queue_work(di->chargalg_wq, &di->chargalg_work);
}
/**
* ab8500_chargalg_time_to_restart() - time to restart CC/CV charging?
* @di: charging algorithm state
*
* This checks if the voltage or capacity of the battery has fallen so
* low that we need to restart the CC/CV charge cycle.
*/
static bool ab8500_chargalg_time_to_restart(struct ab8500_chargalg *di)
{
struct power_supply_battery_info *bi = di->bm->bi;
/* Sanity check - these need to have some reasonable values */
if (!di->batt_data.volt_uv || !di->batt_data.percent)
return false;
/* Some batteries tell us at which voltage we should restart charging */
if (bi->charge_restart_voltage_uv > 0) {
if (di->batt_data.volt_uv <= bi->charge_restart_voltage_uv)
return true;
/* Else we restart as we reach a certain capacity */
} else {
if (di->batt_data.percent <= AB8500_RECHARGE_CAP)
return true;
}
return false;
}
/**
* ab8500_chargalg_algorithm() - Main function for the algorithm
* @di: pointer to the ab8500_chargalg structure
@ -1459,7 +1466,7 @@ static void ab8500_chargalg_algorithm(struct ab8500_chargalg *di)
fallthrough;
case STATE_WAIT_FOR_RECHARGE:
if (di->batt_data.percent <= AB8500_RECHARGE_CAP)
if (ab8500_chargalg_time_to_restart(di))
ab8500_chargalg_state_to(di, STATE_NORMAL_INIT);
break;
@ -1486,6 +1493,14 @@ static void ab8500_chargalg_algorithm(struct ab8500_chargalg *di)
ab8500_chargalg_stop_maintenance_timer(di);
ab8500_chargalg_state_to(di, STATE_MAINTENANCE_B_INIT);
}
/*
* This happens if the voltage drops too quickly during
* maintenance charging, especially in older batteries.
*/
if (ab8500_chargalg_time_to_restart(di)) {
ab8500_chargalg_state_to(di, STATE_NORMAL_INIT);
dev_info(di->dev, "restarted charging from maintenance state A - battery getting old?\n");
}
break;
case STATE_MAINTENANCE_B_INIT:
@ -1510,6 +1525,14 @@ static void ab8500_chargalg_algorithm(struct ab8500_chargalg *di)
ab8500_chargalg_stop_maintenance_timer(di);
ab8500_chargalg_state_to(di, STATE_NORMAL_INIT);
}
/*
* This happens if the voltage drops too quickly during
* maintenance charging, especially in older batteries.
*/
if (ab8500_chargalg_time_to_restart(di)) {
ab8500_chargalg_state_to(di, STATE_NORMAL_INIT);
dev_info(di->dev, "restarted charging from maintenance state B - battery getting old?\n");
}
break;
case STATE_TEMP_LOWHIGH_INIT:
@ -1746,7 +1769,6 @@ static void ab8500_chargalg_unbind(struct device *dev, struct device *master,
/* Delete the work queue */
destroy_workqueue(di->chargalg_wq);
flush_scheduled_work();
}
static const struct component_ops ab8500_chargalg_component_ops = {

48
drivers/power/supply/ab8500_charger.c
View File

@ -1716,29 +1716,6 @@ static int ab8500_charger_usb_en(struct ux500_charger *charger,
return ret;
}
static int ab8500_external_charger_prepare(struct notifier_block *charger_nb,
unsigned long event, void *data)
{
int ret;
struct device *dev = data;
/*Toggle External charger control pin*/
ret = abx500_set_register_interruptible(dev, AB8500_SYS_CTRL1_BLOCK,
AB8500_SYS_CHARGER_CONTROL_REG,
EXTERNAL_CHARGER_DISABLE_REG_VAL);
if (ret < 0) {
dev_err(dev, "write reg failed %d\n", ret);
goto out;
}
ret = abx500_set_register_interruptible(dev, AB8500_SYS_CTRL1_BLOCK,
AB8500_SYS_CHARGER_CONTROL_REG,
EXTERNAL_CHARGER_ENABLE_REG_VAL);
if (ret < 0)
dev_err(dev, "Write reg failed %d\n", ret);
out:
return ret;
}
/**
* ab8500_charger_usb_check_enable() - enable usb charging
* @charger: pointer to the ux500_charger structure
@ -3316,10 +3293,6 @@ static int __maybe_unused ab8500_charger_suspend(struct device *dev)
return 0;
}
static struct notifier_block charger_nb = {
.notifier_call = ab8500_external_charger_prepare,
};
static char *supply_interface[] = {
"ab8500_chargalg",
"ab8500_fg",
@ -3378,6 +3351,7 @@ static int ab8500_charger_bind(struct device *dev)
ret = component_bind_all(dev, di);
if (ret) {
dev_err(dev, "can't bind component devices\n");
destroy_workqueue(di->charger_wq);
return ret;
}
@ -3404,8 +3378,6 @@ static void ab8500_charger_unbind(struct device *dev)
/* Delete the work queue */
destroy_workqueue(di->charger_wq);
flush_scheduled_work();
/* Unbind fg, btemp, algorithm */
component_unbind_all(dev, di);
}
@ -3540,7 +3512,6 @@ static int ab8500_charger_probe(struct platform_device *pdev)
*/
if (!is_ab8505(di->parent))
di->ac_chg.enabled = true;
di->ac_chg.external = false;
/* USB supply */
/* ux500_charger sub-class */
@ -3553,7 +3524,6 @@ static int ab8500_charger_probe(struct platform_device *pdev)
di->usb_chg.max_out_curr_ua =
ab8500_charge_output_curr_map[ARRAY_SIZE(ab8500_charge_output_curr_map) - 1];
di->usb_chg.wdt_refresh = CHG_WD_INTERVAL;
di->usb_chg.external = false;
di->usb_state.usb_current_ua = -1;
mutex_init(&di->charger_attached_mutex);
@ -3677,17 +3647,11 @@ static int ab8500_charger_probe(struct platform_device *pdev)
goto remove_ab8500_bm;
}
/* Notifier for external charger enabling */
if (!di->ac_chg.enabled)
blocking_notifier_chain_register(
&charger_notifier_list, &charger_nb);
di->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
if (IS_ERR_OR_NULL(di->usb_phy)) {
dev_err(dev, "failed to get usb transceiver\n");
ret = -EINVAL;
goto out_charger_notifier;
goto remove_ab8500_bm;
}
di->nb.notifier_call = ab8500_charger_usb_notifier_call;
ret = usb_register_notifier(di->usb_phy, &di->nb);
@ -3696,7 +3660,6 @@ static int ab8500_charger_probe(struct platform_device *pdev)
goto put_usb_phy;
}
ret = component_master_add_with_match(&pdev->dev,
&ab8500_charger_comp_ops,
match);
@ -3711,10 +3674,6 @@ free_notifier:
usb_unregister_notifier(di->usb_phy, &di->nb);
put_usb_phy:
usb_put_phy(di->usb_phy);
out_charger_notifier:
if (!di->ac_chg.enabled)
blocking_notifier_chain_unregister(
&charger_notifier_list, &charger_nb);
remove_ab8500_bm:
ab8500_bm_of_remove(di->usb_chg.psy, di->bm);
return ret;
@ -3729,9 +3688,6 @@ static int ab8500_charger_remove(struct platform_device *pdev)
usb_unregister_notifier(di->usb_phy, &di->nb);
ab8500_bm_of_remove(di->usb_chg.psy, di->bm);
usb_put_phy(di->usb_phy);
if (!di->ac_chg.enabled)
blocking_notifier_chain_unregister(
&charger_notifier_list, &charger_nb);
return 0;
}

3
drivers/power/supply/ab8500_fg.c
View File

@ -412,7 +412,7 @@ static int ab8500_fg_add_cap_sample(struct ab8500_fg *di, int sample)
* ab8500_fg_clear_cap_samples() - Clear average filter
* @di: pointer to the ab8500_fg structure
*
* The capacity filter is is reset to zero.
* The capacity filter is reset to zero.
*/
static void ab8500_fg_clear_cap_samples(struct ab8500_fg *di)
{
@ -3234,7 +3234,6 @@ static int ab8500_fg_remove(struct platform_device *pdev)
struct ab8500_fg *di = platform_get_drvdata(pdev);
destroy_workqueue(di->fg_wq);
flush_scheduled_work();
component_del(&pdev->dev, &ab8500_fg_component_ops);
list_del(&di->node);
ab8500_fg_sysfs_exit(di);

2
drivers/power/supply/bq24257_charger.c
View File

@ -287,7 +287,7 @@ static int bq24257_set_input_current_limit(struct bq24257_device *bq,
{
/*
* Address the case where the user manually sets an input current limit
* while the charger auto-detection mechanism is is active. In this
* while the charger auto-detection mechanism is active. In this
* case we want to abort and go straight to the user-specified value.
*/
if (bq->iilimit_autoset_enable)

2
drivers/power/supply/cros_peripheral_charger.c
View File

@ -63,7 +63,7 @@ static int cros_pchg_ec_command(const struct charger_data *charger,
struct cros_ec_command *msg;
int ret;
msg = kzalloc(sizeof(*msg) + max(outsize, insize), GFP_KERNEL);
msg = kzalloc(struct_size(msg, data, max(outsize, insize)), GFP_KERNEL);
if (!msg)
return -ENOMEM;

4
drivers/power/supply/goldfish_battery.c
View File

@ -221,10 +221,8 @@ static int goldfish_battery_probe(struct platform_device *pdev)
}
data->irq = platform_get_irq(pdev, 0);
if (data->irq < 0) {
dev_err(&pdev->dev, "platform_get_irq failed\n");
if (data->irq < 0)
return -ENODEV;
}
ret = devm_request_irq(&pdev->dev, data->irq,
goldfish_battery_interrupt,

2
drivers/power/supply/lp8788-charger.c
View File

@ -376,7 +376,7 @@ static int lp8788_update_charger_params(struct platform_device *pdev,
return 0;
}
/* settting charging parameters */
/* setting charging parameters */
for (i = 0; i < pdata->num_chg_params; i++) {
param = pdata->chg_params + i;

4
drivers/power/supply/max77976_charger.c
View File

@ -3,7 +3,7 @@
* max77976_charger.c - Driver for the Maxim MAX77976 battery charger
*
* Copyright (C) 2021 Luca Ceresoli
* Author: Luca Ceresoli <luca@lucaceresoli.net>
* Author: Luca Ceresoli <luca.ceresoli@bootlin.com>
*/
#include <linux/i2c.h>
@ -504,6 +504,6 @@ static struct i2c_driver max77976_driver = {
};
module_i2c_driver(max77976_driver);
MODULE_AUTHOR("Luca Ceresoli <luca@lucaceresoli.net>");
MODULE_AUTHOR("Luca Ceresoli <luca.ceresoli@bootlin.com>");
MODULE_DESCRIPTION("Maxim MAX77976 charger driver");
MODULE_LICENSE("GPL v2");

5
drivers/power/supply/olpc_battery.c
View File

@ -635,6 +635,7 @@ static int olpc_battery_probe(struct platform_device *pdev)
struct power_supply_config bat_psy_cfg = {};
struct power_supply_config ac_psy_cfg = {};
struct olpc_battery_data *data;
struct device_node *np;
uint8_t status;
uint8_t ecver;
int ret;
@ -649,7 +650,9 @@ static int olpc_battery_probe(struct platform_device *pdev)
if (ret)
return ret;
if (of_find_compatible_node(NULL, NULL, "olpc,xo1.75-ec")) {
np = of_find_compatible_node(NULL, NULL, "olpc,xo1.75-ec");
if (np) {
of_node_put(np);
/* XO 1.75 */
data->new_proto = true;
data->little_endian = true;

492
drivers/power/supply/pm2301_charger.h
View File

@ -1,492 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) ST-Ericsson SA 2012
*
* PM2301 power supply interface
*/
#ifndef PM2301_CHARGER_H
#define PM2301_CHARGER_H
/* Watchdog timeout constant */
#define WD_TIMER 0x30 /* 4min */
#define WD_KICK_INTERVAL (30 * HZ)
#define PM2XXX_NUM_INT_REG 0x6
/* Constant voltage/current */
#define PM2XXX_CONST_CURR 0x0
#define PM2XXX_CONST_VOLT 0x1
/* Lowest charger voltage is 3.39V -> 0x4E */
#define LOW_VOLT_REG 0x4E
#define PM2XXX_BATT_CTRL_REG1 0x00
#define PM2XXX_BATT_CTRL_REG2 0x01
#define PM2XXX_BATT_CTRL_REG3 0x02
#define PM2XXX_BATT_CTRL_REG4 0x03
#define PM2XXX_BATT_CTRL_REG5 0x04
#define PM2XXX_BATT_CTRL_REG6 0x05
#define PM2XXX_BATT_CTRL_REG7 0x06
#define PM2XXX_BATT_CTRL_REG8 0x07
#define PM2XXX_NTC_CTRL_REG1 0x08
#define PM2XXX_NTC_CTRL_REG2 0x09
#define PM2XXX_BATT_CTRL_REG9 0x0A
#define PM2XXX_BATT_STAT_REG1 0x0B
#define PM2XXX_INP_VOLT_VPWR2 0x11
#define PM2XXX_INP_DROP_VPWR2 0x13
#define PM2XXX_INP_VOLT_VPWR1 0x15
#define PM2XXX_INP_DROP_VPWR1 0x17
#define PM2XXX_INP_MODE_VPWR 0x18
#define PM2XXX_BATT_WD_KICK 0x70
#define PM2XXX_DEV_VER_STAT 0x0C
#define PM2XXX_THERM_WARN_CTRL_REG 0x20
#define PM2XXX_BATT_DISC_REG 0x21
#define PM2XXX_BATT_LOW_LEV_COMP_REG 0x22
#define PM2XXX_BATT_LOW_LEV_VAL_REG 0x23
#define PM2XXX_I2C_PAD_CTRL_REG 0x24
#define PM2XXX_SW_CTRL_REG 0x26
#define PM2XXX_LED_CTRL_REG 0x28
#define PM2XXX_REG_INT1 0x40
#define PM2XXX_MASK_REG_INT1 0x50
#define PM2XXX_SRCE_REG_INT1 0x60
#define PM2XXX_REG_INT2 0x41
#define PM2XXX_MASK_REG_INT2 0x51
#define PM2XXX_SRCE_REG_INT2 0x61
#define PM2XXX_REG_INT3 0x42
#define PM2XXX_MASK_REG_INT3 0x52
#define PM2XXX_SRCE_REG_INT3 0x62
#define PM2XXX_REG_INT4 0x43
#define PM2XXX_MASK_REG_INT4 0x53
#define PM2XXX_SRCE_REG_INT4 0x63
#define PM2XXX_REG_INT5 0x44
#define PM2XXX_MASK_REG_INT5 0x54
#define PM2XXX_SRCE_REG_INT5 0x64
#define PM2XXX_REG_INT6 0x45
#define PM2XXX_MASK_REG_INT6 0x55
#define PM2XXX_SRCE_REG_INT6 0x65
#define VPWR_OVV 0x0
#define VSYSTEM_OVV 0x1
/* control Reg 1 */
#define PM2XXX_CH_RESUME_EN 0x1
#define PM2XXX_CH_RESUME_DIS 0x0
/* control Reg 2 */
#define PM2XXX_CH_AUTO_RESUME_EN 0X2
#define PM2XXX_CH_AUTO_RESUME_DIS 0X0
#define PM2XXX_CHARGER_ENA 0x4
#define PM2XXX_CHARGER_DIS 0x0
/* control Reg 3 */
#define PM2XXX_CH_WD_CC_PHASE_OFF 0x0
#define PM2XXX_CH_WD_CC_PHASE_5MIN 0x1
#define PM2XXX_CH_WD_CC_PHASE_10MIN 0x2
#define PM2XXX_CH_WD_CC_PHASE_30MIN 0x3
#define PM2XXX_CH_WD_CC_PHASE_60MIN 0x4
#define PM2XXX_CH_WD_CC_PHASE_120MIN 0x5
#define PM2XXX_CH_WD_CC_PHASE_240MIN 0x6
#define PM2XXX_CH_WD_CC_PHASE_360MIN 0x7
#define PM2XXX_CH_WD_CV_PHASE_OFF (0x0<<3)
#define PM2XXX_CH_WD_CV_PHASE_5MIN (0x1<<3)
#define PM2XXX_CH_WD_CV_PHASE_10MIN (0x2<<3)
#define PM2XXX_CH_WD_CV_PHASE_30MIN (0x3<<3)
#define PM2XXX_CH_WD_CV_PHASE_60MIN (0x4<<3)
#define PM2XXX_CH_WD_CV_PHASE_120MIN (0x5<<3)
#define PM2XXX_CH_WD_CV_PHASE_240MIN (0x6<<3)
#define PM2XXX_CH_WD_CV_PHASE_360MIN (0x7<<3)
/* control Reg 4 */
#define PM2XXX_CH_WD_PRECH_PHASE_OFF 0x0
#define PM2XXX_CH_WD_PRECH_PHASE_1MIN 0x1
#define PM2XXX_CH_WD_PRECH_PHASE_5MIN 0x2
#define PM2XXX_CH_WD_PRECH_PHASE_10MIN 0x3
#define PM2XXX_CH_WD_PRECH_PHASE_30MIN 0x4
#define PM2XXX_CH_WD_PRECH_PHASE_60MIN 0x5
#define PM2XXX_CH_WD_PRECH_PHASE_120MIN 0x6
#define PM2XXX_CH_WD_PRECH_PHASE_240MIN 0x7
/* control Reg 5 */
#define PM2XXX_CH_WD_AUTO_TIMEOUT_NONE 0x0
#define PM2XXX_CH_WD_AUTO_TIMEOUT_20MIN 0x1
/* control Reg 6 */
#define PM2XXX_DIR_CH_CC_CURRENT_MASK 0x0F
#define PM2XXX_DIR_CH_CC_CURRENT_200MA 0x0
#define PM2XXX_DIR_CH_CC_CURRENT_400MA 0x2
#define PM2XXX_DIR_CH_CC_CURRENT_600MA 0x3
#define PM2XXX_DIR_CH_CC_CURRENT_800MA 0x4
#define PM2XXX_DIR_CH_CC_CURRENT_1000MA 0x5
#define PM2XXX_DIR_CH_CC_CURRENT_1200MA 0x6
#define PM2XXX_DIR_CH_CC_CURRENT_1400MA 0x7
#define PM2XXX_DIR_CH_CC_CURRENT_1600MA 0x8
#define PM2XXX_DIR_CH_CC_CURRENT_1800MA 0x9
#define PM2XXX_DIR_CH_CC_CURRENT_2000MA 0xA
#define PM2XXX_DIR_CH_CC_CURRENT_2200MA 0xB
#define PM2XXX_DIR_CH_CC_CURRENT_2400MA 0xC
#define PM2XXX_DIR_CH_CC_CURRENT_2600MA 0xD
#define PM2XXX_DIR_CH_CC_CURRENT_2800MA 0xE
#define PM2XXX_DIR_CH_CC_CURRENT_3000MA 0xF
#define PM2XXX_CH_PRECH_CURRENT_MASK 0x30
#define PM2XXX_CH_PRECH_CURRENT_25MA (0x0<<4)
#define PM2XXX_CH_PRECH_CURRENT_50MA (0x1<<4)
#define PM2XXX_CH_PRECH_CURRENT_75MA (0x2<<4)
#define PM2XXX_CH_PRECH_CURRENT_100MA (0x3<<4)
#define PM2XXX_CH_EOC_CURRENT_MASK 0xC0
#define PM2XXX_CH_EOC_CURRENT_100MA (0x0<<6)
#define PM2XXX_CH_EOC_CURRENT_150MA (0x1<<6)
#define PM2XXX_CH_EOC_CURRENT_300MA (0x2<<6)
#define PM2XXX_CH_EOC_CURRENT_400MA (0x3<<6)
/* control Reg 7 */
#define PM2XXX_CH_PRECH_VOL_2_5 0x0
#define PM2XXX_CH_PRECH_VOL_2_7 0x1
#define PM2XXX_CH_PRECH_VOL_2_9 0x2
#define PM2XXX_CH_PRECH_VOL_3_1 0x3
#define PM2XXX_CH_VRESUME_VOL_3_2 (0x0<<2)
#define PM2XXX_CH_VRESUME_VOL_3_4 (0x1<<2)
#define PM2XXX_CH_VRESUME_VOL_3_6 (0x2<<2)
#define PM2XXX_CH_VRESUME_VOL_3_8 (0x3<<2)
/* control Reg 8 */
#define PM2XXX_CH_VOLT_MASK 0x3F
#define PM2XXX_CH_VOLT_3_5 0x0
#define PM2XXX_CH_VOLT_3_5225 0x1
#define PM2XXX_CH_VOLT_3_6 0x4
#define PM2XXX_CH_VOLT_3_7 0x8
#define PM2XXX_CH_VOLT_4_0 0x14
#define PM2XXX_CH_VOLT_4_175 0x1B
#define PM2XXX_CH_VOLT_4_2 0x1C
#define PM2XXX_CH_VOLT_4_275 0x1F
#define PM2XXX_CH_VOLT_4_3 0x20
/*NTC control register 1*/
#define PM2XXX_BTEMP_HIGH_TH_45 0x0
#define PM2XXX_BTEMP_HIGH_TH_50 0x1
#define PM2XXX_BTEMP_HIGH_TH_55 0x2
#define PM2XXX_BTEMP_HIGH_TH_60 0x3
#define PM2XXX_BTEMP_HIGH_TH_65 0x4
#define PM2XXX_BTEMP_LOW_TH_N5 (0x0<<3)
#define PM2XXX_BTEMP_LOW_TH_0 (0x1<<3)
#define PM2XXX_BTEMP_LOW_TH_5 (0x2<<3)
#define PM2XXX_BTEMP_LOW_TH_10 (0x3<<3)
/*NTC control register 2*/
#define PM2XXX_NTC_BETA_COEFF_3477 0x0
#define PM2XXX_NTC_BETA_COEFF_3964 0x1
#define PM2XXX_NTC_RES_10K (0x0<<2)
#define PM2XXX_NTC_RES_47K (0x1<<2)
#define PM2XXX_NTC_RES_100K (0x2<<2)
#define PM2XXX_NTC_RES_NO_NTC (0x3<<2)
/* control Reg 9 */
#define PM2XXX_CH_CC_MODEDROP_EN 1
#define PM2XXX_CH_CC_MODEDROP_DIS 0
#define PM2XXX_CH_CC_REDUCED_CURRENT_100MA (0x0<<1)
#define PM2XXX_CH_CC_REDUCED_CURRENT_200MA (0x1<<1)
#define PM2XXX_CH_CC_REDUCED_CURRENT_400MA (0x2<<1)
#define PM2XXX_CH_CC_REDUCED_CURRENT_IDENT (0x3<<1)
#define PM2XXX_CHARCHING_INFO_DIS (0<<3)
#define PM2XXX_CHARCHING_INFO_EN (1<<3)
#define PM2XXX_CH_150MV_DROP_300MV (0<<4)
#define PM2XXX_CH_150MV_DROP_150MV (1<<4)
/* charger status register */
#define PM2XXX_CHG_STATUS_OFF 0x0
#define PM2XXX_CHG_STATUS_ON 0x1
#define PM2XXX_CHG_STATUS_FULL 0x2
#define PM2XXX_CHG_STATUS_ERR 0x3
#define PM2XXX_CHG_STATUS_WAIT 0x4
#define PM2XXX_CHG_STATUS_NOBAT 0x5
/* Input charger voltage VPWR2 */
#define PM2XXX_VPWR2_OVV_6_0 0x0
#define PM2XXX_VPWR2_OVV_6_3 0x1
#define PM2XXX_VPWR2_OVV_10 0x2
#define PM2XXX_VPWR2_OVV_NONE 0x3
/* Input charger drop VPWR2 */
#define PM2XXX_VPWR2_HW_OPT_EN (0x1<<4)
#define PM2XXX_VPWR2_HW_OPT_DIS (0x0<<4)
#define PM2XXX_VPWR2_VALID_EN (0x1<<3)
#define PM2XXX_VPWR2_VALID_DIS (0x0<<3)
#define PM2XXX_VPWR2_DROP_EN (0x1<<2)
#define PM2XXX_VPWR2_DROP_DIS (0x0<<2)
/* Input charger voltage VPWR1 */
#define PM2XXX_VPWR1_OVV_6_0 0x0
#define PM2XXX_VPWR1_OVV_6_3 0x1
#define PM2XXX_VPWR1_OVV_10 0x2
#define PM2XXX_VPWR1_OVV_NONE 0x3
/* Input charger drop VPWR1 */
#define PM2XXX_VPWR1_HW_OPT_EN (0x1<<4)
#define PM2XXX_VPWR1_HW_OPT_DIS (0x0<<4)
#define PM2XXX_VPWR1_VALID_EN (0x1<<3)
#define PM2XXX_VPWR1_VALID_DIS (0x0<<3)
#define PM2XXX_VPWR1_DROP_EN (0x1<<2)
#define PM2XXX_VPWR1_DROP_DIS (0x0<<2)
/* Battery low level comparator control register */
#define PM2XXX_VBAT_LOW_MONITORING_DIS 0x0
#define PM2XXX_VBAT_LOW_MONITORING_ENA 0x1
/* Battery low level value control register */
#define PM2XXX_VBAT_LOW_LEVEL_2_3 0x0
#define PM2XXX_VBAT_LOW_LEVEL_2_4 0x1
#define PM2XXX_VBAT_LOW_LEVEL_2_5 0x2
#define PM2XXX_VBAT_LOW_LEVEL_2_6 0x3
#define PM2XXX_VBAT_LOW_LEVEL_2_7 0x4
#define PM2XXX_VBAT_LOW_LEVEL_2_8 0x5
#define PM2XXX_VBAT_LOW_LEVEL_2_9 0x6
#define PM2XXX_VBAT_LOW_LEVEL_3_0 0x7
#define PM2XXX_VBAT_LOW_LEVEL_3_1 0x8
#define PM2XXX_VBAT_LOW_LEVEL_3_2 0x9
#define PM2XXX_VBAT_LOW_LEVEL_3_3 0xA
#define PM2XXX_VBAT_LOW_LEVEL_3_4 0xB
#define PM2XXX_VBAT_LOW_LEVEL_3_5 0xC
#define PM2XXX_VBAT_LOW_LEVEL_3_6 0xD
#define PM2XXX_VBAT_LOW_LEVEL_3_7 0xE
#define PM2XXX_VBAT_LOW_LEVEL_3_8 0xF
#define PM2XXX_VBAT_LOW_LEVEL_3_9 0x10
#define PM2XXX_VBAT_LOW_LEVEL_4_0 0x11
#define PM2XXX_VBAT_LOW_LEVEL_4_1 0x12
#define PM2XXX_VBAT_LOW_LEVEL_4_2 0x13
/* SW CTRL */
#define PM2XXX_SWCTRL_HW 0x0
#define PM2XXX_SWCTRL_SW 0x1
/* LED Driver Control */
#define PM2XXX_LED_CURRENT_MASK 0x0C
#define PM2XXX_LED_CURRENT_2_5MA (0X0<<2)
#define PM2XXX_LED_CURRENT_1MA (0X1<<2)
#define PM2XXX_LED_CURRENT_5MA (0X2<<2)
#define PM2XXX_LED_CURRENT_10MA (0X3<<2)
#define PM2XXX_LED_SELECT_MASK 0x02
#define PM2XXX_LED_SELECT_EN (0X0<<1)
#define PM2XXX_LED_SELECT_DIS (0X1<<1)
#define PM2XXX_ANTI_OVERSHOOT_MASK 0x01
#define PM2XXX_ANTI_OVERSHOOT_DIS 0X0
#define PM2XXX_ANTI_OVERSHOOT_EN 0X1
enum pm2xxx_reg_int1 {
PM2XXX_INT1_ITVBATDISCONNECT = 0x02,
PM2XXX_INT1_ITVBATLOWR = 0x04,
PM2XXX_INT1_ITVBATLOWF = 0x08,
};
enum pm2xxx_mask_reg_int1 {
PM2XXX_INT1_M_ITVBATDISCONNECT = 0x02,
PM2XXX_INT1_M_ITVBATLOWR = 0x04,
PM2XXX_INT1_M_ITVBATLOWF = 0x08,
};
enum pm2xxx_source_reg_int1 {
PM2XXX_INT1_S_ITVBATDISCONNECT = 0x02,
PM2XXX_INT1_S_ITVBATLOWR = 0x04,
PM2XXX_INT1_S_ITVBATLOWF = 0x08,
};
enum pm2xxx_reg_int2 {
PM2XXX_INT2_ITVPWR2PLUG = 0x01,
PM2XXX_INT2_ITVPWR2UNPLUG = 0x02,
PM2XXX_INT2_ITVPWR1PLUG = 0x04,
PM2XXX_INT2_ITVPWR1UNPLUG = 0x08,
};
enum pm2xxx_mask_reg_int2 {
PM2XXX_INT2_M_ITVPWR2PLUG = 0x01,
PM2XXX_INT2_M_ITVPWR2UNPLUG = 0x02,
PM2XXX_INT2_M_ITVPWR1PLUG = 0x04,
PM2XXX_INT2_M_ITVPWR1UNPLUG = 0x08,
};
enum pm2xxx_source_reg_int2 {
PM2XXX_INT2_S_ITVPWR2PLUG = 0x03,
PM2XXX_INT2_S_ITVPWR1PLUG = 0x0c,
};
enum pm2xxx_reg_int3 {
PM2XXX_INT3_ITCHPRECHARGEWD = 0x01,
PM2XXX_INT3_ITCHCCWD = 0x02,
PM2XXX_INT3_ITCHCVWD = 0x04,
PM2XXX_INT3_ITAUTOTIMEOUTWD = 0x08,
};
enum pm2xxx_mask_reg_int3 {
PM2XXX_INT3_M_ITCHPRECHARGEWD = 0x01,
PM2XXX_INT3_M_ITCHCCWD = 0x02,
PM2XXX_INT3_M_ITCHCVWD = 0x04,
PM2XXX_INT3_M_ITAUTOTIMEOUTWD = 0x08,
};
enum pm2xxx_source_reg_int3 {
PM2XXX_INT3_S_ITCHPRECHARGEWD = 0x01,
PM2XXX_INT3_S_ITCHCCWD = 0x02,
PM2XXX_INT3_S_ITCHCVWD = 0x04,
PM2XXX_INT3_S_ITAUTOTIMEOUTWD = 0x08,
};
enum pm2xxx_reg_int4 {
PM2XXX_INT4_ITBATTEMPCOLD = 0x01,
PM2XXX_INT4_ITBATTEMPHOT = 0x02,
PM2XXX_INT4_ITVPWR2OVV = 0x04,
PM2XXX_INT4_ITVPWR1OVV = 0x08,
PM2XXX_INT4_ITCHARGINGON = 0x10,
PM2XXX_INT4_ITVRESUME = 0x20,
PM2XXX_INT4_ITBATTFULL = 0x40,
PM2XXX_INT4_ITCVPHASE = 0x80,
};
enum pm2xxx_mask_reg_int4 {
PM2XXX_INT4_M_ITBATTEMPCOLD = 0x01,
PM2XXX_INT4_M_ITBATTEMPHOT = 0x02,
PM2XXX_INT4_M_ITVPWR2OVV = 0x04,
PM2XXX_INT4_M_ITVPWR1OVV = 0x08,
PM2XXX_INT4_M_ITCHARGINGON = 0x10,
PM2XXX_INT4_M_ITVRESUME = 0x20,
PM2XXX_INT4_M_ITBATTFULL = 0x40,
PM2XXX_INT4_M_ITCVPHASE = 0x80,
};
enum pm2xxx_source_reg_int4 {
PM2XXX_INT4_S_ITBATTEMPCOLD = 0x01,
PM2XXX_INT4_S_ITBATTEMPHOT = 0x02,
PM2XXX_INT4_S_ITVPWR2OVV = 0x04,
PM2XXX_INT4_S_ITVPWR1OVV = 0x08,
PM2XXX_INT4_S_ITCHARGINGON = 0x10,
PM2XXX_INT4_S_ITVRESUME = 0x20,
PM2XXX_INT4_S_ITBATTFULL = 0x40,
PM2XXX_INT4_S_ITCVPHASE = 0x80,
};
enum pm2xxx_reg_int5 {
PM2XXX_INT5_ITTHERMALSHUTDOWNRISE = 0x01,
PM2XXX_INT5_ITTHERMALSHUTDOWNFALL = 0x02,
PM2XXX_INT5_ITTHERMALWARNINGRISE = 0x04,
PM2XXX_INT5_ITTHERMALWARNINGFALL = 0x08,
PM2XXX_INT5_ITVSYSTEMOVV = 0x10,
};
enum pm2xxx_mask_reg_int5 {
PM2XXX_INT5_M_ITTHERMALSHUTDOWNRISE = 0x01,
PM2XXX_INT5_M_ITTHERMALSHUTDOWNFALL = 0x02,
PM2XXX_INT5_M_ITTHERMALWARNINGRISE = 0x04,
PM2XXX_INT5_M_ITTHERMALWARNINGFALL = 0x08,
PM2XXX_INT5_M_ITVSYSTEMOVV = 0x10,
};
enum pm2xxx_source_reg_int5 {
PM2XXX_INT5_S_ITTHERMALSHUTDOWNRISE = 0x01,
PM2XXX_INT5_S_ITTHERMALSHUTDOWNFALL = 0x02,
PM2XXX_INT5_S_ITTHERMALWARNINGRISE = 0x04,
PM2XXX_INT5_S_ITTHERMALWARNINGFALL = 0x08,
PM2XXX_INT5_S_ITVSYSTEMOVV = 0x10,
};
enum pm2xxx_reg_int6 {
PM2XXX_INT6_ITVPWR2DROP = 0x01,
PM2XXX_INT6_ITVPWR1DROP = 0x02,
PM2XXX_INT6_ITVPWR2VALIDRISE = 0x04,
PM2XXX_INT6_ITVPWR2VALIDFALL = 0x08,
PM2XXX_INT6_ITVPWR1VALIDRISE = 0x10,
PM2XXX_INT6_ITVPWR1VALIDFALL = 0x20,
};
enum pm2xxx_mask_reg_int6 {
PM2XXX_INT6_M_ITVPWR2DROP = 0x01,
PM2XXX_INT6_M_ITVPWR1DROP = 0x02,
PM2XXX_INT6_M_ITVPWR2VALIDRISE = 0x04,
PM2XXX_INT6_M_ITVPWR2VALIDFALL = 0x08,
PM2XXX_INT6_M_ITVPWR1VALIDRISE = 0x10,
PM2XXX_INT6_M_ITVPWR1VALIDFALL = 0x20,
};
enum pm2xxx_source_reg_int6 {
PM2XXX_INT6_S_ITVPWR2DROP = 0x01,
PM2XXX_INT6_S_ITVPWR1DROP = 0x02,
PM2XXX_INT6_S_ITVPWR2VALIDRISE = 0x04,
PM2XXX_INT6_S_ITVPWR2VALIDFALL = 0x08,
PM2XXX_INT6_S_ITVPWR1VALIDRISE = 0x10,
PM2XXX_INT6_S_ITVPWR1VALIDFALL = 0x20,
};
struct pm2xxx_charger_info {
int charger_connected;
int charger_online;
int cv_active;
bool wd_expired;
};
struct pm2xxx_charger_event_flags {
bool mainextchnotok;
bool main_thermal_prot;
bool ovv;
bool chgwdexp;
};
struct pm2xxx_interrupts {
u8 reg[PM2XXX_NUM_INT_REG];
int (*handler[PM2XXX_NUM_INT_REG])(void *, int);
};
struct pm2xxx_config {
struct i2c_client *pm2xxx_i2c;
struct i2c_device_id *pm2xxx_id;
};
struct pm2xxx_irq {
char *name;
irqreturn_t (*isr)(int irq, void *data);
};
struct pm2xxx_charger {
struct device *dev;
u8 chip_id;
bool vddadc_en_ac;
struct pm2xxx_config config;
bool ac_conn;
unsigned int gpio_irq;
int vbat;
int old_vbat;
int failure_case;
int failure_input_ovv;
unsigned int lpn_pin;
struct pm2xxx_interrupts *pm2_int;
struct regulator *regu;
struct pm2xxx_bm_data *bat;
struct mutex lock;
struct ab8500 *parent;
struct pm2xxx_charger_info ac;
struct pm2xxx_charger_platform_data *pdata;
struct workqueue_struct *charger_wq;
struct delayed_work check_vbat_work;
struct work_struct ac_work;
struct work_struct check_main_thermal_prot_work;
struct delayed_work check_hw_failure_work;
struct ux500_charger ac_chg;
struct power_supply_desc ac_chg_desc;
struct pm2xxx_charger_event_flags flags;
};
#endif /* PM2301_CHARGER_H */

4
drivers/power/supply/power_supply_core.c
View File

@ -263,13 +263,13 @@ static int power_supply_check_supplies(struct power_supply *psy)
return 0;
/* All supplies found, allocate char ** array for filling */
psy->supplied_from = devm_kzalloc(&psy->dev, sizeof(psy->supplied_from),
psy->supplied_from = devm_kzalloc(&psy->dev, sizeof(*psy->supplied_from),
GFP_KERNEL);
if (!psy->supplied_from)
return -ENOMEM;
*psy->supplied_from = devm_kcalloc(&psy->dev,
cnt - 1, sizeof(char *),
cnt - 1, sizeof(**psy->supplied_from),
GFP_KERNEL);
if (!*psy->supplied_from)
return -ENOMEM;

10
include/dt-bindings/reset/sama7g5-reset.h Normal file
View File

@ -0,0 +1,10 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
#ifndef __DT_BINDINGS_RESET_SAMA7G5_H
#define __DT_BINDINGS_RESET_SAMA7G5_H
#define SAMA7G5_RESET_USB_PHY1 4
#define SAMA7G5_RESET_USB_PHY2 5
#define SAMA7G5_RESET_USB_PHY3 6
#endif /* __DT_BINDINGS_RESET_SAMA7G5_H */