iop-adma: P+Q self test
Even though the intent is to extend dmatest with P+Q tests there is still value in having an always-on sanity check to prevent an unintentionally broken driver from registering. This depends on raid6_pq.ko for verification, the side effect being that PQ capable channels will fail to register when raid6 is disabled. Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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7bf649aee8
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f6dbf65161
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@ -31,6 +31,7 @@
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#include <linux/platform_device.h>
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#include <linux/memory.h>
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#include <linux/ioport.h>
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#include <linux/raid/pq.h>
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#include <mach/adma.h>
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@ -1267,6 +1268,170 @@ out:
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return err;
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}
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#ifdef CONFIG_MD_RAID6_PQ
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static int __devinit
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iop_adma_pq_zero_sum_self_test(struct iop_adma_device *device)
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{
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/* combined sources, software pq results, and extra hw pq results */
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struct page *pq[IOP_ADMA_NUM_SRC_TEST+2+2];
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/* ptr to the extra hw pq buffers defined above */
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struct page **pq_hw = &pq[IOP_ADMA_NUM_SRC_TEST+2];
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/* address conversion buffers (dma_map / page_address) */
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void *pq_sw[IOP_ADMA_NUM_SRC_TEST+2];
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dma_addr_t pq_src[IOP_ADMA_NUM_SRC_TEST];
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dma_addr_t pq_dest[2];
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int i;
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struct dma_async_tx_descriptor *tx;
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struct dma_chan *dma_chan;
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dma_cookie_t cookie;
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u32 zero_sum_result;
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int err = 0;
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struct device *dev;
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dev_dbg(device->common.dev, "%s\n", __func__);
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for (i = 0; i < ARRAY_SIZE(pq); i++) {
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pq[i] = alloc_page(GFP_KERNEL);
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if (!pq[i]) {
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while (i--)
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__free_page(pq[i]);
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return -ENOMEM;
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}
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}
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/* Fill in src buffers */
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for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) {
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pq_sw[i] = page_address(pq[i]);
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memset(pq_sw[i], 0x11111111 * (1<<i), PAGE_SIZE);
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}
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pq_sw[i] = page_address(pq[i]);
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pq_sw[i+1] = page_address(pq[i+1]);
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dma_chan = container_of(device->common.channels.next,
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struct dma_chan,
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device_node);
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if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
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err = -ENODEV;
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goto out;
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}
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dev = dma_chan->device->dev;
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/* initialize the dests */
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memset(page_address(pq_hw[0]), 0 , PAGE_SIZE);
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memset(page_address(pq_hw[1]), 0 , PAGE_SIZE);
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/* test pq */
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pq_dest[0] = dma_map_page(dev, pq_hw[0], 0, PAGE_SIZE, DMA_FROM_DEVICE);
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pq_dest[1] = dma_map_page(dev, pq_hw[1], 0, PAGE_SIZE, DMA_FROM_DEVICE);
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for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
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pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE,
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DMA_TO_DEVICE);
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tx = iop_adma_prep_dma_pq(dma_chan, pq_dest, pq_src,
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IOP_ADMA_NUM_SRC_TEST, (u8 *)raid6_gfexp,
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PAGE_SIZE,
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DMA_PREP_INTERRUPT |
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DMA_CTRL_ACK);
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cookie = iop_adma_tx_submit(tx);
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iop_adma_issue_pending(dma_chan);
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msleep(8);
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if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
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DMA_SUCCESS) {
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dev_err(dev, "Self-test pq timed out, disabling\n");
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err = -ENODEV;
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goto free_resources;
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}
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raid6_call.gen_syndrome(IOP_ADMA_NUM_SRC_TEST+2, PAGE_SIZE, pq_sw);
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if (memcmp(pq_sw[IOP_ADMA_NUM_SRC_TEST],
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page_address(pq_hw[0]), PAGE_SIZE) != 0) {
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dev_err(dev, "Self-test p failed compare, disabling\n");
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err = -ENODEV;
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goto free_resources;
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}
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if (memcmp(pq_sw[IOP_ADMA_NUM_SRC_TEST+1],
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page_address(pq_hw[1]), PAGE_SIZE) != 0) {
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dev_err(dev, "Self-test q failed compare, disabling\n");
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err = -ENODEV;
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goto free_resources;
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}
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/* test correct zero sum using the software generated pq values */
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for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 2; i++)
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pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE,
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DMA_TO_DEVICE);
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zero_sum_result = ~0;
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tx = iop_adma_prep_dma_pq_val(dma_chan, &pq_src[IOP_ADMA_NUM_SRC_TEST],
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pq_src, IOP_ADMA_NUM_SRC_TEST,
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raid6_gfexp, PAGE_SIZE, &zero_sum_result,
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DMA_PREP_INTERRUPT|DMA_CTRL_ACK);
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cookie = iop_adma_tx_submit(tx);
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iop_adma_issue_pending(dma_chan);
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msleep(8);
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if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
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DMA_SUCCESS) {
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dev_err(dev, "Self-test pq-zero-sum timed out, disabling\n");
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err = -ENODEV;
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goto free_resources;
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}
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if (zero_sum_result != 0) {
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dev_err(dev, "Self-test pq-zero-sum failed to validate: %x\n",
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zero_sum_result);
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err = -ENODEV;
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goto free_resources;
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}
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/* test incorrect zero sum */
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i = IOP_ADMA_NUM_SRC_TEST;
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memset(pq_sw[i] + 100, 0, 100);
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memset(pq_sw[i+1] + 200, 0, 200);
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for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 2; i++)
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pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE,
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DMA_TO_DEVICE);
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zero_sum_result = 0;
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tx = iop_adma_prep_dma_pq_val(dma_chan, &pq_src[IOP_ADMA_NUM_SRC_TEST],
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pq_src, IOP_ADMA_NUM_SRC_TEST,
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raid6_gfexp, PAGE_SIZE, &zero_sum_result,
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DMA_PREP_INTERRUPT|DMA_CTRL_ACK);
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cookie = iop_adma_tx_submit(tx);
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iop_adma_issue_pending(dma_chan);
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msleep(8);
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if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
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DMA_SUCCESS) {
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dev_err(dev, "Self-test !pq-zero-sum timed out, disabling\n");
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err = -ENODEV;
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goto free_resources;
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}
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if (zero_sum_result != (SUM_CHECK_P_RESULT | SUM_CHECK_Q_RESULT)) {
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dev_err(dev, "Self-test !pq-zero-sum failed to validate: %x\n",
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zero_sum_result);
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err = -ENODEV;
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goto free_resources;
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}
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free_resources:
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iop_adma_free_chan_resources(dma_chan);
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out:
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i = ARRAY_SIZE(pq);
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while (i--)
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__free_page(pq[i]);
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return err;
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}
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#endif
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static int __devexit iop_adma_remove(struct platform_device *dev)
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{
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struct iop_adma_device *device = platform_get_drvdata(dev);
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@ -1417,13 +1582,28 @@ static int __devinit iop_adma_probe(struct platform_device *pdev)
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}
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if (dma_has_cap(DMA_XOR, dma_dev->cap_mask) ||
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dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
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dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
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ret = iop_adma_xor_val_self_test(adev);
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dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
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if (ret)
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goto err_free_iop_chan;
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}
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if (dma_has_cap(DMA_PQ, dma_dev->cap_mask) &&
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dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask)) {
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#ifdef CONFIG_MD_RAID6_PQ
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ret = iop_adma_pq_zero_sum_self_test(adev);
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dev_dbg(&pdev->dev, "pq self test returned %d\n", ret);
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#else
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/* can not test raid6, so do not publish capability */
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dma_cap_clear(DMA_PQ, dma_dev->cap_mask);
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dma_cap_clear(DMA_PQ_VAL, dma_dev->cap_mask);
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ret = 0;
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#endif
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if (ret)
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goto err_free_iop_chan;
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}
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dev_printk(KERN_INFO, &pdev->dev, "Intel(R) IOP: "
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"( %s%s%s%s%s%s%s%s%s%s)\n",
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dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "pq " : "",
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