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clk: tegra: Remove CLK_IS_ROOT 

This flag is a no-op now. Remove usage of the flag.

Acked-by: Rhyland Klein <rklein@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Stephen Boyd 2016-03-01 11:00:02 -08:00
parent afb4bdc9d8
commit f6da46a307
5 changed files with 8 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/clk/tegra/clk-audio-sync.c
View File

@ -72,7 +72,7 @@ struct clk *tegra_clk_register_sync_source(const char *name,
init.ops = &tegra_clk_sync_source_ops;
init.name = name;
init.flags = CLK_IS_ROOT;
init.flags = 0;
init.parent_names = NULL;
init.num_parents = 0;

1
drivers/clk/tegra/clk-dfll.c
View File

@ -995,7 +995,6 @@ static const struct clk_ops dfll_clk_ops = {
};
static struct clk_init_data dfll_clk_init_data = {
.flags = CLK_IS_ROOT,
.ops = &dfll_clk_ops,
.num_parents = 0,
};

6
drivers/clk/tegra/clk-tegra-fixed.c
View File

@ -52,8 +52,7 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
return -EINVAL;
}
osc = clk_register_fixed_rate(NULL, "osc", NULL, CLK_IS_ROOT,
*osc_freq);
osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq);
dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);
if (!dt_clk)
@ -88,8 +87,7 @@ void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
/* clk_32k */
dt_clk = tegra_lookup_dt_id(tegra_clk_clk_32k, tegra_clks);
if (dt_clk) {
clk = clk_register_fixed_rate(NULL, "clk_32k", NULL,
CLK_IS_ROOT, 32768);
clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
*dt_clk = clk;
}

3
drivers/clk/tegra/clk-tegra114.c
View File

@ -972,8 +972,7 @@ static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
struct clk *clk;
/* clk_32k */
clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
32768);
clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
clks[TEGRA114_CLK_CLK_32K] = clk;
/* clk_m_div2 */

10
drivers/clk/tegra/clk-tegra20.c
View File

@ -837,15 +837,13 @@ static void __init tegra20_periph_clk_init(void)
clks[TEGRA20_CLK_PEX] = clk;
/* cdev1 */
clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT,
26000000);
clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, 0, 26000000);
clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0,
clk_base, 0, 94, periph_clk_enb_refcnt);
clks[TEGRA20_CLK_CDEV1] = clk;
/* cdev2 */
clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT,
26000000);
clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, 0, 26000000);
clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0,
clk_base, 0, 93, periph_clk_enb_refcnt);
clks[TEGRA20_CLK_CDEV2] = clk;
@ -879,8 +877,8 @@ static void __init tegra20_osc_clk_init(void)
input_freq = tegra20_clk_measure_input_freq();
/* clk_m */
clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT |
CLK_IGNORE_UNUSED, input_freq);
clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IGNORE_UNUSED,
input_freq);
clks[TEGRA20_CLK_CLK_M] = clk;
/* pll_ref */