dmfe: trivial/spelling fixes
Fix a typo, wrap lines on 80-th column, change KERN_ERR to KERN_INFO for link status message Signed-off-by: Maxim Levitsky <maximlevitsky@gmail.com> Cc: Valerie Henson <val_henson@linux.intel.com> Cc: Jeff Garzik <jeff@garzik.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Maxim Levitsky
Jeff Garzik
parent
ead9bffb15
commit
f67ba792fa
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@ -143,9 +143,16 @@
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#define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
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#define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
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#define DMFE_DBUG(dbug_now, msg, value) if (dmfe_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
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#define DMFE_DBUG(dbug_now, msg, value) \
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do { \
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if (dmfe_debug || (dbug_now)) \
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printk(KERN_ERR DRV_NAME ": %s %lx\n",\
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(msg), (long) (value)); \
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} while (0)
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#define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
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#define SHOW_MEDIA_TYPE(mode) \
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printk (KERN_INFO DRV_NAME ": Change Speed to %sMhz %s duplex\n" , \
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(mode & 1) ? "100":"10", (mode & 4) ? "full":"half");
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/* CR9 definition: SROM/MII */
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@ -163,10 +170,20 @@
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#define SROM_V41_CODE 0x14
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#define SROM_CLK_WRITE(data, ioaddr) outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);
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#define SROM_CLK_WRITE(data, ioaddr) \
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outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
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udelay(5); \
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outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
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udelay(5); \
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outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
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udelay(5);
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#define __CHK_IO_SIZE(pci_id, dev_rev) ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE
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#define CHK_IO_SIZE(pci_dev, dev_rev) __CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev)
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#define __CHK_IO_SIZE(pci_id, dev_rev) \
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(( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? \
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DM9102A_IO_SIZE: DM9102_IO_SIZE)
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#define CHK_IO_SIZE(pci_dev, dev_rev) \
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(__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev))
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/* Sten Check */
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#define DEVICE net_device
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@ -329,7 +346,7 @@ static void dmfe_program_DM9802(struct dmfe_board_info *);
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static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
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static void dmfe_set_phyxcer(struct dmfe_board_info *);
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/* DM910X network baord routine ---------------------------- */
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/* DM910X network board routine ---------------------------- */
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/*
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* Search DM910X board ,allocate space and register it
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@ -356,7 +373,8 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
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SET_NETDEV_DEV(dev, &pdev->dev);
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if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
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printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n");
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printk(KERN_WARNING DRV_NAME
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": 32-bit PCI DMA not available.\n");
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err = -ENODEV;
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goto err_out_free;
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}
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@ -400,8 +418,11 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
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db = netdev_priv(dev);
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/* Allocate Tx/Rx descriptor memory */
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db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
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db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
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db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) *
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DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
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db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC *
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TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
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db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
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db->first_tx_desc_dma = db->desc_pool_dma_ptr;
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@ -437,7 +458,8 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
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/* read 64 word srom data */
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for (i = 0; i < 64; i++)
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((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
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((u16 *) db->srom)[i] =
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cpu_to_le16(read_srom_word(db->ioaddr, i));
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/* Set Node address */
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for (i = 0; i < 6; i++)
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@ -506,7 +528,8 @@ static int dmfe_open(struct DEVICE *dev)
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DMFE_DBUG(0, "dmfe_open", 0);
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ret = request_irq(dev->irq, &dmfe_interrupt, IRQF_SHARED, dev->name, dev);
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ret = request_irq(dev->irq, &dmfe_interrupt,
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IRQF_SHARED, dev->name, dev);
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if (ret)
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return ret;
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@ -647,7 +670,8 @@ static int dmfe_start_xmit(struct sk_buff *skb, struct DEVICE *dev)
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/* No Tx resource check, it never happen nromally */
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if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
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spin_unlock_irqrestore(&db->lock, flags);
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printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_queue_cnt);
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printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n",
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db->tx_queue_cnt);
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return 1;
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}
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@ -719,7 +743,8 @@ static int dmfe_stop(struct DEVICE *dev)
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#if 0
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/* show statistic counter */
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printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
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printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx"
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" LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
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db->tx_fifo_underrun, db->tx_excessive_collision,
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db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
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db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
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@ -916,7 +941,9 @@ static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
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db->rx_avail_cnt--;
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db->interval_rx_cnt++;
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pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
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pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2),
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RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
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if ( (rdes0 & 0x300) != 0x300) {
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/* A packet without First/Last flag */
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/* reuse this SKB */
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@ -1074,7 +1101,8 @@ static void dmfe_timer(unsigned long data)
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if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
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db->cr6_data &= ~0x40000;
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update_cr6(db->cr6_data, db->ioaddr);
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phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
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phy_write(db->ioaddr,
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db->phy_addr, 0, 0x1000, db->chip_id);
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db->cr6_data |= 0x40000;
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update_cr6(db->cr6_data, db->ioaddr);
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db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
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@ -1148,7 +1176,8 @@ static void dmfe_timer(unsigned long data)
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/* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
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/* AUTO or force 1M Homerun/Longrun don't need */
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if ( !(db->media_mode & 0x38) )
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phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
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phy_write(db->ioaddr, db->phy_addr,
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0, 0x1000, db->chip_id);
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/* AUTO mode, if INT phyxcer link failed, select EXT device */
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if (db->media_mode & DMFE_AUTO) {
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@ -1252,7 +1281,8 @@ static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
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if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
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rxptr->rx_skb_ptr = skb;
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rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
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rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev,
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skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
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wmb();
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rxptr->rdes0 = cpu_to_le32(0x80000000);
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db->rx_avail_cnt++;
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@ -1284,8 +1314,11 @@ static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioadd
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outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
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/* rx descriptor start pointer */
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db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
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db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
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db->first_rx_desc = (void *)db->first_tx_desc +
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sizeof(struct tx_desc) * TX_DESC_CNT;
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db->first_rx_desc_dma = db->first_tx_desc_dma +
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sizeof(struct tx_desc) * TX_DESC_CNT;
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db->rx_insert_ptr = db->first_rx_desc;
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db->rx_ready_ptr = db->first_rx_desc;
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outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
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@ -1463,7 +1496,8 @@ static void allocate_rx_buffer(struct dmfe_board_info *db)
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if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
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break;
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rxptr->rx_skb_ptr = skb; /* FIXME (?) */
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rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
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rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data,
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RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
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wmb();
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rxptr->rdes0 = cpu_to_le32(0x80000000);
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rxptr = rxptr->next_rx_desc;
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@ -1503,7 +1537,8 @@ static u16 read_srom_word(long ioaddr, int offset)
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for (i = 16; i > 0; i--) {
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outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
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udelay(5);
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srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
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srom_data = (srom_data << 1) |
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((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
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outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
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udelay(5);
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}
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@ -1530,9 +1565,11 @@ static u8 dmfe_sense_speed(struct dmfe_board_info * db)
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if ( (phy_mode & 0x24) == 0x24 ) {
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if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
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phy_mode = phy_read(db->ioaddr, db->phy_addr, 7, db->chip_id) & 0xf000;
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phy_mode = phy_read(db->ioaddr,
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db->phy_addr, 7, db->chip_id) & 0xf000;
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else /* DM9102/DM9102A */
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phy_mode = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0xf000;
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phy_mode = phy_read(db->ioaddr,
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db->phy_addr, 17, db->chip_id) & 0xf000;
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/* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
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switch (phy_mode) {
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case 0x1000: db->op_mode = DMFE_10MHF; break;
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@ -1569,8 +1606,11 @@ static void dmfe_set_phyxcer(struct dmfe_board_info *db)
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/* DM9009 Chip: Phyxcer reg18 bit12=0 */
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if (db->chip_id == PCI_DM9009_ID) {
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phy_reg = phy_read(db->ioaddr, db->phy_addr, 18, db->chip_id) & ~0x1000;
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phy_write(db->ioaddr, db->phy_addr, 18, phy_reg, db->chip_id);
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phy_reg = phy_read(db->ioaddr,
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db->phy_addr, 18, db->chip_id) & ~0x1000;
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phy_write(db->ioaddr,
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db->phy_addr, 18, phy_reg, db->chip_id);
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}
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/* Phyxcer capability setting */
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@ -1643,10 +1683,12 @@ static void dmfe_process_mode(struct dmfe_board_info *db)
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case DMFE_100MHF: phy_reg = 0x2000; break;
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case DMFE_100MFD: phy_reg = 0x2100; break;
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}
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phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
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phy_write(db->ioaddr,
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db->phy_addr, 0, phy_reg, db->chip_id);
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if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
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mdelay(20);
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phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
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phy_write(db->ioaddr,
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db->phy_addr, 0, phy_reg, db->chip_id);
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}
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}
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}
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@ -1656,7 +1698,8 @@ static void dmfe_process_mode(struct dmfe_board_info *db)
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* Write a word to Phy register
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*/
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static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
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static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
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u16 phy_data, u32 chip_id)
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{
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u16 i;
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unsigned long ioaddr;
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@ -1682,11 +1725,13 @@ static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data
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/* Send Phy address */
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for (i = 0x10; i > 0; i = i >> 1)
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phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
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phy_write_1bit(ioaddr,
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phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
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/* Send register address */
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for (i = 0x10; i > 0; i = i >> 1)
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phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
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phy_write_1bit(ioaddr,
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offset & i ? PHY_DATA_1 : PHY_DATA_0);
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/* written trasnition */
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phy_write_1bit(ioaddr, PHY_DATA_1);
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@ -1694,7 +1739,8 @@ static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data
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/* Write a word data to PHY controller */
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for ( i = 0x8000; i > 0; i >>= 1)
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phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
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phy_write_1bit(ioaddr,
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phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
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}
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}
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@ -1731,11 +1777,13 @@ static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
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/* Send Phy address */
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for (i = 0x10; i > 0; i = i >> 1)
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phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
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phy_write_1bit(ioaddr,
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phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
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/* Send register address */
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for (i = 0x10; i > 0; i = i >> 1)
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phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
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phy_write_1bit(ioaddr,
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offset & i ? PHY_DATA_1 : PHY_DATA_0);
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/* Skip transition state */
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phy_read_1bit(ioaddr);
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@ -1956,7 +2004,8 @@ static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
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/* Check remote device status match our setting ot not */
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if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
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phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
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phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
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db->chip_id);
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db->HPNA_timer=8;
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} else
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db->HPNA_timer=600; /* Match, every 10 minutes, check */
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@ -1996,8 +2045,11 @@ module_param(HPNA_tx_cmd, byte, 0);
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module_param(HPNA_NoiseFloor, byte, 0);
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module_param(SF_mode, byte, 0);
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MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
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MODULE_PARM_DESC(mode, "Davicom DM9xxx: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
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MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function (bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
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MODULE_PARM_DESC(mode, "Davicom DM9xxx: "
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"Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
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MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function "
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"(bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
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/* Description:
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* when user used insmod to add module, system invoked init_module()
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