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Merge branch 'next-samsung-irq_data' into for-next

This commit is contained in:
Kukjin Kim 2011-01-03 19:20:21 +09:00
parent c6906c3e29 04ea1cc8ab
commit f651ef6575
16 changed files with 345 additions and 354 deletions
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22
arch/arm/mach-s3c2410/bast-irq.c
View File

@ -75,38 +75,38 @@ static unsigned char bast_pc104_irqmasks[] = {
static unsigned char bast_pc104_irqs[] = { 3, 5, 7, 10 };
static void
bast_pc104_mask(unsigned int irqno)
bast_pc104_mask(struct irq_data *data)
{
unsigned long temp;
temp = __raw_readb(BAST_VA_PC104_IRQMASK);
temp &= ~bast_pc104_irqmasks[irqno];
temp &= ~bast_pc104_irqmasks[data->irq];
__raw_writeb(temp, BAST_VA_PC104_IRQMASK);
}
static void
bast_pc104_maskack(unsigned int irqno)
bast_pc104_maskack(struct irq_data *data)
{
struct irq_desc *desc = irq_desc + IRQ_ISA;
bast_pc104_mask(irqno);
desc->chip->ack(IRQ_ISA);
bast_pc104_mask(data);
desc->irq_data.chip->irq_ack(&desc->irq_data);
}
static void
bast_pc104_unmask(unsigned int irqno)
bast_pc104_unmask(struct irq_data *data)
{
unsigned long temp;
temp = __raw_readb(BAST_VA_PC104_IRQMASK);
temp |= bast_pc104_irqmasks[irqno];
temp |= bast_pc104_irqmasks[data->irq];
__raw_writeb(temp, BAST_VA_PC104_IRQMASK);
}
static struct irq_chip bast_pc104_chip = {
.mask = bast_pc104_mask,
.unmask = bast_pc104_unmask,
.ack = bast_pc104_maskack
.irq_mask = bast_pc104_mask,
.irq_unmask = bast_pc104_unmask,
.irq_ack = bast_pc104_maskack
};
static void
@ -123,7 +123,7 @@ bast_irq_pc104_demux(unsigned int irq,
/* ack if we get an irq with nothing (ie, startup) */
desc = irq_desc + IRQ_ISA;
desc->chip->ack(IRQ_ISA);
desc->irq_data.chip->irq_ack(&desc->irq_data);
} else {
/* handle the IRQ */

50
arch/arm/mach-s3c2412/irq.c
View File

@ -49,9 +49,9 @@
*/
static void
s3c2412_irq_mask(unsigned int irqno)
s3c2412_irq_mask(struct irq_data *data)
{
unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
unsigned long mask;
mask = __raw_readl(S3C2410_INTMSK);
@ -62,9 +62,9 @@ s3c2412_irq_mask(unsigned int irqno)
}
static inline void
s3c2412_irq_ack(unsigned int irqno)
s3c2412_irq_ack(struct irq_data *data)
{
unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
__raw_writel(bitval, S3C2412_EINTPEND);
__raw_writel(bitval, S3C2410_SRCPND);
@ -72,9 +72,9 @@ s3c2412_irq_ack(unsigned int irqno)
}
static inline void
s3c2412_irq_maskack(unsigned int irqno)
s3c2412_irq_maskack(struct irq_data *data)
{
unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
unsigned long mask;
mask = __raw_readl(S3C2410_INTMSK);
@ -89,9 +89,9 @@ s3c2412_irq_maskack(unsigned int irqno)
}
static void
s3c2412_irq_unmask(unsigned int irqno)
s3c2412_irq_unmask(struct irq_data *data)
{
unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
unsigned long mask;
mask = __raw_readl(S3C2412_EINTMASK);
@ -102,11 +102,11 @@ s3c2412_irq_unmask(unsigned int irqno)
}
static struct irq_chip s3c2412_irq_eint0t4 = {
.ack = s3c2412_irq_ack,
.mask = s3c2412_irq_mask,
.unmask = s3c2412_irq_unmask,
.set_wake = s3c_irq_wake,
.set_type = s3c_irqext_type,
.irq_ack = s3c2412_irq_ack,
.irq_mask = s3c2412_irq_mask,
.irq_unmask = s3c2412_irq_unmask,
.irq_set_wake = s3c_irq_wake,
.irq_set_type = s3c_irqext_type,
};
#define INTBIT(x) (1 << ((x) - S3C2410_IRQSUB(0)))
@ -132,29 +132,29 @@ static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc)
#define INTMSK_CFSDI (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0))
#define SUBMSK_CFSDI INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF)
static void s3c2412_irq_cfsdi_mask(unsigned int irqno)
static void s3c2412_irq_cfsdi_mask(struct irq_data *data)
{
s3c_irqsub_mask(irqno, INTMSK_CFSDI, SUBMSK_CFSDI);
s3c_irqsub_mask(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
}
static void s3c2412_irq_cfsdi_unmask(unsigned int irqno)
static void s3c2412_irq_cfsdi_unmask(struct irq_data *data)
{
s3c_irqsub_unmask(irqno, INTMSK_CFSDI);
s3c_irqsub_unmask(data->irq, INTMSK_CFSDI);
}
static void s3c2412_irq_cfsdi_ack(unsigned int irqno)
static void s3c2412_irq_cfsdi_ack(struct irq_data *data)
{
s3c_irqsub_maskack(irqno, INTMSK_CFSDI, SUBMSK_CFSDI);
s3c_irqsub_maskack(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
}
static struct irq_chip s3c2412_irq_cfsdi = {
.name = "s3c2412-cfsdi",
.ack = s3c2412_irq_cfsdi_ack,
.mask = s3c2412_irq_cfsdi_mask,
.unmask = s3c2412_irq_cfsdi_unmask,
.irq_ack = s3c2412_irq_cfsdi_ack,
.irq_mask = s3c2412_irq_cfsdi_mask,
.irq_unmask = s3c2412_irq_cfsdi_unmask,
};
static int s3c2412_irq_rtc_wake(unsigned int irqno, unsigned int state)
static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state)
{
unsigned long pwrcfg;
@ -165,7 +165,7 @@ static int s3c2412_irq_rtc_wake(unsigned int irqno, unsigned int state)
pwrcfg |= S3C2412_PWRCFG_RTC_MASKIRQ;
__raw_writel(pwrcfg, S3C2412_PWRCFG);
return s3c_irq_chip.set_wake(irqno, state);
return s3c_irq_chip.irq_set_wake(data, state);
}
static struct irq_chip s3c2412_irq_rtc_chip;
@ -193,7 +193,7 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
/* change RTC IRQ's set wake method */
s3c2412_irq_rtc_chip = s3c_irq_chip;
s3c2412_irq_rtc_chip.set_wake = s3c2412_irq_rtc_wake;
s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake;
set_irq_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);

76
arch/arm/mach-s3c2416/irq.c
View File

@ -77,28 +77,27 @@ static void s3c2416_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0))
#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
static void s3c2416_irq_wdtac97_mask(unsigned int irqno)
static void s3c2416_irq_wdtac97_mask(struct irq_data *data)
{
s3c_irqsub_mask(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97);
s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
}
static void s3c2416_irq_wdtac97_unmask(unsigned int irqno)
static void s3c2416_irq_wdtac97_unmask(struct irq_data *data)
{
s3c_irqsub_unmask(irqno, INTMSK_WDTAC97);
s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
}
static void s3c2416_irq_wdtac97_ack(unsigned int irqno)
static void s3c2416_irq_wdtac97_ack(struct irq_data *data)
{
s3c_irqsub_maskack(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97);
s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
}
static struct irq_chip s3c2416_irq_wdtac97 = {
.mask = s3c2416_irq_wdtac97_mask,
.unmask = s3c2416_irq_wdtac97_unmask,
.ack = s3c2416_irq_wdtac97_ack,
.irq_mask = s3c2416_irq_wdtac97_mask,
.irq_unmask = s3c2416_irq_wdtac97_unmask,
.irq_ack = s3c2416_irq_wdtac97_ack,
};
/* LCD sub interrupts */
static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
@ -109,28 +108,27 @@ static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0))
#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
static void s3c2416_irq_lcd_mask(unsigned int irqno)
static void s3c2416_irq_lcd_mask(struct irq_data *data)
{
s3c_irqsub_mask(irqno, INTMSK_LCD, SUBMSK_LCD);
s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
}
static void s3c2416_irq_lcd_unmask(unsigned int irqno)
static void s3c2416_irq_lcd_unmask(struct irq_data *data)
{
s3c_irqsub_unmask(irqno, INTMSK_LCD);
s3c_irqsub_unmask(data->irq, INTMSK_LCD);
}
static void s3c2416_irq_lcd_ack(unsigned int irqno)
static void s3c2416_irq_lcd_ack(struct irq_data *data)
{
s3c_irqsub_maskack(irqno, INTMSK_LCD, SUBMSK_LCD);
s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
}
static struct irq_chip s3c2416_irq_lcd = {
.mask = s3c2416_irq_lcd_mask,
.unmask = s3c2416_irq_lcd_unmask,
.ack = s3c2416_irq_lcd_ack,
.irq_mask = s3c2416_irq_lcd_mask,
.irq_unmask = s3c2416_irq_lcd_unmask,
.irq_ack = s3c2416_irq_lcd_ack,
};
/* DMA sub interrupts */
static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
@ -142,28 +140,27 @@ static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
static void s3c2416_irq_dma_mask(unsigned int irqno)
static void s3c2416_irq_dma_mask(struct irq_data *data)
{
s3c_irqsub_mask(irqno, INTMSK_DMA, SUBMSK_DMA);
s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
}
static void s3c2416_irq_dma_unmask(unsigned int irqno)
static void s3c2416_irq_dma_unmask(struct irq_data *data)
{
s3c_irqsub_unmask(irqno, INTMSK_DMA);
s3c_irqsub_unmask(data->irq, INTMSK_DMA);
}
static void s3c2416_irq_dma_ack(unsigned int irqno)
static void s3c2416_irq_dma_ack(struct irq_data *data)
{
s3c_irqsub_maskack(irqno, INTMSK_DMA, SUBMSK_DMA);
s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
}
static struct irq_chip s3c2416_irq_dma = {
.mask = s3c2416_irq_dma_mask,
.unmask = s3c2416_irq_dma_unmask,
.ack = s3c2416_irq_dma_ack,
.irq_mask = s3c2416_irq_dma_mask,
.irq_unmask = s3c2416_irq_dma_unmask,
.irq_ack = s3c2416_irq_dma_ack,
};
/* UART3 sub interrupts */
static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
@ -174,28 +171,27 @@ static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
#define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
static void s3c2416_irq_uart3_mask(unsigned int irqno)
static void s3c2416_irq_uart3_mask(struct irq_data *data)
{
s3c_irqsub_mask(irqno, INTMSK_UART3, SUBMSK_UART3);
s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
}
static void s3c2416_irq_uart3_unmask(unsigned int irqno)
static void s3c2416_irq_uart3_unmask(struct irq_data *data)
{
s3c_irqsub_unmask(irqno, INTMSK_UART3);
s3c_irqsub_unmask(data->irq, INTMSK_UART3);
}
static void s3c2416_irq_uart3_ack(unsigned int irqno)
static void s3c2416_irq_uart3_ack(struct irq_data *data)
{
s3c_irqsub_maskack(irqno, INTMSK_UART3, SUBMSK_UART3);
s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
}
static struct irq_chip s3c2416_irq_uart3 = {
.mask = s3c2416_irq_uart3_mask,
.unmask = s3c2416_irq_uart3_unmask,
.ack = s3c2416_irq_uart3_ack,
.irq_mask = s3c2416_irq_uart3_mask,
.irq_unmask = s3c2416_irq_uart3_unmask,
.irq_ack = s3c2416_irq_uart3_ack,
};
/* IRQ initialisation code */
static int __init s3c2416_add_sub(unsigned int base,

18
arch/arm/mach-s3c2440/irq.c
View File

@ -69,27 +69,27 @@ static void s3c_irq_demux_wdtac97(unsigned int irq,
#define INTMSK_WDT (1UL << (IRQ_WDT - IRQ_EINT0))
static void
s3c_irq_wdtac97_mask(unsigned int irqno)
s3c_irq_wdtac97_mask(struct irq_data *data)
{
s3c_irqsub_mask(irqno, INTMSK_WDT, 3<<13);
s3c_irqsub_mask(data->irq, INTMSK_WDT, 3 << 13);
}
static void
s3c_irq_wdtac97_unmask(unsigned int irqno)
s3c_irq_wdtac97_unmask(struct irq_data *data)
{
s3c_irqsub_unmask(irqno, INTMSK_WDT);
s3c_irqsub_unmask(data->irq, INTMSK_WDT);
}
static void
s3c_irq_wdtac97_ack(unsigned int irqno)
s3c_irq_wdtac97_ack(struct irq_data *data)
{
s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13);
s3c_irqsub_maskack(data->irq, INTMSK_WDT, 3 << 13);
}
static struct irq_chip s3c_irq_wdtac97 = {
.mask = s3c_irq_wdtac97_mask,
.unmask = s3c_irq_wdtac97_unmask,
.ack = s3c_irq_wdtac97_ack,
.irq_mask = s3c_irq_wdtac97_mask,
.irq_unmask = s3c_irq_wdtac97_unmask,
.irq_ack = s3c_irq_wdtac97_ack,
};
static int s3c2440_irq_add(struct sys_device *sysdev)

18
arch/arm/mach-s3c2440/s3c244x-irq.c
View File

@ -68,27 +68,27 @@ static void s3c_irq_demux_cam(unsigned int irq,
#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
static void
s3c_irq_cam_mask(unsigned int irqno)
s3c_irq_cam_mask(struct irq_data *data)
{
s3c_irqsub_mask(irqno, INTMSK_CAM, 3<<11);
s3c_irqsub_mask(data->irq, INTMSK_CAM, 3 << 11);
}
static void
s3c_irq_cam_unmask(unsigned int irqno)
s3c_irq_cam_unmask(struct irq_data *data)
{
s3c_irqsub_unmask(irqno, INTMSK_CAM);
s3c_irqsub_unmask(data->irq, INTMSK_CAM);
}
static void
s3c_irq_cam_ack(unsigned int irqno)
s3c_irq_cam_ack(struct irq_data *data)
{
s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11);
s3c_irqsub_maskack(data->irq, INTMSK_CAM, 3 << 11);
}
static struct irq_chip s3c_irq_cam = {
.mask = s3c_irq_cam_mask,
.unmask = s3c_irq_cam_unmask,
.ack = s3c_irq_cam_ack,
.irq_mask = s3c_irq_cam_mask,
.irq_unmask = s3c_irq_cam_unmask,
.irq_ack = s3c_irq_cam_ack,
};
static int s3c244x_irq_add(struct sys_device *sysdev)

95
arch/arm/mach-s3c2443/irq.c
View File

@ -75,28 +75,27 @@ static void s3c2443_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0))
#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
static void s3c2443_irq_wdtac97_mask(unsigned int irqno)
static void s3c2443_irq_wdtac97_mask(struct irq_data *data)
{
s3c_irqsub_mask(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97);
s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
}
static void s3c2443_irq_wdtac97_unmask(unsigned int irqno)
static void s3c2443_irq_wdtac97_unmask(struct irq_data *data)
{
s3c_irqsub_unmask(irqno, INTMSK_WDTAC97);
s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
}
static void s3c2443_irq_wdtac97_ack(unsigned int irqno)
static void s3c2443_irq_wdtac97_ack(struct irq_data *data)
{
s3c_irqsub_maskack(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97);
s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
}
static struct irq_chip s3c2443_irq_wdtac97 = {
.mask = s3c2443_irq_wdtac97_mask,
.unmask = s3c2443_irq_wdtac97_unmask,
.ack = s3c2443_irq_wdtac97_ack,
.irq_mask = s3c2443_irq_wdtac97_mask,
.irq_unmask = s3c2443_irq_wdtac97_unmask,
.irq_ack = s3c2443_irq_wdtac97_ack,
};
/* LCD sub interrupts */
static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
@ -107,28 +106,27 @@ static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0))
#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
static void s3c2443_irq_lcd_mask(unsigned int irqno)
static void s3c2443_irq_lcd_mask(struct irq_data *data)
{
s3c_irqsub_mask(irqno, INTMSK_LCD, SUBMSK_LCD);
s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
}
static void s3c2443_irq_lcd_unmask(unsigned int irqno)
static void s3c2443_irq_lcd_unmask(struct irq_data *data)
{
s3c_irqsub_unmask(irqno, INTMSK_LCD);
s3c_irqsub_unmask(data->irq, INTMSK_LCD);
}
static void s3c2443_irq_lcd_ack(unsigned int irqno)
static void s3c2443_irq_lcd_ack(struct irq_data *data)
{
s3c_irqsub_maskack(irqno, INTMSK_LCD, SUBMSK_LCD);
s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
}
static struct irq_chip s3c2443_irq_lcd = {
.mask = s3c2443_irq_lcd_mask,
.unmask = s3c2443_irq_lcd_unmask,
.ack = s3c2443_irq_lcd_ack,
.irq_mask = s3c2443_irq_lcd_mask,
.irq_unmask = s3c2443_irq_lcd_unmask,
.irq_ack = s3c2443_irq_lcd_ack,
};
/* DMA sub interrupts */
static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
@ -139,29 +137,27 @@ static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
#define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
static void s3c2443_irq_dma_mask(unsigned int irqno)
static void s3c2443_irq_dma_mask(struct irq_data *data)
{
s3c_irqsub_mask(irqno, INTMSK_DMA, SUBMSK_DMA);
s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
}
static void s3c2443_irq_dma_unmask(unsigned int irqno)
static void s3c2443_irq_dma_unmask(struct irq_data *data)
{
s3c_irqsub_unmask(irqno, INTMSK_DMA);
s3c_irqsub_unmask(data->irq, INTMSK_DMA);
}
static void s3c2443_irq_dma_ack(unsigned int irqno)
static void s3c2443_irq_dma_ack(struct irq_data *data)
{
s3c_irqsub_maskack(irqno, INTMSK_DMA, SUBMSK_DMA);
s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
}
static struct irq_chip s3c2443_irq_dma = {
.mask = s3c2443_irq_dma_mask,
.unmask = s3c2443_irq_dma_unmask,
.ack = s3c2443_irq_dma_ack,
.irq_mask = s3c2443_irq_dma_mask,
.irq_unmask = s3c2443_irq_dma_unmask,
.irq_ack = s3c2443_irq_dma_ack,
};
/* UART3 sub interrupts */
static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
@ -172,28 +168,27 @@ static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
#define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
static void s3c2443_irq_uart3_mask(unsigned int irqno)
static void s3c2443_irq_uart3_mask(struct irq_data *data)
{
s3c_irqsub_mask(irqno, INTMSK_UART3, SUBMSK_UART3);
s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
}
static void s3c2443_irq_uart3_unmask(unsigned int irqno)
static void s3c2443_irq_uart3_unmask(struct irq_data *data)
{
s3c_irqsub_unmask(irqno, INTMSK_UART3);
s3c_irqsub_unmask(data->irq, INTMSK_UART3);
}
static void s3c2443_irq_uart3_ack(unsigned int irqno)
static void s3c2443_irq_uart3_ack(struct irq_data *data)
{
s3c_irqsub_maskack(irqno, INTMSK_UART3, SUBMSK_UART3);
s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
}
static struct irq_chip s3c2443_irq_uart3 = {
.mask = s3c2443_irq_uart3_mask,
.unmask = s3c2443_irq_uart3_unmask,
.ack = s3c2443_irq_uart3_ack,
.irq_mask = s3c2443_irq_uart3_mask,
.irq_unmask = s3c2443_irq_uart3_unmask,
.irq_ack = s3c2443_irq_uart3_ack,
};
/* CAM sub interrupts */
static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc)
@ -204,25 +199,25 @@ static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc)
#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
#define SUBMSK_CAM INTMSK(IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P)
static void s3c2443_irq_cam_mask(unsigned int irqno)
static void s3c2443_irq_cam_mask(struct irq_data *data)
{
s3c_irqsub_mask(irqno, INTMSK_CAM, SUBMSK_CAM);
s3c_irqsub_mask(data->irq, INTMSK_CAM, SUBMSK_CAM);
}
static void s3c2443_irq_cam_unmask(unsigned int irqno)
static void s3c2443_irq_cam_unmask(struct irq_data *data)
{
s3c_irqsub_unmask(irqno, INTMSK_CAM);
s3c_irqsub_unmask(data->irq, INTMSK_CAM);
}
static void s3c2443_irq_cam_ack(unsigned int irqno)
static void s3c2443_irq_cam_ack(struct irq_data *data)
{
s3c_irqsub_maskack(irqno, INTMSK_CAM, SUBMSK_CAM);
s3c_irqsub_maskack(data->irq, INTMSK_CAM, SUBMSK_CAM);
}
static struct irq_chip s3c2443_irq_cam = {
.mask = s3c2443_irq_cam_mask,
.unmask = s3c2443_irq_cam_unmask,
.ack = s3c2443_irq_cam_ack,
.irq_mask = s3c2443_irq_cam_mask,
.irq_unmask = s3c2443_irq_cam_unmask,
.irq_ack = s3c2443_irq_cam_ack,
};
/* IRQ initialisation code */

26
arch/arm/mach-s5pv310/irq-combiner.c
View File

@ -30,24 +30,26 @@ struct combiner_chip_data {
static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
static inline void __iomem *combiner_base(unsigned int irq)
static inline void __iomem *combiner_base(struct irq_data *data)
{
struct combiner_chip_data *combiner_data = get_irq_chip_data(irq);
struct combiner_chip_data *combiner_data =
irq_data_get_irq_chip_data(data);
return combiner_data->base;
}
static void combiner_mask_irq(unsigned int irq)
static void combiner_mask_irq(struct irq_data *data)
{
u32 mask = 1 << (irq % 32);
u32 mask = 1 << (data->irq % 32);
__raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_CLEAR);
__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
}
static void combiner_unmask_irq(unsigned int irq)
static void combiner_unmask_irq(struct irq_data *data)
{
u32 mask = 1 << (irq % 32);
u32 mask = 1 << (data->irq % 32);
__raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_SET);
__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
}
static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
@ -58,7 +60,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
unsigned long status;
/* primary controller ack'ing */
chip->ack(irq);
chip->irq_ack(&desc->irq_data);
spin_lock(&irq_controller_lock);
status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
@ -78,13 +80,13 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
out:
/* primary controller unmasking */
chip->unmask(irq);
chip->irq_unmask(&desc->irq_data);
}
static struct irq_chip combiner_chip = {
.name = "COMBINER",
.mask = combiner_mask_irq,
.unmask = combiner_unmask_irq,
.irq_mask = combiner_mask_irq,
.irq_unmask = combiner_unmask_irq,
};
void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)

53
arch/arm/mach-s5pv310/irq-eint.c
View File

@ -48,42 +48,43 @@ static unsigned int s5pv310_get_irq_nr(unsigned int number)
return ret;
}
static inline void s5pv310_irq_eint_mask(unsigned int irq)
static inline void s5pv310_irq_eint_mask(struct irq_data *data)
{
u32 mask;
spin_lock(&eint_lock);
mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
mask |= eint_irq_to_bit(irq);
__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
mask |= eint_irq_to_bit(data->irq);
__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
spin_unlock(&eint_lock);
}
static void s5pv310_irq_eint_unmask(unsigned int irq)
static void s5pv310_irq_eint_unmask(struct irq_data *data)
{
u32 mask;
spin_lock(&eint_lock);
mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
mask &= ~(eint_irq_to_bit(irq));
__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
mask &= ~(eint_irq_to_bit(data->irq));
__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
spin_unlock(&eint_lock);
}
static inline void s5pv310_irq_eint_ack(unsigned int irq)
static inline void s5pv310_irq_eint_ack(struct irq_data *data)
{
__raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
__raw_writel(eint_irq_to_bit(data->irq),
S5P_EINT_PEND(EINT_REG_NR(data->irq)));
}
static void s5pv310_irq_eint_maskack(unsigned int irq)
static void s5pv310_irq_eint_maskack(struct irq_data *data)
{
s5pv310_irq_eint_mask(irq);
s5pv310_irq_eint_ack(irq);
s5pv310_irq_eint_mask(data);
s5pv310_irq_eint_ack(data);
}
static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type)
static int s5pv310_irq_eint_set_type(struct irq_data *data, unsigned int type)
{
int offs = EINT_OFFSET(irq);
int offs = EINT_OFFSET(data->irq);
int shift;
u32 ctrl, mask;
u32 newvalue = 0;
@ -118,10 +119,10 @@ static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type)
mask = 0x7 << shift;
spin_lock(&eint_lock);
ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq)));
ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
ctrl &= ~mask;
ctrl |= newvalue << shift;
__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq)));
__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
spin_unlock(&eint_lock);
switch (offs) {
@ -146,11 +147,11 @@ static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type)
static struct irq_chip s5pv310_irq_eint = {
.name = "s5pv310-eint",
.mask = s5pv310_irq_eint_mask,
.unmask = s5pv310_irq_eint_unmask,
.mask_ack = s5pv310_irq_eint_maskack,
.ack = s5pv310_irq_eint_ack,
.set_type = s5pv310_irq_eint_set_type,
.irq_mask = s5pv310_irq_eint_mask,
.irq_unmask = s5pv310_irq_eint_unmask,
.irq_mask_ack = s5pv310_irq_eint_maskack,
.irq_ack = s5pv310_irq_eint_ack,
.irq_set_type = s5pv310_irq_eint_set_type,
#ifdef CONFIG_PM
.irq_set_wake = s3c_irqext_wake,
#endif
@ -192,14 +193,14 @@ static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
u32 *irq_data = get_irq_data(irq);
struct irq_chip *chip = get_irq_chip(irq);
chip->mask(irq);
chip->irq_mask(&desc->irq_data);
if (chip->ack)
chip->ack(irq);
if (chip->irq_ack)
chip->irq_ack(&desc->irq_data);
generic_handle_irq(*irq_data);
chip->unmask(irq);
chip->irq_unmask(&desc->irq_data);
}
int __init s5pv310_init_irq_eint(void)

4
arch/arm/plat-s3c24xx/include/plat/irq.h
View File

@ -107,9 +107,9 @@ s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group)
/* exported for use in arch/arm/mach-s3c2410 */
#ifdef CONFIG_PM
extern int s3c_irq_wake(unsigned int irqno, unsigned int state);
extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
#else
#define s3c_irq_wake NULL
#endif
extern int s3c_irqext_type(unsigned int irq, unsigned int type);
extern int s3c_irqext_type(struct irq_data *d, unsigned int type);

9
arch/arm/plat-s3c24xx/irq-pm.c
View File

@ -15,11 +15,14 @@
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/sysdev.h>
#include <linux/irq.h>
#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/irq.h>
#include <asm/irq.h>
/* state for IRQs over sleep */
/* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
@ -30,15 +33,15 @@
unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
unsigned long s3c_irqwake_eintallow = 0x0000fff0L;
int s3c_irq_wake(unsigned int irqno, unsigned int state)
int s3c_irq_wake(struct irq_data *data, unsigned int state)
{
unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
unsigned long irqbit = 1 << (data->irq - IRQ_EINT0);
if (!(s3c_irqwake_intallow & irqbit))
return -ENOENT;
printk(KERN_INFO "wake %s for irq %d\n",
state ? "enabled" : "disabled", irqno);
state ? "enabled" : "disabled", data->irq);
if (!state)
s3c_irqwake_intmask |= irqbit;

180
arch/arm/plat-s3c24xx/irq.c
View File

@ -34,30 +34,29 @@
#include <plat/irq.h>
static void
s3c_irq_mask(unsigned int irqno)
s3c_irq_mask(struct irq_data *data)
{
unsigned int irqno = data->irq - IRQ_EINT0;
unsigned long mask;
irqno -= IRQ_EINT0;
mask = __raw_readl(S3C2410_INTMSK);
mask |= 1UL << irqno;
__raw_writel(mask, S3C2410_INTMSK);
}
static inline void
s3c_irq_ack(unsigned int irqno)
s3c_irq_ack(struct irq_data *data)
{
unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
__raw_writel(bitval, S3C2410_SRCPND);
__raw_writel(bitval, S3C2410_INTPND);
}
static inline void
s3c_irq_maskack(unsigned int irqno)
s3c_irq_maskack(struct irq_data *data)
{
unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
unsigned long mask;
mask = __raw_readl(S3C2410_INTMSK);
@ -69,8 +68,9 @@ s3c_irq_maskack(unsigned int irqno)
static void
s3c_irq_unmask(unsigned int irqno)
s3c_irq_unmask(struct irq_data *data)
{
unsigned int irqno = data->irq;
unsigned long mask;
if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
@ -85,40 +85,39 @@ s3c_irq_unmask(unsigned int irqno)
struct irq_chip s3c_irq_level_chip = {
.name = "s3c-level",
.ack = s3c_irq_maskack,
.mask = s3c_irq_mask,
.unmask = s3c_irq_unmask,
.set_wake = s3c_irq_wake
.irq_ack = s3c_irq_maskack,
.irq_mask = s3c_irq_mask,
.irq_unmask = s3c_irq_unmask,
.irq_set_wake = s3c_irq_wake
};
struct irq_chip s3c_irq_chip = {
.name = "s3c",
.ack = s3c_irq_ack,
.mask = s3c_irq_mask,
.unmask = s3c_irq_unmask,
.set_wake = s3c_irq_wake
.irq_ack = s3c_irq_ack,
.irq_mask = s3c_irq_mask,
.irq_unmask = s3c_irq_unmask,
.irq_set_wake = s3c_irq_wake
};
static void
s3c_irqext_mask(unsigned int irqno)
s3c_irqext_mask(struct irq_data *data)
{
unsigned int irqno = data->irq - EXTINT_OFF;
unsigned long mask;
irqno -= EXTINT_OFF;
mask = __raw_readl(S3C24XX_EINTMASK);
mask |= ( 1UL << irqno);
__raw_writel(mask, S3C24XX_EINTMASK);
}
static void
s3c_irqext_ack(unsigned int irqno)
s3c_irqext_ack(struct irq_data *data)
{
unsigned long req;
unsigned long bit;
unsigned long mask;
bit = 1UL << (irqno - EXTINT_OFF);
bit = 1UL << (data->irq - EXTINT_OFF);
mask = __raw_readl(S3C24XX_EINTMASK);
@ -129,64 +128,57 @@ s3c_irqext_ack(unsigned int irqno)
/* not sure if we should be acking the parent irq... */
if (irqno <= IRQ_EINT7 ) {
if (data->irq <= IRQ_EINT7) {
if ((req & 0xf0) == 0)
s3c_irq_ack(IRQ_EINT4t7);
s3c_irq_ack(irq_get_irq_data(IRQ_EINT4t7));
} else {
if ((req >> 8) == 0)
s3c_irq_ack(IRQ_EINT8t23);
s3c_irq_ack(irq_get_irq_data(IRQ_EINT8t23));
}
}
static void
s3c_irqext_unmask(unsigned int irqno)
s3c_irqext_unmask(struct irq_data *data)
{
unsigned int irqno = data->irq - EXTINT_OFF;
unsigned long mask;
irqno -= EXTINT_OFF;
mask = __raw_readl(S3C24XX_EINTMASK);
mask &= ~( 1UL << irqno);
mask &= ~(1UL << irqno);
__raw_writel(mask, S3C24XX_EINTMASK);
}
int
s3c_irqext_type(unsigned int irq, unsigned int type)
s3c_irqext_type(struct irq_data *data, unsigned int type)
{
void __iomem *extint_reg;
void __iomem *gpcon_reg;
unsigned long gpcon_offset, extint_offset;
unsigned long newvalue = 0, value;
if ((irq >= IRQ_EINT0) && (irq <= IRQ_EINT3))
{
if ((data->irq >= IRQ_EINT0) && (data->irq <= IRQ_EINT3)) {
gpcon_reg = S3C2410_GPFCON;
extint_reg = S3C24XX_EXTINT0;
gpcon_offset = (irq - IRQ_EINT0) * 2;
extint_offset = (irq - IRQ_EINT0) * 4;
}
else if ((irq >= IRQ_EINT4) && (irq <= IRQ_EINT7))
{
gpcon_offset = (data->irq - IRQ_EINT0) * 2;
extint_offset = (data->irq - IRQ_EINT0) * 4;
} else if ((data->irq >= IRQ_EINT4) && (data->irq <= IRQ_EINT7)) {
gpcon_reg = S3C2410_GPFCON;
extint_reg = S3C24XX_EXTINT0;
gpcon_offset = (irq - (EXTINT_OFF)) * 2;
extint_offset = (irq - (EXTINT_OFF)) * 4;
}
else if ((irq >= IRQ_EINT8) && (irq <= IRQ_EINT15))
{
gpcon_offset = (data->irq - (EXTINT_OFF)) * 2;
extint_offset = (data->irq - (EXTINT_OFF)) * 4;
} else if ((data->irq >= IRQ_EINT8) && (data->irq <= IRQ_EINT15)) {
gpcon_reg = S3C2410_GPGCON;
extint_reg = S3C24XX_EXTINT1;
gpcon_offset = (irq - IRQ_EINT8) * 2;
extint_offset = (irq - IRQ_EINT8) * 4;
}
else if ((irq >= IRQ_EINT16) && (irq <= IRQ_EINT23))
{
gpcon_offset = (data->irq - IRQ_EINT8) * 2;
extint_offset = (data->irq - IRQ_EINT8) * 4;
} else if ((data->irq >= IRQ_EINT16) && (data->irq <= IRQ_EINT23)) {
gpcon_reg = S3C2410_GPGCON;
extint_reg = S3C24XX_EXTINT2;
gpcon_offset = (irq - IRQ_EINT8) * 2;
extint_offset = (irq - IRQ_EINT16) * 4;
} else
gpcon_offset = (data->irq - IRQ_EINT8) * 2;
extint_offset = (data->irq - IRQ_EINT16) * 4;
} else {
return -1;
}
/* Set the GPIO to external interrupt mode */
value = __raw_readl(gpcon_reg);
@ -234,20 +226,20 @@ s3c_irqext_type(unsigned int irq, unsigned int type)
static struct irq_chip s3c_irqext_chip = {
.name = "s3c-ext",
.mask = s3c_irqext_mask,
.unmask = s3c_irqext_unmask,
.ack = s3c_irqext_ack,
.set_type = s3c_irqext_type,
.irq_mask = s3c_irqext_mask,
.irq_unmask = s3c_irqext_unmask,
.irq_ack = s3c_irqext_ack,
.irq_set_type = s3c_irqext_type,
.irq_set_wake = s3c_irqext_wake
};
static struct irq_chip s3c_irq_eint0t4 = {
.name = "s3c-ext0",
.ack = s3c_irq_ack,
.mask = s3c_irq_mask,
.unmask = s3c_irq_unmask,
.set_wake = s3c_irq_wake,
.set_type = s3c_irqext_type,
.irq_ack = s3c_irq_ack,
.irq_mask = s3c_irq_mask,
.irq_unmask = s3c_irq_unmask,
.irq_set_wake = s3c_irq_wake,
.irq_set_type = s3c_irqext_type,
};
/* mask values for the parent registers for each of the interrupt types */
@ -261,109 +253,109 @@ static struct irq_chip s3c_irq_eint0t4 = {
/* UART0 */
static void
s3c_irq_uart0_mask(unsigned int irqno)
s3c_irq_uart0_mask(struct irq_data *data)
{
s3c_irqsub_mask(irqno, INTMSK_UART0, 7);
s3c_irqsub_mask(data->irq, INTMSK_UART0, 7);
}
static void
s3c_irq_uart0_unmask(unsigned int irqno)
s3c_irq_uart0_unmask(struct irq_data *data)
{
s3c_irqsub_unmask(irqno, INTMSK_UART0);
s3c_irqsub_unmask(data->irq, INTMSK_UART0);
}
static void
s3c_irq_uart0_ack(unsigned int irqno)
s3c_irq_uart0_ack(struct irq_data *data)
{
s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
s3c_irqsub_maskack(data->irq, INTMSK_UART0, 7);
}
static struct irq_chip s3c_irq_uart0 = {
.name = "s3c-uart0",
.mask = s3c_irq_uart0_mask,
.unmask = s3c_irq_uart0_unmask,
.ack = s3c_irq_uart0_ack,
.irq_mask = s3c_irq_uart0_mask,
.irq_unmask = s3c_irq_uart0_unmask,
.irq_ack = s3c_irq_uart0_ack,
};
/* UART1 */
static void
s3c_irq_uart1_mask(unsigned int irqno)
s3c_irq_uart1_mask(struct irq_data *data)
{
s3c_irqsub_mask(irqno, INTMSK_UART1, 7 << 3);
s3c_irqsub_mask(data->irq, INTMSK_UART1, 7 << 3);
}
static void
s3c_irq_uart1_unmask(unsigned int irqno)
s3c_irq_uart1_unmask(struct irq_data *data)
{
s3c_irqsub_unmask(irqno, INTMSK_UART1);
s3c_irqsub_unmask(data->irq, INTMSK_UART1);
}
static void
s3c_irq_uart1_ack(unsigned int irqno)
s3c_irq_uart1_ack(struct irq_data *data)
{
s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
s3c_irqsub_maskack(data->irq, INTMSK_UART1, 7 << 3);
}
static struct irq_chip s3c_irq_uart1 = {
.name = "s3c-uart1",
.mask = s3c_irq_uart1_mask,
.unmask = s3c_irq_uart1_unmask,
.ack = s3c_irq_uart1_ack,
.irq_mask = s3c_irq_uart1_mask,
.irq_unmask = s3c_irq_uart1_unmask,
.irq_ack = s3c_irq_uart1_ack,
};
/* UART2 */
static void
s3c_irq_uart2_mask(unsigned int irqno)
s3c_irq_uart2_mask(struct irq_data *data)
{
s3c_irqsub_mask(irqno, INTMSK_UART2, 7 << 6);
s3c_irqsub_mask(data->irq, INTMSK_UART2, 7 << 6);
}
static void
s3c_irq_uart2_unmask(unsigned int irqno)
s3c_irq_uart2_unmask(struct irq_data *data)
{
s3c_irqsub_unmask(irqno, INTMSK_UART2);
s3c_irqsub_unmask(data->irq, INTMSK_UART2);
}
static void
s3c_irq_uart2_ack(unsigned int irqno)
s3c_irq_uart2_ack(struct irq_data *data)
{
s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
s3c_irqsub_maskack(data->irq, INTMSK_UART2, 7 << 6);
}
static struct irq_chip s3c_irq_uart2 = {
.name = "s3c-uart2",
.mask = s3c_irq_uart2_mask,
.unmask = s3c_irq_uart2_unmask,
.ack = s3c_irq_uart2_ack,
.irq_mask = s3c_irq_uart2_mask,
.irq_unmask = s3c_irq_uart2_unmask,
.irq_ack = s3c_irq_uart2_ack,
};
/* ADC and Touchscreen */
static void
s3c_irq_adc_mask(unsigned int irqno)
s3c_irq_adc_mask(struct irq_data *d)
{
s3c_irqsub_mask(irqno, INTMSK_ADCPARENT, 3 << 9);
s3c_irqsub_mask(d->irq, INTMSK_ADCPARENT, 3 << 9);
}
static void
s3c_irq_adc_unmask(unsigned int irqno)
s3c_irq_adc_unmask(struct irq_data *d)
{
s3c_irqsub_unmask(irqno, INTMSK_ADCPARENT);
s3c_irqsub_unmask(d->irq, INTMSK_ADCPARENT);
}
static void
s3c_irq_adc_ack(unsigned int irqno)
s3c_irq_adc_ack(struct irq_data *d)
{
s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9);
s3c_irqsub_ack(d->irq, INTMSK_ADCPARENT, 3 << 9);
}
static struct irq_chip s3c_irq_adc = {
.name = "s3c-adc",
.mask = s3c_irq_adc_mask,
.unmask = s3c_irq_adc_unmask,
.ack = s3c_irq_adc_ack,
.irq_mask = s3c_irq_adc_mask,
.irq_unmask = s3c_irq_adc_unmask,
.irq_ack = s3c_irq_adc_ack,
};
/* irq demux for adc */

82
arch/arm/plat-s5p/irq-eint.c
View File

@ -28,39 +28,40 @@
#include <plat/gpio-cfg.h>
#include <mach/regs-gpio.h>
static inline void s5p_irq_eint_mask(unsigned int irq)
static inline void s5p_irq_eint_mask(struct irq_data *data)
{
u32 mask;
mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
mask |= eint_irq_to_bit(irq);
__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
mask |= eint_irq_to_bit(data->irq);
__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
}
static void s5p_irq_eint_unmask(unsigned int irq)
static void s5p_irq_eint_unmask(struct irq_data *data)
{
u32 mask;
mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
mask &= ~(eint_irq_to_bit(irq));
__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
mask &= ~(eint_irq_to_bit(data->irq));
__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
}
static inline void s5p_irq_eint_ack(unsigned int irq)
static inline void s5p_irq_eint_ack(struct irq_data *data)
{
__raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
__raw_writel(eint_irq_to_bit(data->irq),
S5P_EINT_PEND(EINT_REG_NR(data->irq)));
}
static void s5p_irq_eint_maskack(unsigned int irq)
static void s5p_irq_eint_maskack(struct irq_data *data)
{
/* compiler should in-line these */
s5p_irq_eint_mask(irq);
s5p_irq_eint_ack(irq);
s5p_irq_eint_mask(data);
s5p_irq_eint_ack(data);
}
static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type)
static int s5p_irq_eint_set_type(struct irq_data *data, unsigned int type)
{
int offs = EINT_OFFSET(irq);
int offs = EINT_OFFSET(data->irq);
int shift;
u32 ctrl, mask;
u32 newvalue = 0;
@ -94,10 +95,10 @@ static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type)
shift = (offs & 0x7) * 4;
mask = 0x7 << shift;
ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq)));
ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
ctrl &= ~mask;
ctrl |= newvalue << shift;
__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq)));
__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
if ((0 <= offs) && (offs < 8))
s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
@ -119,11 +120,11 @@ static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type)
static struct irq_chip s5p_irq_eint = {
.name = "s5p-eint",
.mask = s5p_irq_eint_mask,
.unmask = s5p_irq_eint_unmask,
.mask_ack = s5p_irq_eint_maskack,
.ack = s5p_irq_eint_ack,
.set_type = s5p_irq_eint_set_type,
.irq_mask = s5p_irq_eint_mask,
.irq_unmask = s5p_irq_eint_unmask,
.irq_mask_ack = s5p_irq_eint_maskack,
.irq_ack = s5p_irq_eint_ack,
.irq_set_type = s5p_irq_eint_set_type,
#ifdef CONFIG_PM
.irq_set_wake = s3c_irqext_wake,
#endif
@ -159,40 +160,41 @@ static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
s5p_irq_demux_eint(IRQ_EINT(24));
}
static inline void s5p_irq_vic_eint_mask(unsigned int irq)
static inline void s5p_irq_vic_eint_mask(struct irq_data *data)
{
void __iomem *base = get_irq_chip_data(irq);
void __iomem *base = irq_data_get_irq_chip_data(data);
s5p_irq_eint_mask(irq);
writel(1 << EINT_OFFSET(irq), base + VIC_INT_ENABLE_CLEAR);
s5p_irq_eint_mask(data);
writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE_CLEAR);
}
static void s5p_irq_vic_eint_unmask(unsigned int irq)
static void s5p_irq_vic_eint_unmask(struct irq_data *data)
{
void __iomem *base = get_irq_chip_data(irq);
void __iomem *base = irq_data_get_irq_chip_data(data);
s5p_irq_eint_unmask(irq);
writel(1 << EINT_OFFSET(irq), base + VIC_INT_ENABLE);
s5p_irq_eint_unmask(data);
writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE);
}
static inline void s5p_irq_vic_eint_ack(unsigned int irq)
static inline void s5p_irq_vic_eint_ack(struct irq_data *data)
{
__raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
__raw_writel(eint_irq_to_bit(data->irq),
S5P_EINT_PEND(EINT_REG_NR(data->irq)));
}
static void s5p_irq_vic_eint_maskack(unsigned int irq)
static void s5p_irq_vic_eint_maskack(struct irq_data *data)
{
s5p_irq_vic_eint_mask(irq);
s5p_irq_vic_eint_ack(irq);
s5p_irq_vic_eint_mask(data);
s5p_irq_vic_eint_ack(data);
}
static struct irq_chip s5p_irq_vic_eint = {
.name = "s5p_vic_eint",
.mask = s5p_irq_vic_eint_mask,
.unmask = s5p_irq_vic_eint_unmask,
.mask_ack = s5p_irq_vic_eint_maskack,
.ack = s5p_irq_vic_eint_ack,
.set_type = s5p_irq_eint_set_type,
.irq_mask = s5p_irq_vic_eint_mask,
.irq_unmask = s5p_irq_vic_eint_unmask,
.irq_mask_ack = s5p_irq_vic_eint_maskack,
.irq_ack = s5p_irq_vic_eint_ack,
.irq_set_type = s5p_irq_eint_set_type,
#ifdef CONFIG_PM
.irq_set_wake = s3c_irqext_wake,
#endif

50
arch/arm/plat-s5p/irq-gpioint.c
View File

@ -30,9 +30,9 @@
static struct s3c_gpio_chip *irq_chips[S5P_GPIOINT_GROUP_MAXNR];
static int s5p_gpioint_get_group(unsigned int irq)
static int s5p_gpioint_get_group(struct irq_data *data)
{
struct gpio_chip *chip = get_irq_data(irq);
struct gpio_chip *chip = irq_data_get_irq_data(data);
struct s3c_gpio_chip *s3c_chip = container_of(chip,
struct s3c_gpio_chip, chip);
int group;
@ -44,22 +44,22 @@ static int s5p_gpioint_get_group(unsigned int irq)
return group;
}
static int s5p_gpioint_get_offset(unsigned int irq)
static int s5p_gpioint_get_offset(struct irq_data *data)
{
struct gpio_chip *chip = get_irq_data(irq);
struct gpio_chip *chip = irq_data_get_irq_data(data);
struct s3c_gpio_chip *s3c_chip = container_of(chip,
struct s3c_gpio_chip, chip);
return irq - s3c_chip->irq_base;
return data->irq - s3c_chip->irq_base;
}
static void s5p_gpioint_ack(unsigned int irq)
static void s5p_gpioint_ack(struct irq_data *data)
{
int group, offset, pend_offset;
unsigned int value;
group = s5p_gpioint_get_group(irq);
offset = s5p_gpioint_get_offset(irq);
group = s5p_gpioint_get_group(data);
offset = s5p_gpioint_get_offset(data);
pend_offset = group << 2;
value = __raw_readl(S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset);
@ -67,13 +67,13 @@ static void s5p_gpioint_ack(unsigned int irq)
__raw_writel(value, S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset);
}
static void s5p_gpioint_mask(unsigned int irq)
static void s5p_gpioint_mask(struct irq_data *data)
{
int group, offset, mask_offset;
unsigned int value;
group = s5p_gpioint_get_group(irq);
offset = s5p_gpioint_get_offset(irq);
group = s5p_gpioint_get_group(data);
offset = s5p_gpioint_get_offset(data);
mask_offset = group << 2;
value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
@ -81,13 +81,13 @@ static void s5p_gpioint_mask(unsigned int irq)
__raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
}
static void s5p_gpioint_unmask(unsigned int irq)
static void s5p_gpioint_unmask(struct irq_data *data)
{
int group, offset, mask_offset;
unsigned int value;
group = s5p_gpioint_get_group(irq);
offset = s5p_gpioint_get_offset(irq);
group = s5p_gpioint_get_group(data);
offset = s5p_gpioint_get_offset(data);
mask_offset = group << 2;
value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
@ -95,19 +95,19 @@ static void s5p_gpioint_unmask(unsigned int irq)
__raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
}
static void s5p_gpioint_mask_ack(unsigned int irq)
static void s5p_gpioint_mask_ack(struct irq_data *data)
{
s5p_gpioint_mask(irq);
s5p_gpioint_ack(irq);
s5p_gpioint_mask(data);
s5p_gpioint_ack(data);
}
static int s5p_gpioint_set_type(unsigned int irq, unsigned int type)
static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
{
int group, offset, con_offset;
unsigned int value;
group = s5p_gpioint_get_group(irq);
offset = s5p_gpioint_get_offset(irq);
group = s5p_gpioint_get_group(data);
offset = s5p_gpioint_get_offset(data);
con_offset = group << 2;
switch (type) {
@ -142,11 +142,11 @@ static int s5p_gpioint_set_type(unsigned int irq, unsigned int type)
struct irq_chip s5p_gpioint = {
.name = "s5p_gpioint",
.ack = s5p_gpioint_ack,
.mask = s5p_gpioint_mask,
.mask_ack = s5p_gpioint_mask_ack,
.unmask = s5p_gpioint_unmask,
.set_type = s5p_gpioint_set_type,
.irq_ack = s5p_gpioint_ack,
.irq_mask = s5p_gpioint_mask,
.irq_mask_ack = s5p_gpioint_mask_ack,
.irq_unmask = s5p_gpioint_unmask,
.irq_set_type = s5p_gpioint_set_type,
};
static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)

6
arch/arm/plat-s5p/irq-pm.c
View File

@ -37,14 +37,14 @@
unsigned long s3c_irqwake_intallow = 0x00000006L;
unsigned long s3c_irqwake_eintallow = 0xffffffffL;
int s3c_irq_wake(unsigned int irqno, unsigned int state)
int s3c_irq_wake(struct irq_data *data, unsigned int state)
{
unsigned long irqbit;
switch (irqno) {
switch (data->irq) {
case IRQ_RTC_TIC:
case IRQ_RTC_ALARM:
irqbit = 1 << (irqno + 1 - IRQ_RTC_ALARM);
irqbit = 1 << (data->irq + 1 - IRQ_RTC_ALARM);
if (!state)
s3c_irqwake_intmask |= irqbit;
else

6
arch/arm/plat-samsung/irq-uart.c
View File

@ -30,7 +30,7 @@
static inline void __iomem *s3c_irq_uart_base(struct irq_data *data)
{
struct s3c_uart_irq *uirq = data->chip_data;
struct s3c_uart_irq *uirq = irq_data_get_irq_chip_data(data);
return uirq->regs;
}
@ -83,7 +83,7 @@ static void s3c_irq_uart_ack(struct irq_data *data)
static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
{
struct s3c_uart_irq *uirq = desc->handler_data;
struct s3c_uart_irq *uirq = desc->irq_data.handler_data;
u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
int base = uirq->base_irq;
@ -124,7 +124,7 @@ static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
set_irq_flags(irq, IRQF_VALID);
}
desc->handler_data = uirq;
desc->irq_data.handler_data = uirq;
set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
}

4
arch/arm/plat-samsung/irq-vic-timer.c
View File

@ -24,7 +24,7 @@
static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
{
generic_handle_irq((int)desc->handler_data);
generic_handle_irq((int)desc->irq_data.handler_data);
}
/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
@ -86,5 +86,5 @@ void __init s3c_init_vic_timer_irq(unsigned int parent_irq,
set_irq_handler(timer_irq, handle_level_irq);
set_irq_flags(timer_irq, IRQF_VALID);
desc->handler_data = (void *)timer_irq;
desc->irq_data.handler_data = (void *)timer_irq;
}