csky: Add pmu interrupt support
This patch add interrupt request and handler for csky pmu. perf can record on hardware event with this patch applied. Signed-off-by: Mao Han <han_mao@c-sky.com> Signed-off-by: Guo Ren <guoren@kernel.org>
This commit is contained in:
Mao Han
Guo Ren
parent
ccffa1ad15
commit
f622fbf205
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@ -11,17 +11,42 @@
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#define CSKY_PMU_MAX_EVENTS 32
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#define DEFAULT_COUNT_WIDTH 48
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#define HPCR "<0, 0x0>" /* PMU Control reg */
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#define HPCNTENR "<0, 0x4>" /* Count Enable reg */
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#define HPCR "<0, 0x0>" /* PMU Control reg */
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#define HPSPR "<0, 0x1>" /* Start PC reg */
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#define HPEPR "<0, 0x2>" /* End PC reg */
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#define HPSIR "<0, 0x3>" /* Soft Counter reg */
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#define HPCNTENR "<0, 0x4>" /* Count Enable reg */
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#define HPINTENR "<0, 0x5>" /* Interrupt Enable reg */
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#define HPOFSR "<0, 0x6>" /* Interrupt Status reg */
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/* The events for a given PMU register set. */
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struct pmu_hw_events {
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/*
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* The events that are active on the PMU for the given index.
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*/
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struct perf_event *events[CSKY_PMU_MAX_EVENTS];
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/*
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* A 1 bit for an index indicates that the counter is being used for
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* an event. A 0 means that the counter can be used.
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*/
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unsigned long used_mask[BITS_TO_LONGS(CSKY_PMU_MAX_EVENTS)];
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};
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static uint64_t (*hw_raw_read_mapping[CSKY_PMU_MAX_EVENTS])(void);
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static void (*hw_raw_write_mapping[CSKY_PMU_MAX_EVENTS])(uint64_t val);
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struct csky_pmu_t {
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struct pmu pmu;
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uint32_t count_width;
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uint32_t hpcr;
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static struct csky_pmu_t {
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struct pmu pmu;
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struct pmu_hw_events __percpu *hw_events;
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struct platform_device *plat_device;
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uint32_t count_width;
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uint32_t hpcr;
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u64 max_period;
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} csky_pmu;
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static int csky_pmu_irq;
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#define to_csky_pmu(p) (container_of(p, struct csky_pmu, pmu))
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#define cprgr(reg) \
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({ \
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@ -802,6 +827,47 @@ static const int csky_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
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},
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};
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int csky_pmu_event_set_period(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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s64 left = local64_read(&hwc->period_left);
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s64 period = hwc->sample_period;
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int ret = 0;
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if (unlikely(left <= -period)) {
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left = period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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ret = 1;
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}
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if (unlikely(left <= 0)) {
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left += period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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ret = 1;
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}
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if (left > (s64)csky_pmu.max_period)
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left = csky_pmu.max_period;
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/*
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* The hw event starts counting from this event offset,
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* mark it to be able to extract future "deltas":
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*/
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local64_set(&hwc->prev_count, (u64)(-left));
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if (hw_raw_write_mapping[hwc->idx] != NULL)
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hw_raw_write_mapping[hwc->idx]((u64)(-left) &
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csky_pmu.max_period);
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cpwcr(HPOFSR, ~BIT(hwc->idx) & cprcr(HPOFSR));
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perf_event_update_userpage(event);
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return ret;
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}
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static void csky_perf_event_update(struct perf_event *event,
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struct hw_perf_event *hwc)
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{
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@ -823,6 +889,11 @@ static void csky_perf_event_update(struct perf_event *event,
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local64_sub(delta, &hwc->period_left);
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}
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static void csky_pmu_reset(void *info)
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{
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cpwcr(HPCR, BIT(31) | BIT(30) | BIT(1));
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}
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static void csky_pmu_read(struct perf_event *event)
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{
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csky_perf_event_update(event, &event->hw);
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@ -899,6 +970,7 @@ static void csky_pmu_disable(struct pmu *pmu)
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static void csky_pmu_start(struct perf_event *event, int flags)
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{
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unsigned long flg;
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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@ -910,16 +982,34 @@ static void csky_pmu_start(struct perf_event *event, int flags)
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hwc->state = 0;
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csky_pmu_event_set_period(event);
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local_irq_save(flg);
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cpwcr(HPINTENR, BIT(idx) | cprcr(HPINTENR));
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cpwcr(HPCNTENR, BIT(idx) | cprcr(HPCNTENR));
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local_irq_restore(flg);
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}
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static void csky_pmu_stop_event(struct perf_event *event)
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{
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unsigned long flg;
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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local_irq_save(flg);
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cpwcr(HPINTENR, ~BIT(idx) & cprcr(HPINTENR));
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cpwcr(HPCNTENR, ~BIT(idx) & cprcr(HPCNTENR));
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local_irq_restore(flg);
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}
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static void csky_pmu_stop(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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if (!(event->hw.state & PERF_HES_STOPPED)) {
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cpwcr(HPCNTENR, ~BIT(idx) & cprcr(HPCNTENR));
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csky_pmu_stop_event(event);
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event->hw.state |= PERF_HES_STOPPED;
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}
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@ -932,22 +1022,26 @@ static void csky_pmu_stop(struct perf_event *event, int flags)
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static void csky_pmu_del(struct perf_event *event, int flags)
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{
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struct pmu_hw_events *hw_events = this_cpu_ptr(csky_pmu.hw_events);
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struct hw_perf_event *hwc = &event->hw;
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csky_pmu_stop(event, PERF_EF_UPDATE);
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hw_events->events[hwc->idx] = NULL;
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perf_event_update_userpage(event);
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}
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/* allocate hardware counter and optionally start counting */
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static int csky_pmu_add(struct perf_event *event, int flags)
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{
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struct pmu_hw_events *hw_events = this_cpu_ptr(csky_pmu.hw_events);
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struct hw_perf_event *hwc = &event->hw;
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local64_set(&hwc->prev_count, 0);
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if (hw_raw_write_mapping[hwc->idx] != NULL)
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hw_raw_write_mapping[hwc->idx](0);
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hw_events->events[hwc->idx] = event;
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hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
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if (flags & PERF_EF_START)
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csky_pmu_start(event, PERF_EF_RELOAD);
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@ -956,8 +1050,110 @@ static int csky_pmu_add(struct perf_event *event, int flags)
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return 0;
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}
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static irqreturn_t csky_pmu_handle_irq(int irq_num, void *dev)
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{
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struct perf_sample_data data;
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struct pmu_hw_events *cpuc = this_cpu_ptr(csky_pmu.hw_events);
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struct pt_regs *regs;
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int idx;
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/*
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* Did an overflow occur?
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*/
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if (!cprcr(HPOFSR))
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return IRQ_NONE;
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/*
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* Handle the counter(s) overflow(s)
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*/
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regs = get_irq_regs();
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csky_pmu_disable(&csky_pmu.pmu);
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for (idx = 0; idx < CSKY_PMU_MAX_EVENTS; ++idx) {
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struct perf_event *event = cpuc->events[idx];
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struct hw_perf_event *hwc;
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/* Ignore if we don't have an event. */
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if (!event)
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continue;
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/*
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* We have a single interrupt for all counters. Check that
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* each counter has overflowed before we process it.
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*/
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if (!(cprcr(HPOFSR) & BIT(idx)))
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continue;
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hwc = &event->hw;
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csky_perf_event_update(event, &event->hw);
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perf_sample_data_init(&data, 0, hwc->last_period);
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csky_pmu_event_set_period(event);
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if (perf_event_overflow(event, &data, regs))
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csky_pmu_stop_event(event);
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}
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csky_pmu_enable(&csky_pmu.pmu);
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/*
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* Handle the pending perf events.
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*
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* Note: this call *must* be run with interrupts disabled. For
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* platforms that can have the PMU interrupts raised as an NMI, this
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* will not work.
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*/
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irq_work_run();
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return IRQ_HANDLED;
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}
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static int csky_pmu_request_irq(irq_handler_t handler)
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{
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int err, irqs;
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struct platform_device *pmu_device = csky_pmu.plat_device;
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if (!pmu_device)
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return -ENODEV;
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irqs = min(pmu_device->num_resources, num_possible_cpus());
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if (irqs < 1) {
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pr_err("no irqs for PMUs defined\n");
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return -ENODEV;
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}
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csky_pmu_irq = platform_get_irq(pmu_device, 0);
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if (csky_pmu_irq < 0)
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return -ENODEV;
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err = request_percpu_irq(csky_pmu_irq, handler, "csky-pmu",
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this_cpu_ptr(csky_pmu.hw_events));
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if (err) {
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pr_err("unable to request IRQ%d for CSKY PMU counters\n",
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csky_pmu_irq);
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return err;
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}
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return 0;
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}
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static void csky_pmu_free_irq(void)
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{
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int irq;
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struct platform_device *pmu_device = csky_pmu.plat_device;
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irq = platform_get_irq(pmu_device, 0);
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if (irq >= 0)
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free_percpu_irq(irq, this_cpu_ptr(csky_pmu.hw_events));
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}
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int init_hw_perf_events(void)
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{
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csky_pmu.hw_events = alloc_percpu_gfp(struct pmu_hw_events,
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GFP_KERNEL);
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if (!csky_pmu.hw_events) {
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pr_info("failed to allocate per-cpu PMU data.\n");
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return -ENOMEM;
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}
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csky_pmu.pmu = (struct pmu) {
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.pmu_enable = csky_pmu_enable,
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.pmu_disable = csky_pmu_disable,
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@ -1029,11 +1225,19 @@ int init_hw_perf_events(void)
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hw_raw_write_mapping[0x1a] = csky_pmu_write_l2wac;
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hw_raw_write_mapping[0x1b] = csky_pmu_write_l2wmc;
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csky_pmu.pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
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return 0;
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}
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cpwcr(HPCR, BIT(31) | BIT(30) | BIT(1));
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static int csky_pmu_starting_cpu(unsigned int cpu)
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{
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enable_percpu_irq(csky_pmu_irq, 0);
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return 0;
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}
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return perf_pmu_register(&csky_pmu.pmu, "cpu", PERF_TYPE_RAW);
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static int csky_pmu_dying_cpu(unsigned int cpu)
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{
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disable_percpu_irq(csky_pmu_irq);
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return 0;
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}
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int csky_pmu_device_probe(struct platform_device *pdev,
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@ -1052,6 +1256,33 @@ int csky_pmu_device_probe(struct platform_device *pdev,
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&csky_pmu.count_width)) {
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csky_pmu.count_width = DEFAULT_COUNT_WIDTH;
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}
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csky_pmu.max_period = BIT(csky_pmu.count_width) - 1;
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csky_pmu.plat_device = pdev;
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/* Ensure the PMU has sane values out of reset. */
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on_each_cpu(csky_pmu_reset, &csky_pmu, 1);
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ret = csky_pmu_request_irq(csky_pmu_handle_irq);
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if (ret) {
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csky_pmu.pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
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pr_notice("[perf] PMU request irq fail!\n");
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}
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ret = cpuhp_setup_state(CPUHP_AP_PERF_ONLINE, "AP_PERF_ONLINE",
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csky_pmu_starting_cpu,
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csky_pmu_dying_cpu);
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if (ret) {
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csky_pmu_free_irq();
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free_percpu(csky_pmu.hw_events);
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return ret;
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}
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ret = perf_pmu_register(&csky_pmu.pmu, "cpu", PERF_TYPE_RAW);
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if (ret) {
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csky_pmu_free_irq();
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free_percpu(csky_pmu.hw_events);
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}
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return ret;
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}
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